)]}'
{
  "commit": "c836732fa058a62bb8f30a7a03f776f6c488fa58",
  "tree": "2d970152b6cf195b22088d2f7a1fe52890c92012",
  "parents": [
    "70e4c234aa48e11c0575364939dfab4cb27b2172"
  ],
  "author": {
    "name": "Ralf Baechle",
    "email": "ralf@linux-mips.org",
    "time": "Thu May 22 09:55:02 2014 +0200"
  },
  "committer": {
    "name": "Ralf Baechle",
    "email": "ralf@linux-mips.org",
    "time": "Fri May 23 15:12:38 2014 +0200"
  },
  "message": "MIPS: c-r4k: Call R4600_HIT_CACHEOP_WAR_IMPL only for 32 byte cache lines.\n\nR4600_HIT_CACHEOP_WAR_IMPL is only needed on R4600 v1.6 and the R4600 has\ndata cache lines that are always 32 bytes so the call is pointless in\nr4k_blast_dcache_page_dc64.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1c74a6ad072a984be8005d7047ed7eb815ddb115",
      "old_mode": 33188,
      "old_path": "arch/mips/mm/c-r4k.c",
      "new_id": "7bc14ffc7a1c2049c79ef6768931826df63b7bce",
      "new_mode": 33188,
      "new_path": "arch/mips/mm/c-r4k.c"
    }
  ]
}