)]}'
{
  "commit": "cb1d220da0faa5ca0deb93449aff953f0c2cce6d",
  "tree": "98a3d02918490581660702135f186a368a4212c5",
  "parents": [
    "7cfc5c653b07782e7059527df8dc1e3143a7591e"
  ],
  "author": {
    "name": "Like Xu",
    "email": "likexu@tencent.com",
    "time": "Thu Nov 18 21:03:20 2021 +0800"
  },
  "committer": {
    "name": "Paolo Bonzini",
    "email": "pbonzini@redhat.com",
    "time": "Thu Dec 02 04:11:50 2021 -0500"
  },
  "message": "KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register\n\nIf we run the following perf command in an AMD Milan guest:\n\n  perf stat \\\n  -e cpu/event\u003d0x1d0/ \\\n  -e cpu/event\u003d0x1c7/ \\\n  -e cpu/umask\u003d0x1f,event\u003d0x18e/ \\\n  -e cpu/umask\u003d0x7,event\u003d0x18e/ \\\n  -e cpu/umask\u003d0x18,event\u003d0x18e/ \\\n  ./workload\n\ndmesg will report a #GP warning from an unchecked MSR access\nerror on MSR_F15H_PERF_CTLx.\n\nThis is because according to APM (Revision: 4.03) Figure 13-7,\nthe bits [35:32] of AMD PerfEvtSeln register is a part of the\nevent select encoding, which extends the EVENT_SELECT field\nfrom 8 bits to 12 bits.\n\nOpportunistically update pmu-\u003ereserved_bits for reserved bit 19.\n\nReported-by: Jim Mattson \u003cjmattson@google.com\u003e\nFixes: ca724305a2b0 (\"KVM: x86/vPMU: Implement AMD vPMU code for KVM\")\nSigned-off-by: Like Xu \u003clikexu@tencent.com\u003e\nMessage-Id: \u003c20211118130320.95997-1-likexu@tencent.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "871c426ec389a98632307b16d661c2abf5b856b0",
      "old_mode": 33188,
      "old_path": "arch/x86/kvm/svm/pmu.c",
      "new_id": "b4095dfeeee62fa1702c3aa48d2af059d03e4d28",
      "new_mode": 33188,
      "new_path": "arch/x86/kvm/svm/pmu.c"
    }
  ]
}