// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2017 NXP
 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
 */

#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx8mq-pinfunc.h"

/ {
	/* This should really be the GPC, but we need a driver for this first */
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
	};

	ckil: clock-ckil {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "ckil";
	};

	osc_25m: clock-osc-25m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
		clock-output-names = "osc_25m";
	};

	osc_27m: clock-osc-27m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
		clock-output-names = "osc_27m";
	};

	clk_ext1: clock-ext1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext1";
	};

	clk_ext2: clock-ext2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext2";
	};

	clk_ext3: clock-ext3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext3";
	};

	clk_ext4: clock-ext4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency= <133000000>;
		clock-output-names = "clk_ext4";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		A53_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
		};

		A53_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
		};

		A53_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
		};

		A53_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
		};

		A53_L2: l2-cache0 {
			compatible = "cache";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
		             <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
		             <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
		             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
		interrupt-parent = <&gic>;
		arm,no-tick-in-suspend;
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x3e000000>;

		bus@30000000 { /* AIPS1 */
			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30000000 0x30000000 0x400000>;

			gpio1: gpio@30200000 {
				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
				reg = <0x30200000 0x10000>;
				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@30210000 {
				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
				reg = <0x30210000 0x10000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@30220000 {
				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
				reg = <0x30220000 0x10000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@30230000 {
				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
				reg = <0x30230000 0x10000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio5: gpio@30240000 {
				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
				reg = <0x30240000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			iomuxc: iomuxc@30330000 {
				compatible = "fsl,imx8mq-iomuxc";
				reg = <0x30330000 0x10000>;
			};

			iomuxc_gpr: syscon@30340000 {
				compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
				reg = <0x30340000 0x10000>;
			};

			anatop: syscon@30360000 {
				compatible = "fsl,imx8mq-anatop", "syscon";
				reg = <0x30360000 0x10000>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			};

			clk: clock-controller@30380000 {
				compatible = "fsl,imx8mq-ccm";
				reg = <0x30380000 0x10000>;
				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				#clock-cells = <1>;
				clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
				         <&clk_ext1>, <&clk_ext2>,
				         <&clk_ext3>, <&clk_ext4>;
				clock-names = "ckil", "osc_25m", "osc_27m",
				              "clk_ext1", "clk_ext2",
				              "clk_ext3", "clk_ext4";
			};

			wdog1: watchdog@30280000 {
				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
				reg = <0x30280000 0x10000>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
				status = "disabled";
			};

			wdog2: watchdog@30290000 {
				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
				reg = <0x30290000 0x10000>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
				status = "disabled";
			};

			wdog3: watchdog@302a0000 {
				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
				reg = <0x302a0000 0x10000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
				status = "disabled";
			};
		};

		bus@30400000 { /* AIPS2 */
			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30400000 0x30400000 0x400000>;
		};

		bus@30800000 { /* AIPS3 */
			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30800000 0x30800000 0x400000>;

			uart1: serial@30860000 {
				compatible = "fsl,imx8mq-uart",
				             "fsl,imx6q-uart";
				reg = <0x30860000 0x10000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
				         <&clk IMX8MQ_CLK_UART1_ROOT>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart3: serial@30880000 {
				compatible = "fsl,imx8mq-uart",
				             "fsl,imx6q-uart";
				reg = <0x30880000 0x10000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
				         <&clk IMX8MQ_CLK_UART3_ROOT>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@30890000 {
				compatible = "fsl,imx8mq-uart",
				             "fsl,imx6q-uart";
				reg = <0x30890000 0x10000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
				         <&clk IMX8MQ_CLK_UART2_ROOT>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c1: i2c@30a20000 {
				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
				reg = <0x30a20000 0x10000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c2: i2c@30a30000 {
				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
				reg = <0x30a30000 0x10000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c3: i2c@30a40000 {
				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
				reg = <0x30a40000 0x10000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c4: i2c@30a50000 {
				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
				reg = <0x30a50000 0x10000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			uart4: serial@30a60000 {
				compatible = "fsl,imx8mq-uart",
				             "fsl,imx6q-uart";
				reg = <0x30a60000 0x10000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
				         <&clk IMX8MQ_CLK_UART4_ROOT>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			usdhc1: mmc@30b40000 {
				compatible = "fsl,imx8mq-usdhc",
				             "fsl,imx7d-usdhc";
				reg = <0x30b40000 0x10000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_DUMMY>,
				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@30b50000 {
				compatible = "fsl,imx8mq-usdhc",
				             "fsl,imx7d-usdhc";
				reg = <0x30b50000 0x10000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_DUMMY>,
				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
				         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			fec1: ethernet@30be0000 {
				compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
				reg = <0x30be0000 0x10000>;
				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
				         <&clk IMX8MQ_CLK_ENET1_ROOT>,
				         <&clk IMX8MQ_CLK_ENET_TIMER>,
				         <&clk IMX8MQ_CLK_ENET_REF>,
				         <&clk IMX8MQ_CLK_ENET_PHY_REF>;
				clock-names = "ipg", "ahb", "ptp",
				              "enet_clk_ref", "enet_out";
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				status = "disabled";
			};
		};

		gic: interrupt-controller@38800000 {
			compatible = "arm,gic-v3";
			reg = <0x38800000 0x10000>,	/* GIC Dist */
			      <0x38880000 0xc0000>,	/* GICR */
			      <0x31000000 0x2000>,	/* GICC */
			      <0x31010000 0x2000>,	/* GICV */
			      <0x31020000 0x2000>;	/* GICH */
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
		};
	};
};