drm/i915: Clean up PIPEMISC register defines
Use REG_BIT() & co. for PIPEMISC* bits, and while at it
fill in the missing dithering bits since we already had some
of them defined.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211112193813.8224-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 507cc3d..2d17112 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5308,32 +5308,35 @@ enum {
#define _PIPE_MISC_A 0x70030
#define _PIPE_MISC_B 0x71030
-#define PIPEMISC_YUV420_ENABLE (1 << 27) /* glk+ */
-#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
-#define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */
-#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
-#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
+#define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
+#define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
+#define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
+#define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
+#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
/*
* For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
* valid values of: 6, 8, 10 BPC.
* ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
* 6, 8, 10, 12 BPC.
*/
-#define PIPEMISC_BPC_MASK (7 << 5)
-#define PIPEMISC_8_BPC (0 << 5)
-#define PIPEMISC_10_BPC (1 << 5)
-#define PIPEMISC_6_BPC (2 << 5)
-#define PIPEMISC_12_BPC_ADLP (4 << 5) /* adlp+ */
-#define PIPEMISC_DITHER_ENABLE (1 << 4)
-#define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
-#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
+#define PIPEMISC_BPC_MASK REG_GENMASK(7, 5)
+#define PIPEMISC_BPC_8 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
+#define PIPEMISC_BPC_10 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
+#define PIPEMISC_BPC_6 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
+#define PIPEMISC_BPC_12_ADLP REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
+#define PIPEMISC_DITHER_ENABLE REG_BIT(4)
+#define PIPEMISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
+#define PIPEMISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
+#define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
+#define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
+#define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
#define _PIPE_MISC2_A 0x7002C
#define _PIPE_MISC2_B 0x7102C
-#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN (0x50 << 24)
-#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS (0x14 << 24)
-#define PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK (0xff << 24)
+#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
+#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
+#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
#define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A)
/* Skylake+ pipe bottom (background) color */
