| commit | d25cbd3e392730f459f1fbf5f959c16b460a59ca | [log] [tgz] |
|---|---|---|
| author | Peng Fan <peng.fan@nxp.com> | Fri Feb 25 16:17:31 2022 +0800 |
| committer | Abel Vesa <abel.vesa@nxp.com> | Fri Mar 04 17:06:29 2022 +0200 |
| tree | e5d8ad309098a5dc2227fd1f7459be837e1ace2d | |
| parent | 24defbe194b650218680fcd9dec8cd103537b531 [diff] |
clk: imx8mm: remove SYS PLL 1/2 clock gates Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220225081733.2294166-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>