| commit | d4b95c445cab0fb583eed7caafbc1b734f6a3a59 | [log] [tgz] |
|---|---|---|
| author | Emil Renner Berthing <emil.renner.berthing@canonical.com> | Thu Nov 30 16:19:28 2023 +0100 |
| committer | Conor Dooley <conor.dooley@microchip.com> | Wed Dec 13 15:50:23 2023 +0000 |
| tree | be378d740f95deca4270369291edb73d6fe1fc2c | |
| parent | ba0074972ee9b3231b3de44650583654422e9758 [diff] |
riscv: dts: starfive: Add JH7100 cache controller The StarFive JH7100 SoC also features the SiFive L2 cache controller, so add the device tree nodes for it. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>