tree be378d740f95deca4270369291edb73d6fe1fc2c
parent ba0074972ee9b3231b3de44650583654422e9758
author Emil Renner Berthing <emil.renner.berthing@canonical.com> 1701357568 +0100
committer Conor Dooley <conor.dooley@microchip.com> 1702482623 +0000

riscv: dts: starfive: Add JH7100 cache controller

The StarFive JH7100 SoC also features the SiFive L2 cache controller,
so add the device tree nodes for it.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>