Tegra TPM driver with HW flow control
Merge series from Krishna Yarlagadda <kyarlagadda@nvidia.com>:
TPM devices may insert wait state on last clock cycle of ADDR phase.
For SPI controllers that support full-duplex transfers, this can be
detected using software by reading the MISO line. For SPI controllers
that only support half-duplex transfers, such as the Tegra QSPI, it is
not possible to detect the wait signal from software. The QSPI
controller in Tegra234 and Tegra241 implement hardware detection of the
wait signal which can be enabled in the controller for TPM devices.
Add a flag for this in the SPI core and implement support in the Tegra
QuadSPI driver.
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index 96633a0..9939593 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -617,7 +617,6 @@ static void bcm63xx_spi_remove(struct platform_device *pdev)
clk_disable_unprepare(bs->clk);
}
-#ifdef CONFIG_PM_SLEEP
static int bcm63xx_spi_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
@@ -644,7 +643,6 @@ static int bcm63xx_spi_resume(struct device *dev)
return 0;
}
-#endif
static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
