)]}'
{
  "commit": "d9f3a60ebbbd7244fe532dc8dcd278ac1651247f",
  "tree": "cfe25840fabfe73ab0a6026799002934ee69cffd",
  "parents": [
    "25f0617109496e1aff49594fbae5644286447a0f",
    "967ca91a996f82219f2883e9e53d8e20df49025a"
  ],
  "author": {
    "name": "Mark Brown",
    "email": "broonie@kernel.org",
    "time": "Mon Apr 24 12:59:47 2023 +0100"
  },
  "committer": {
    "name": "Mark Brown",
    "email": "broonie@kernel.org",
    "time": "Mon Apr 24 12:59:47 2023 +0100"
  },
  "message": "Tegra TPM driver with HW flow control\n\nMerge series from Krishna Yarlagadda \u003ckyarlagadda@nvidia.com\u003e:\n\nTPM devices may insert wait state on last clock cycle of ADDR phase.\nFor SPI controllers that support full-duplex transfers, this can be\ndetected using software by reading the MISO line. For SPI controllers\nthat only support half-duplex transfers, such as the Tegra QSPI, it is\nnot possible to detect the wait signal from software. The QSPI\ncontroller in Tegra234 and Tegra241 implement hardware detection of the\nwait signal which can be enabled in the controller for TPM devices.\n\nAdd a flag for this in the SPI core and implement support in the Tegra\nQuadSPI driver.\n",
  "tree_diff": []
}