tree 7cbb0b1ce047c514f92da5ef382ca0bc6002cf21
parent c5600b2dd9fc7318feddf69f127ca793437c714d
author Al Cooper <alcooperx@gmail.com> 1342212291 -0400
committer Ralf Baechle <ralf@linux-mips.org> 1349946274 +0200

MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)

The PCI (Program Counter Interrupt) bit in the "cause" register
is mandatory for MIPS32R2 cores, but has also been added to some R1
cores (BMIPS5000). This change adds a cpu feature bit to make it
easier to check for and use this feature.

Signed-off-by: Al Cooper <alcooperx@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/4106/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>