// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
 *
 * Copyright (C) 2021 Renesas Electronics Corp.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a07g044-cpg.h>

/ {
	compatible = "renesas,r9a07g044";
	#address-cells = <2>;
	#size-cells = <2>;

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			reg = <0>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
		};

		cpu1: cpu@100 {
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
		};

		L3_CA55: cache-controller-0 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x40000>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		scif0: serial@1004b800 {
			compatible = "renesas,scif-r9a07g044";
			reg = <0 0x1004b800 0 0x400>;
			interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
			clock-names = "fck";
			power-domains = <&cpg>;
			resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
			status = "disabled";
		};

		canfd: can@10050000 {
			compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
			reg = <0 0x10050000 0 0x8000>;
			interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "g_err", "g_recc",
					  "ch0_err", "ch0_rec", "ch0_trx",
					  "ch1_err", "ch1_rec", "ch1_trx";
			clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
				 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
				 <&can_clk>;
			clock-names = "fck", "canfd", "can_clk";
			assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
			assigned-clock-rates = <50000000>;
			resets = <&cpg R9A07G044_CANFD_RSTP_N>,
				 <&cpg R9A07G044_CANFD_RSTC_N>;
			reset-names = "rstp_n", "rstc_n";
			power-domains = <&cpg>;
			status = "disabled";

			channel0 {
				status = "disabled";
			};
			channel1 {
				status = "disabled";
			};
		};

		i2c0: i2c@10058000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
			reg = <0 0x10058000 0 0x400>;
			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
			clock-frequency = <100000>;
			resets = <&cpg R9A07G044_I2C0_MRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c1: i2c@10058400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
			reg = <0 0x10058400 0 0x400>;
			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
			clock-frequency = <100000>;
			resets = <&cpg R9A07G044_I2C1_MRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c2: i2c@10058800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
			reg = <0 0x10058800 0 0x400>;
			interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
			clock-frequency = <100000>;
			resets = <&cpg R9A07G044_I2C2_MRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c3: i2c@10058c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
			reg = <0 0x10058c00 0 0x400>;
			interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
			clock-frequency = <100000>;
			resets = <&cpg R9A07G044_I2C3_MRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		adc: adc@10059000 {
			compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
			reg = <0 0x10059000 0 0x400>;
			interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
				 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
			clock-names = "adclk", "pclk";
			resets = <&cpg R9A07G044_ADC_PRESETN>,
				 <&cpg R9A07G044_ADC_ADRST_N>;
			reset-names = "presetn", "adrst-n";
			power-domains = <&cpg>;
			status = "disabled";

			#address-cells = <1>;
			#size-cells = <0>;

			channel@0 {
				reg = <0>;
			};
			channel@1 {
				reg = <1>;
			};
			channel@2 {
				reg = <2>;
			};
			channel@3 {
				reg = <3>;
			};
			channel@4 {
				reg = <4>;
			};
			channel@5 {
				reg = <5>;
			};
			channel@6 {
				reg = <6>;
			};
			channel@7 {
				reg = <7>;
			};
		};

		cpg: clock-controller@11010000 {
			compatible = "renesas,r9a07g044-cpg";
			reg = <0 0x11010000 0 0x10000>;
			clocks = <&extal_clk>;
			clock-names = "extal";
			#clock-cells = <2>;
			#reset-cells = <1>;
			#power-domain-cells = <0>;
		};

		sysc: system-controller@11020000 {
			compatible = "renesas,r9a07g044-sysc";
			reg = <0 0x11020000 0 0x10000>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "lpm_int", "ca55stbydone_int",
					  "cm33stbyr_int", "ca55_deny";
			status = "disabled";
		};

		pinctrl: pin-controller@11030000 {
			compatible = "renesas,r9a07g044-pinctrl";
			reg = <0 0x11030000 0 0x10000>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 392>;
			clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
			power-domains = <&cpg>;
			resets = <&cpg R9A07G044_GPIO_RSTN>,
				 <&cpg R9A07G044_GPIO_PORT_RESETN>,
				 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
		};

		gic: interrupt-controller@11900000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0x11900000 0 0x40000>,
			      <0x0 0x11940000 0 0x60000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};
};