tree c296cb097c801ef64ee182a59978d3e541e700e8
parent 81bc3009e061cfd0e62e03a6761cce39c750b65e
parent 3c424f359898aff48c3d5bed608ac706f8a528c3
author Linus Torvalds <torvalds@linux-foundation.org> 1327786030 -0800
committer Linus Torvalds <torvalds@linux-foundation.org> 1327786030 -0800

Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm

* 'fixes' of git://git.linaro.org/people/rmk/linux-arm: (31 commits)
  ARM: 7304/1: ioremap: fix boundary check when reusing static mapping
  ARM: 7301/1: Rename the T() macro to TUSER() to avoid namespace conflicts
  ARM: 7299/1: ftrace: clear zero bit in reported IPs for Thumb-2
  ARM: 7298/1: realview: fix mapping of MPCore private memory region
  PCMCIA: fix sa1111 oops on remove
  ARM: 7288/1: mach-sa1100: add missing module_init() call
  ARM: 7297/1: smp_twd: make sure timer is stopped before registering it
  ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards
  ARM: 7295/1: cortex-a7: move proc_info out of !CONFIG_ARM_LPAE block
  ARM: 7293/1: logical_cpu_map: decouple CPU mapping from SMP
  ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs
  ARM: 7290/1: vmlinux.lds.S: align the exception fixup table to a 4-byte boundary
  ARM: 7289/1: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes
  MFD: ucb1x00-ts: fix resume failure
  MFD: ucb1x00-core: fix gpiolib direction_output handling
  MFD: ucb1x00-core: fix missing restore of io output data on resume
  MFD: mcp-core: fix mcp_priv() to be more type safe
  MFD: mcp-core: fix complaints from the genirq layer
  Revert "ARM: sa11x0: Implement autoloading of codec and codec pdata for mcp bus."
  Revert "ARM: sa1100: Refactor mcp-sa11x0 to use platform resources."
  ...

Fix up conflict due to arch/arm/mach-mx5/Kconfig having been merged into
mach-imx5 (commit 784a90c0a7d8: "ARM i.MX: Merge i.MX5 support into
mach-imx"), but the ARM_L1_CACHE_SHIFT_6 entry was moved to be driven by
the CPU_V7 logic from it in the old location in rmk's branch (commit
a092f2b15399: "ARM: 7291/1: cache: assume 64-byte L1 cachelines for
ARMv7 CPUs").