| [ |
| { |
| "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", |
| "EventCode": "0x80", |
| "EventName": "ICACHE.ACCESSES", |
| "SampleAfterValue": "200003", |
| "UMask": "0x3", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", |
| "EventCode": "0x80", |
| "EventName": "ICACHE.MISSES", |
| "SampleAfterValue": "200003", |
| "UMask": "0x2", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.", |
| "EventCode": "0x9c", |
| "EventName": "IDQ_BUBBLES.CORE", |
| "PublicDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.\nThe count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| } |
| ] |
