tree f0bd0b6e0911b841a1eee0549e4e91530fa894a1
parent 94ebc035456a4ccacfbbef60c444079a256623ad
author Shen, George <George.Shen@amd.com> 1637033898 -0500
committer Alex Deucher <alexander.deucher@amd.com> 1638396326 -0500

drm/amd/display: Clear DPCD lane settings after repeater training

[Why]
VS and PE requested by repeater should not persist for the sink.

[How]
Clear DPCD lane settings after repeater link training finishes.

Reviewed-by: Wesley Chalmers <wesley.chalmers@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: George Shen <George.Shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>