[
    {
        "BriefDescription": "Uncore cache clock ticks",
        "Counter": "0,1,2,3",
        "EventName": "UNC_CHA_CLOCKTICKS",
        "PerPkg": "1",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss",
        "Counter": "0,1,2,3",
        "EventCode": "0x35",
        "EventName": "LLC_MISSES.UNCACHEABLE",
        "Filter": "config1=0x40e33",
        "PerPkg": "1",
        "UMask": "0x21",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
        "Counter": "0,1,2,3",
        "EventCode": "0x35",
        "EventName": "LLC_MISSES.MMIO_READ",
        "Filter": "config1=0x40040e33",
        "PerPkg": "1",
        "UMask": "0x21",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
        "Counter": "0,1,2,3",
        "EventCode": "0x35",
        "EventName": "LLC_MISSES.MMIO_WRITE",
        "Filter": "config1=0x40041e33",
        "PerPkg": "1",
        "UMask": "0x21",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
        "Counter": "0,1,2,3",
        "EventCode": "0x35",
        "EventName": "LLC_REFERENCES.STREAMING_FULL",
        "Filter": "config1=0x41833",
        "PerPkg": "1",
        "ScaleUnit": "64Bytes",
        "UMask": "0x21",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
        "Counter": "0,1,2,3",
        "EventCode": "0x35",
        "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
        "Filter": "config1=0x41a33",
        "PerPkg": "1",
        "ScaleUnit": "64Bytes",
        "UMask": "0x21",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "read requests from home agent",
        "Counter": "0,1,2,3",
        "EventCode": "0x50",
        "EventName": "UNC_CHA_REQUESTS.READS",
        "PerPkg": "1",
        "UMask": "0x03",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "read requests from local home agent",
        "Counter": "0,1,2,3",
        "EventCode": "0x50",
        "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
        "PerPkg": "1",
        "UMask": "0x01",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "read requests from remote home agent",
        "Counter": "0,1,2,3",
        "EventCode": "0x50",
        "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
        "PerPkg": "1",
        "UMask": "0x02",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "write requests from home agent",
        "Counter": "0,1,2,3",
        "EventCode": "0x50",
        "EventName": "UNC_CHA_REQUESTS.WRITES",
        "PerPkg": "1",
        "UMask": "0x0C",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "write requests from local home agent",
        "Counter": "0,1,2,3",
        "EventCode": "0x50",
        "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
        "PerPkg": "1",
        "UMask": "0x04",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data",
        "Counter": "0,1,2,3",
        "EventCode": "0x2",
        "EventName": "UPI_DATA_BANDWIDTH_TX",
        "PerPkg": "1",
        "ScaleUnit": "7.11E-06Bytes",
        "UMask": "0xf",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "ScaleUnit": "4Bytes",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "ScaleUnit": "4Bytes",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "ScaleUnit": "4Bytes",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "ScaleUnit": "4Bytes",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "LLC_MISSES.PCIE_WRITE",
        "FCMask": "0x07",
        "Filter": "ch_mask=0x1f",
        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
        "MetricName": "LLC_MISSES.PCIE_WRITE",
        "PerPkg": "1",
        "PortMask": "0x01",
        "ScaleUnit": "4Bytes",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "ScaleUnit": "4Bytes",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "ScaleUnit": "4Bytes",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "ScaleUnit": "4Bytes",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "ScaleUnit": "4Bytes",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "LLC_MISSES.PCIE_READ",
        "FCMask": "0x07",
        "Filter": "ch_mask=0x1f",
        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
        "MetricName": "LLC_MISSES.PCIE_READ",
        "PerPkg": "1",
        "PortMask": "0x01",
        "ScaleUnit": "4Bytes",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests",
        "Counter": "0,1,2,3",
        "EventCode": "0x33",
        "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
        "PerPkg": "1",
        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
        "UMask": "0x42",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction",
        "Counter": "0,1,2,3",
        "EventCode": "0x33",
        "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
        "PerPkg": "1",
        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
        "UMask": "0x82",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
        "Counter": "0,1,2,3",
        "EventCode": "0x53",
        "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
        "PerPkg": "1",
        "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed",
        "UMask": "0x02",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
        "Counter": "0,1,2,3",
        "EventCode": "0x53",
        "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
        "PerPkg": "1",
        "PublicDescription": "Counts  transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed",
        "UMask": "0x01",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "UNC_CHA_DIR_UPDATE.HA",
        "PerPkg": "1",
        "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
        "UMask": "0x01",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
        "Counter": "0,1,2,3",
        "EventCode": "0x54",
        "EventName": "UNC_CHA_DIR_UPDATE.TOR",
        "PerPkg": "1",
        "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
        "UMask": "0x02",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "FaST wire asserted; Horizontal",
        "Counter": "0,1,2,3",
        "EventCode": "0xA5",
        "EventName": "UNC_CHA_FAST_ASSERTED.HORZ",
        "PerPkg": "1",
        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
        "UMask": "0x02",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
        "Counter": "0,1,2,3",
        "EventCode": "0x5F",
        "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
        "PerPkg": "1",
        "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state.  This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)",
        "UMask": "0x01",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
        "Counter": "0,1,2,3",
        "EventCode": "0x59",
        "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
        "PerPkg": "1",
        "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.",
        "UMask": "0x01",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
        "Counter": "0,1,2,3",
        "EventCode": "0x5B",
        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
        "PerPkg": "1",
        "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.",
        "UMask": "0x01",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Lines Victimized; Lines in E state",
        "Counter": "0,1,2,3",
        "EventCode": "0x37",
        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
        "PerPkg": "1",
        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
        "UMask": "0x02",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Lines Victimized; Lines in F State",
        "Counter": "0,1,2,3",
        "EventCode": "0x37",
        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F",
        "PerPkg": "1",
        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
        "UMask": "0x08",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Lines Victimized; Lines in M state",
        "Counter": "0,1,2,3",
        "EventCode": "0x37",
        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
        "PerPkg": "1",
        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
        "UMask": "0x01",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Lines Victimized; Lines in S State",
        "Counter": "0,1,2,3",
        "EventCode": "0x37",
        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
        "PerPkg": "1",
        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
        "UMask": "0x04",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Number of times that an RFO hit in S state.",
        "Counter": "0,1,2,3",
        "EventCode": "0x39",
        "EventName": "UNC_CHA_MISC.RFO_HIT_S",
        "PerPkg": "1",
        "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a  write) request hit a cacheline in the S (Shared) state.",
        "UMask": "0x08",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Local requests for exclusive ownership of a cache line  without receiving data",
        "Counter": "0,1,2,3",
        "EventCode": "0x50",
        "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
        "PerPkg": "1",
        "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
        "UMask": "0x10",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
        "Counter": "0,1,2,3",
        "EventCode": "0x50",
        "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
        "PerPkg": "1",
        "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
        "UMask": "0x20",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Ingress (from CMS) Allocations; IRQ",
        "Counter": "0,1,2,3",
        "EventCode": "0x13",
        "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
        "PerPkg": "1",
        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
        "UMask": "0x01",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
        "Counter": "0,1,2,3",
        "EventCode": "0x19",
        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
        "PerPkg": "1",
        "PublicDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
        "UMask": "0x80",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Ingress (from CMS) Occupancy; IRQ",
        "EventCode": "0x11",
        "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
        "PerPkg": "1",
        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
        "UMask": "0x01",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Snoop filter capacity evictions for E-state entries.",
        "Counter": "0,1,2,3",
        "EventCode": "0x3D",
        "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
        "PerPkg": "1",
        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
        "UMask": "0x02",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Snoop filter capacity evictions for M-state entries.",
        "Counter": "0,1,2,3",
        "EventCode": "0x3D",
        "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
        "PerPkg": "1",
        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
        "UMask": "0x01",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Snoop filter capacity evictions for S-state entries.",
        "Counter": "0,1,2,3",
        "EventCode": "0x3D",
        "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
        "PerPkg": "1",
        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
        "UMask": "0x04",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "RspCnflct* Snoop Responses Received",
        "Counter": "0,1,2,3",
        "EventCode": "0x5C",
        "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
        "PerPkg": "1",
        "PublicDescription": "Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI.",
        "UMask": "0x40",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "RspI Snoop Responses Received",
        "Counter": "0,1,2,3",
        "EventCode": "0x5C",
        "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
        "PerPkg": "1",
        "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).",
        "UMask": "0x01",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "RspIFwd Snoop Responses Received",
        "Counter": "0,1,2,3",
        "EventCode": "0x5C",
        "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
        "PerPkg": "1",
        "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states.  This is commonly returned with RFO (the Read for Ownership issued before a write) transactions.  The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward)  states.",
        "UMask": "0x04",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "RspSFwd Snoop Responses Received",
        "Counter": "0,1,2,3",
        "EventCode": "0x5C",
        "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
        "PerPkg": "1",
        "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy.  This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
        "UMask": "0x08",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received",
        "Counter": "0,1,2,3",
        "EventCode": "0x5C",
        "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
        "PerPkg": "1",
        "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to it's home socket, and the cacheline was forwarded to the requestor socket.  This snoop response is only used in >= 4 socket systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to it's home socket to be written back to memory.",
        "UMask": "0x20",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Rsp*WB Snoop Responses Received",
        "Counter": "0,1,2,3",
        "EventCode": "0x5C",
        "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB",
        "PerPkg": "1",
        "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home.  This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured.  This reponse will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.",
        "UMask": "0x10",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
        "Counter": "0,1,2,3",
        "EventCode": "0x35",
        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
        "Filter": "config1=0x40433",
        "PerPkg": "1",
        "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
        "UMask": "0x21",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
        "EventCode": "0x36",
        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
        "Filter": "config1=0x40433",
        "PerPkg": "1",
        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
        "UMask": "0x21",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Clockticks of the IIO Traffic Controller",
        "Counter": "0,1,2,3",
        "EventCode": "0x1",
        "EventName": "UNC_IIO_CLOCKTICKS",
        "PerPkg": "1",
        "PublicDescription": "Counts clockticks of the 1GHz trafiic controller clock in the IIO unit.",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
        "Counter": "0,1,2,3",
        "EventCode": "0xC2",
        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
        "FCMask": "0x4",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
        "UMask": "0x03",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
        "Counter": "0,1,2,3",
        "EventCode": "0xC2",
        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
        "FCMask": "0x4",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
        "UMask": "0x03",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
        "Counter": "0,1,2,3",
        "EventCode": "0xC2",
        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
        "FCMask": "0x4",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
        "UMask": "0x03",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
        "Counter": "0,1,2,3",
        "EventCode": "0xC2",
        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
        "FCMask": "0x4",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
        "UMask": "0x03",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
        "Counter": "2,3",
        "EventCode": "0xD5",
        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
        "FCMask": "0x04",
        "PerPkg": "1",
        "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1",
        "Counter": "2,3",
        "EventCode": "0xD5",
        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
        "FCMask": "0x04",
        "PerPkg": "1",
        "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2",
        "Counter": "2,3",
        "EventCode": "0xD5",
        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
        "FCMask": "0x04",
        "PerPkg": "1",
        "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3",
        "Counter": "2,3",
        "EventCode": "0xD5",
        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
        "FCMask": "0x04",
        "PerPkg": "1",
        "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit.  In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit",
        "Counter": "2,3",
        "EventCode": "0xC0",
        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
        "Counter": "0,1",
        "EventCode": "0x83",
        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit",
        "Counter": "0,1,2,3",
        "EventCode": "0xC1",
        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Read request for up to a 64 byte transaction is  made by IIO Part1 to Memory",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x04",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x01",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x08",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x01",
        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x02",
        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x04",
        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
        "FCMask": "0x07",
        "PerPkg": "1",
        "PortMask": "0x08",
        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
        "UMask": "0x02",
        "Unit": "IIO"
    },
    {
        "BriefDescription": "Total IRP occupancy of inbound read and write requests.",
        "Counter": "0,1",
        "EventCode": "0xF",
        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
        "PerPkg": "1",
        "PublicDescription": "Total IRP occupancy of inbound read and write requests.  This is effectively the sum of read occupancy and write occupancy.",
        "UMask": "0x4",
        "Unit": "IRP"
    },
    {
        "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
        "Counter": "0,1",
        "EventCode": "0x10",
        "EventName": "UNC_I_COHERENT_OPS.PCITOM",
        "PerPkg": "1",
        "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO.  PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
        "UMask": "0x10",
        "Unit": "IRP"
    },
    {
        "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
        "Counter": "0,1",
        "EventCode": "0x10",
        "EventName": "UNC_I_COHERENT_OPS.RFO",
        "PerPkg": "1",
        "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory.  RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
        "UMask": "0x8",
        "Unit": "IRP"
    },
    {
        "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
        "Counter": "0,1",
        "EventCode": "0x18",
        "EventName": "UNC_I_FAF_INSERTS",
        "PerPkg": "1",
        "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.",
        "Unit": "IRP"
    },
    {
        "BriefDescription": "Occupancy of the IRP FAF queue.",
        "Counter": "0,1",
        "EventCode": "0x19",
        "EventName": "UNC_I_FAF_OCCUPANCY",
        "PerPkg": "1",
        "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.",
        "Unit": "IRP"
    },
    {
        "BriefDescription": "Inbound write (fast path) requests received by the IRP.",
        "Counter": "0,1",
        "EventCode": "0x11",
        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
        "PerPkg": "1",
        "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
        "UMask": "0x8",
        "Unit": "IRP"
    },
    {
        "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken",
        "Counter": "0,1,2,3",
        "EventCode": "0x22",
        "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN",
        "PerPkg": "1",
        "PublicDescription": "Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken",
        "UMask": "0x2",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
        "PerPkg": "1",
        "PublicDescription": "Counts cycles when direct to core mode (which bypasses the CHA) was disabled",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
        "Counter": "0,1,2,3",
        "EventCode": "0x23",
        "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
        "PerPkg": "1",
        "PublicDescription": "Counts when messages were sent direct to core (bypassing the CHA)",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Number of reads in which direct to core transaction were overridden",
        "Counter": "0,1,2,3",
        "EventCode": "0x25",
        "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
        "PerPkg": "1",
        "PublicDescription": "Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
        "Counter": "0,1,2,3",
        "EventCode": "0x28",
        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
        "PerPkg": "1",
        "PublicDescription": "Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Cycles when direct to Intel UPI was disabled",
        "Counter": "0,1,2,3",
        "EventCode": "0x27",
        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
        "PerPkg": "1",
        "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabled",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Messages sent direct to the Intel UPI",
        "Counter": "0,1,2,3",
        "EventCode": "0x26",
        "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
        "PerPkg": "1",
        "PublicDescription": "Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA)",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
        "Counter": "0,1,2,3",
        "EventCode": "0x29",
        "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
        "PerPkg": "1",
        "PublicDescription": "Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
        "Counter": "0,1,2,3",
        "EventCode": "0x2D",
        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)",
        "UMask": "0x1",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
        "Counter": "0,1,2,3",
        "EventCode": "0x2D",
        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data.  The data may be stored in any state in the local socket.",
        "UMask": "0x8",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
        "Counter": "0,1,2,3",
        "EventCode": "0x2D",
        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socket.",
        "UMask": "0x2",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
        "Counter": "0,1,2,3",
        "EventCode": "0x2D",
        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socket.",
        "UMask": "0x4",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory update from A to I",
        "Counter": "0,1,2,3",
        "EventCode": "0x2E",
        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to I (Invalid)",
        "UMask": "0x20",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory update from A to S",
        "Counter": "0,1,2,3",
        "EventCode": "0x2E",
        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to S (Shared)",
        "UMask": "0x40",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
        "Counter": "0,1,2,3",
        "EventCode": "0x2E",
        "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state",
        "UMask": "0x1",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory update from I to A",
        "Counter": "0,1,2,3",
        "EventCode": "0x2E",
        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to A (SnoopAll)",
        "UMask": "0x4",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory update from I to S",
        "Counter": "0,1,2,3",
        "EventCode": "0x2E",
        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to S (Shared)",
        "UMask": "0x2",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory update from S to A",
        "Counter": "0,1,2,3",
        "EventCode": "0x2E",
        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to A (SnoopAll)",
        "UMask": "0x10",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Multi-socket cacheline Directory update from S to I",
        "Counter": "0,1,2,3",
        "EventCode": "0x2E",
        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to I (Invalid)",
        "UMask": "0x8",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Reads to iMC issued",
        "Counter": "0,1,2,3",
        "EventCode": "0x37",
        "EventName": "UNC_M2M_IMC_READS.ALL",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).",
        "UMask": "0x4",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)",
        "Counter": "0,1,2,3",
        "EventCode": "0x37",
        "EventName": "UNC_M2M_IMC_READS.NORMAL",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).  It only counts  normal priority non-isochronous reads.",
        "UMask": "0x1",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Read requests to Intel Optane DC persistent memory issued to the iMC from M2M",
        "Counter": "0,1,2,3",
        "EventCode": "0x37",
        "EventName": "UNC_M2M_IMC_READS.TO_PMM",
        "PerPkg": "1",
        "PublicDescription": "M2M Reads Issued to iMC; All, regardless of priority.",
        "UMask": "0x8",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Writes to iMC issued",
        "Counter": "0,1,2,3",
        "EventCode": "0x38",
        "EventName": "UNC_M2M_IMC_WRITES.ALL",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller).",
        "UMask": "0x10",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
        "Counter": "0,1,2,3",
        "EventCode": "0x38",
        "EventName": "UNC_M2M_IMC_WRITES.NI",
        "PerPkg": "1",
        "PublicDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
        "UMask": "0x80",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Partial Non-Isochronous writes to the iMC",
        "Counter": "0,1,2,3",
        "EventCode": "0x38",
        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller).  It only counts normal priority non-isochronous writes.",
        "UMask": "0x2",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Write requests to Intel Optane DC persistent memory issued to the iMC from M2M",
        "Counter": "0,1,2,3",
        "EventCode": "0x38",
        "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
        "PerPkg": "1",
        "PublicDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
        "UMask": "0x20",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Prefecth requests that got turn into a demand request",
        "Counter": "0,1,2,3",
        "EventCode": "0x56",
        "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address.  Explanatory Side Note: The Prefecth queue is made of CAM (Content Addressable Memory)",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Inserts into the Memory Controller Prefetch Queue",
        "Counter": "0,1,2,3",
        "EventCode": "0x57",
        "EventName": "UNC_M2M_PREFCAM_INSERTS",
        "PerPkg": "1",
        "PublicDescription": "Counts when the M2M (Mesh to Memory) recieves a prefetch request and inserts it into its outstanding prefetch queue.  Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "AD Ingress (from CMS) Queue Inserts",
        "Counter": "0,1,2,3",
        "EventCode": "0x1",
        "EventName": "UNC_M2M_RxC_AD_INSERTS",
        "PerPkg": "1",
        "PublicDescription": "Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop).  This is generally used for reads, and",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "AD Ingress (from CMS) Occupancy",
        "Counter": "0,1,2,3",
        "EventCode": "0x2",
        "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
        "PerPkg": "1",
        "PublicDescription": "AD Ingress (from CMS) Occupancy",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "BL Ingress (from CMS) Allocations",
        "Counter": "0,1,2,3",
        "EventCode": "0x5",
        "EventName": "UNC_M2M_RxC_BL_INSERTS",
        "PerPkg": "1",
        "PublicDescription": "BL Ingress (from CMS) Allocations",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "BL Ingress (from CMS) Occupancy",
        "Counter": "0,1,2,3",
        "EventCode": "0x6",
        "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
        "PerPkg": "1",
        "PublicDescription": "BL Ingress (from CMS) Occupancy",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x2C",
        "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
        "PerPkg": "1",
        "PublicDescription": "Tag Hit; Read Hit from NearMem, Dirty  Line",
        "UMask": "0x02",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x2C",
        "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
        "PerPkg": "1",
        "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Clean Line",
        "UMask": "0x04",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x2C",
        "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
        "PerPkg": "1",
        "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Dirty  Line",
        "UMask": "0x08",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "AD Egress (to CMS) Allocations",
        "Counter": "0,1,2,3",
        "EventCode": "0x9",
        "EventName": "UNC_M2M_TxC_AD_INSERTS",
        "PerPkg": "1",
        "PublicDescription": "AD Egress (to CMS) Allocations",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "AD Egress (to CMS) Occupancy",
        "Counter": "0,1,2,3",
        "EventCode": "0xA",
        "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
        "PerPkg": "1",
        "PublicDescription": "AD Egress (to CMS) Occupancy",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "BL Egress (to CMS) Allocations; All",
        "Counter": "0,1,2,3",
        "EventCode": "0x15",
        "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
        "PerPkg": "1",
        "PublicDescription": "BL Egress (to CMS) Allocations; All",
        "UMask": "0x03",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "BL Egress (to CMS) Occupancy; All",
        "Counter": "0,1,2,3",
        "EventCode": "0x16",
        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL",
        "PerPkg": "1",
        "PublicDescription": "BL Egress (to CMS) Occupancy; All",
        "UMask": "0x03",
        "Unit": "M2M"
    },
    {
        "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.",
        "Counter": "0,1,2",
        "EventCode": "0x29",
        "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
        "PerPkg": "1",
        "PublicDescription": "Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)",
        "Unit": "M3UPI"
    },
    {
        "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)",
        "Counter": "0,1,2,3",
        "EventCode": "0x1",
        "EventName": "UNC_UPI_CLOCKTICKS",
        "PerPkg": "1",
        "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI).  This clock runs at1/8th the 'GT/s' speed of the UPI link.  For example, a  9.6GT/s  link will have a fixed Frequency of 1.2 Ghz.",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "Data Response packets that go direct to core",
        "Counter": "0,1,2,3",
        "EventCode": "0x12",
        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
        "PerPkg": "1",
        "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA.",
        "UMask": "0x1",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "Data Response packets that go direct to Intel UPI",
        "Counter": "0,1,2,3",
        "EventCode": "0x12",
        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U",
        "PerPkg": "1",
        "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA .",
        "UMask": "0x2",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)",
        "Counter": "0,1,2,3",
        "EventCode": "0x21",
        "EventName": "UNC_UPI_L1_POWER_CYCLES",
        "PerPkg": "1",
        "PublicDescription": "Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode.  L1 is a mode that totally shuts down the UPI link.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x25",
        "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
        "PerPkg": "1",
        "PublicDescription": "Counts cycles when the the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
        "Counter": "0,1,2,3",
        "EventCode": "0x31",
        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
        "PerPkg": "1",
        "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
        "UMask": "0x1",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
        "Counter": "0,1,2,3",
        "EventCode": "0x31",
        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
        "PerPkg": "1",
        "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer  (Receive Queue) and passed directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
        "UMask": "0x2",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "FLITs received which bypassed the Slot0 Recieve Buffer",
        "Counter": "0,1,2,3",
        "EventCode": "0x31",
        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
        "PerPkg": "1",
        "PublicDescription": "Counts incoming FLITs (FLow control unITs) whcih bypassed the slot2 RxQ buffer (Receive Queue)  and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
        "UMask": "0x4",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "Valid data FLITs received from any slot",
        "Counter": "0,1,2,3",
        "EventCode": "0x3",
        "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
        "PerPkg": "1",
        "PublicDescription": "Counts valid data FLITs  (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.",
        "UMask": "0x0F",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "Null FLITs received from any slot",
        "Counter": "0,1,2,3",
        "EventCode": "0x3",
        "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
        "PerPkg": "1",
        "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.",
        "UMask": "0x27",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "Protocol header and credit FLITs received from any slot",
        "Counter": "0,1,2,3",
        "EventCode": "0x3",
        "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
        "PerPkg": "1",
        "PublicDescription": "Counts protocol header and credit FLITs  (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit.",
        "UMask": "0x97",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x27",
        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
        "PerPkg": "1",
        "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "FLITs that bypassed the TxL Buffer",
        "Counter": "0,1,2,3",
        "EventCode": "0x41",
        "EventName": "UNC_UPI_TxL_BYPASSED",
        "PerPkg": "1",
        "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR  mode, increasing latency to transfer out to the link.",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "Null FLITs transmitted from any slot",
        "Counter": "0,1,2,3",
        "EventCode": "0x2",
        "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
        "PerPkg": "1",
        "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unit.",
        "UMask": "0x27",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "Valid Flits Sent; Data",
        "Counter": "0,1,2,3",
        "EventCode": "0x2",
        "EventName": "UNC_UPI_TxL_FLITS.DATA",
        "PerPkg": "1",
        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
        "UMask": "0x8",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "Idle FLITs transmitted",
        "Counter": "0,1,2,3",
        "EventCode": "0x2",
        "EventName": "UNC_UPI_TxL_FLITS.IDLE",
        "PerPkg": "1",
        "PublicDescription": "Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs).  Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs.",
        "UMask": "0x47",
        "Unit": "UPI LL"
    },
    {
        "BriefDescription": "Protocol header and credit FLITs transmitted across any slot",
        "Counter": "0,1,2,3",
        "EventCode": "0x2",
        "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
        "PerPkg": "1",
        "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit.",
        "UMask": "0x97",
        "Unit": "UPI LL"
    }
]