| commit | f31bccd3989d504a0c90b4562908ea18162d7662 | [log] [tgz] |
|---|---|---|
| author | Imre Deak <imre.deak@intel.com> | Wed Jul 27 19:45:23 2022 +0300 |
| committer | Imre Deak <imre.deak@intel.com> | Thu Jul 28 16:52:56 2022 +0300 |
| tree | 2fedb82c3fc2db1c43ba726922afdf7de5e968cf | |
| parent | fa6a4cdeafa0ab674d0f72067304c5408c89964f [diff] |
drm/i915/d13: Add Wa_16015201720 disabling clock gating for PIPEDMC-A/B Add a workaround making sure that PIPEDMC-A/B is enabled when the firmware needs these on D13 platforms to save/restore the registers backed by the PW_1 and PW_A power wells. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220727164523.1621361-2-imre.deak@intel.com