commit f41ae0b2b9e5b4455cfc68dcc885f4fa2a973384
author Ralf Baechle <ralf@linux-mips.org> Mon Jun 05 17:24:46 2006 +0100
committer Ralf Baechle <ralf@linux-mips.org> Thu Jun 29 21:10:51 2006 +0100
tree 1d571a10b4265233b511ce2f45d4ca03b9fbb13a
parent e73ea273ef87a04ff59fc368fa33333dca275dde

[MIPS] Fix configuration of R2 CPU features and multithreading.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/kernel/traps.c

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index ad16ece..6797193 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1050,7 +1050,7 @@
 	return (void *)old_handler;
 }
 
-#ifdef CONFIG_CPU_MIPSR2
+#ifdef CONFIG_CPU_MIPSR2_SRS
 /*
  * MIPSR2 shadow register set allocation
  * FIXME: SMP...
@@ -1069,11 +1069,9 @@
 
 static void mips_srs_init(void)
 {
-#ifdef CONFIG_CPU_MIPSR2_SRS
 	shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
 	printk(KERN_INFO "%d MIPSR2 register sets available\n",
 	       shadow_registers.sr_supported);
-#endif
 	shadow_registers.sr_allocated = 1;	/* Set 0 used by kernel */
 }
 
@@ -1198,7 +1196,14 @@
 {
 	return set_vi_srs_handler(n, addr, 0);
 }
-#endif
+
+#else
+
+static inline void mips_srs_init(void)
+{
+}
+
+#endif /* CONFIG_CPU_MIPSR2_SRS */
 
 /*
  * This is used by native signal handling
@@ -1388,9 +1393,7 @@
 	else
 		ebase = CAC_BASE;
 
-#ifdef CONFIG_CPU_MIPSR2
 	mips_srs_init();
-#endif
 
 	per_cpu_trap_init();