)]}'
{
  "commit": "f81a348728ec5ac43f3bbcf81c97d52baba253f7",
  "tree": "2be7b3bdfa04369661c86d7858bc0f280a08cd01",
  "parents": [
    "4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323"
  ],
  "author": {
    "name": "Mark Rutland",
    "email": "mark.rutland@arm.com",
    "time": "Tue Nov 21 11:59:13 2017 +0000"
  },
  "committer": {
    "name": "Will Deacon",
    "email": "will.deacon@arm.com",
    "time": "Tue Nov 28 18:13:18 2017 +0000"
  },
  "message": "arm64: mm: cleanup stale AIVIVT references\n\nSince commit:\n\n  155433cb365ee466 (\"arm64: cache: Remove support for ASID-tagged VIVT I-caches\")\n\n... the kernel no longer cares about AIVIVT I-caches, as these were\nremoved from the architecture.\n\nThis patch removes the stale references to such I-caches.\n\nThe comment in flush_context() is also updated to clarify when and where\nthe TLB invalidation occurs.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nCc: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nCc: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "76d1cc85d5b115915aaa63138121e9ba286d8f4e",
      "old_mode": 33188,
      "old_path": "arch/arm64/include/asm/cacheflush.h",
      "new_id": "955130762a3c6acc09f3ee76574f7cefc5097b4c",
      "new_mode": 33188,
      "new_path": "arch/arm64/include/asm/cacheflush.h"
    },
    {
      "type": "modify",
      "old_id": "ab9f5f0fb2c7fc6ada0605e31d8f73b0024ae277",
      "old_mode": 33188,
      "old_path": "arch/arm64/mm/context.c",
      "new_id": "28a45a19aae7fcddeeb185ceb6211a4d98429644",
      "new_mode": 33188,
      "new_path": "arch/arm64/mm/context.c"
    }
  ]
}