tree 671340da3038bdabb6381f350ad9dd2b95ccd43c
parent 1c15ca4e4efaddb78f83eed31eeee34c522c3ae2
parent cc5f6fa4f6590e3b9eb8d34302ea43af4a3cfed7
author Linus Torvalds <torvalds@linux-foundation.org> 1682618546 -0700
committer Linus Torvalds <torvalds@linux-foundation.org> 1682618546 -0700
mergetag object cc5f6fa4f6590e3b9eb8d34302ea43af4a3cfed7
 type commit
 tag spi-v6.4
 tagger Mark Brown <broonie@kernel.org> 1682445510 +0100
 
 spi: Updates for v6.4
 
 A fairly standard release for SPI with the exception of a change to the
 API for specifying chip selects done in preparation for supporting
 devices with more than one chip select, this required some mechanical
 changes throughout the tree which have been cooking in -next happily for
 a while.  There's also a new API to allow us to TPM chips on half duplex
 controllers.
 
 There's three commits in here that were mangled by a bad interaction
 between the alsa-devel mailing list software and b4, I didn't notice
 until there were merges on top with it being SPI not ALSA.  It seemed
 clear enough to not be worth going back and fixing.
 
  - Refactoring in preparation for supporting multiple chip selects for a
    single device, needed by some flash devices, which required a change
    in the SPI device API visible throughout the tree.
  - Support for hardware assisted interaction with SPI TPMs on half
    duplex controllers, implemented on nVidia Tedra210 QuadSPI.
  - Optimisation for large transfers on fsl-cpm devices.
  - Cleanups around device property use which fix some sisues with
    fwnode.
  - Use of both void remove() and devm_platform_.*ioremap_resource().
  - Support for AMD Pensando Elba, Amlogic A1, Cadence device mode,
    Intel MetorLake-S and StarFive J7110 QuadSPI.
 
 The final commit converting to DEV_PM_OPS() was applied late to fix a
 warning that was introduced by some of the earlier work.
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Merge tag 'spi-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
 "A fairly standard release for SPI with the exception of a change to
  the API for specifying chip selects done in preparation for supporting
  devices with more than one chip select, this required some mechanical
  changes throughout the tree which have been cooking in -next happily
  for a while.

  There's also a new API to allow us to support TPM chips on half duplex
  controllers.

  Summary:

   - Refactoring in preparation for supporting multiple chip selects for
     a single device, needed by some flash devices, which required a
     change in the SPI device API visible throughout the tree

   - Support for hardware assisted interaction with SPI TPMs on half
     duplex controllers, implemented on nVidia Tedra210 QuadSPI

   - Optimisation for large transfers on fsl-cpm devices

   - Cleanups around device property use which fix some sisues with
     fwnode

   - Use of both void remove() and devm_platform_.*ioremap_resource()

   - Support for AMD Pensando Elba, Amlogic A1, Cadence device mode,
     Intel MetorLake-S and StarFive J7110 QuadSPI"

* tag 'spi-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (185 commits)
  spi: bcm63xx: use macro DEFINE_SIMPLE_DEV_PM_OPS
  spi: tegra210-quad: Enable TPM wait polling
  spi: Add TPM HW flow flag
  spi: bcm63xx: remove PM_SLEEP based conditional compilation
  spi: cadence-quadspi: use macro DEFINE_SIMPLE_DEV_PM_OPS
  spi: spi-cadence: Add support for Slave mode
  spi: spi-cadence: Switch to spi_controller structure
  spi: cadence-quadspi: fix suspend-resume implementations
  spi: dw: Add support for AMD Pensando Elba SoC
  spi: dw: Add AMD Pensando Elba SoC SPI Controller
  spi: cadence-quadspi: Disable the SPI before reconfiguring
  spi: cadence-quadspi: Update the read timeout based on the length
  spi: spi-loopback-test: Add module param for iteration length
  spi: add support for Amlogic A1 SPI Flash Controller
  dt-bindings: spi: add Amlogic A1 SPI controller
  spi: fsl-spi: No need to check transfer length versus word size
  spi: fsl-spi: Change mspi_apply_cpu_mode_quirks() to void
  spi: fsl-cpm: Use 16 bit mode for large transfers with even size
  spi: fsl-spi: Re-organise transfer bits_per_word adaptation
  spi: fsl-spi: Fix CPM/QE mode Litte Endian
  ...