// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2021 NXP
 */

/dts-v1/;

#include "imx8ulp.dtsi"

/ {
	model = "NXP i.MX8ULP EVK";
	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";

	chosen {
		stdout-path = &lpuart5;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0 0x80000000>;
	};

	clock_ext_rmii: clock-ext-rmii {
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
		clock-output-names = "ext_rmii_clk";
		#clock-cells = <0>;
	};

	clock_ext_ts: clock-ext-ts {
		compatible = "fixed-clock";
		/* External ts clock is 50MHZ from PHY on EVK board. */
		clock-frequency = <50000000>;
		clock-output-names = "ext_ts_clk";
		#clock-cells = <0>;
	};
};

&lpuart5 {
	/* console */
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_lpuart5>;
	pinctrl-1 = <&pinctrl_lpuart5>;
	status = "okay";
};

&usdhc0 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_usdhc0>;
	pinctrl-1 = <&pinctrl_usdhc0>;
	non-removable;
	bus-width = <8>;
	status = "okay";
};

&fec {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_enet>;
	pinctrl-1 = <&pinctrl_enet>;
	clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
		 <&pcc4 IMX8ULP_CLK_ENET>,
		 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
		 <&clock_ext_rmii>;
	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
	assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
	assigned-clock-parents = <&clock_ext_ts>;
	phy-mode = "rmii";
	phy-handle = <&ethphy>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy: ethernet-phy@1 {
			reg = <1>;
			micrel,led-mode = <1>;
		};
	};
};

&iomuxc1 {
	pinctrl_enet: enetgrp {
		fsl,pins = <
			MX8ULP_PAD_PTE15__ENET0_MDC     0x43
			MX8ULP_PAD_PTE14__ENET0_MDIO    0x43
			MX8ULP_PAD_PTE17__ENET0_RXER    0x43
			MX8ULP_PAD_PTE18__ENET0_CRS_DV  0x43
			MX8ULP_PAD_PTF1__ENET0_RXD0     0x43
			MX8ULP_PAD_PTE20__ENET0_RXD1    0x43
			MX8ULP_PAD_PTE16__ENET0_TXEN    0x43
			MX8ULP_PAD_PTE23__ENET0_TXD0    0x43
			MX8ULP_PAD_PTE22__ENET0_TXD1    0x43
			MX8ULP_PAD_PTE19__ENET0_REFCLK  0x43
			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
		>;
	};

	pinctrl_lpuart5: lpuart5grp {
		fsl,pins = <
			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
			MX8ULP_PAD_PTF15__LPUART5_RX	0x3
		>;
	};

	pinctrl_usdhc0: usdhc0grp {
		fsl,pins = <
			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
		>;
	};
};