arm64: alternatives: avoid prio masking code if pseudo NMI is disabled
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h
index ff328e5b..9865a4d 100644
--- a/arch/arm64/include/asm/irqflags.h
+++ b/arch/arm64/include/asm/irqflags.h
@@ -34,10 +34,11 @@
WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF);
}
- asm volatile(ALTERNATIVE(
+ asm volatile(ALTERNATIVE_IF(
"msr daifclr, #2 // arch_local_irq_enable",
__msr_s(SYS_ICC_PMR_EL1, "%0"),
- ARM64_HAS_IRQ_PRIO_MASKING)
+ ARM64_HAS_IRQ_PRIO_MASKING,
+ CONFIG_ARM64_PSEUDO_NMI)
:
: "r" ((unsigned long) GIC_PRIO_IRQON)
: "memory");
@@ -53,10 +54,11 @@
WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF);
}
- asm volatile(ALTERNATIVE(
+ asm volatile(ALTERNATIVE_IF(
"msr daifset, #2 // arch_local_irq_disable",
__msr_s(SYS_ICC_PMR_EL1, "%0"),
- ARM64_HAS_IRQ_PRIO_MASKING)
+ ARM64_HAS_IRQ_PRIO_MASKING,
+ CONFIG_ARM64_PSEUDO_NMI)
:
: "r" ((unsigned long) GIC_PRIO_IRQOFF)
: "memory");
@@ -69,10 +71,11 @@
{
unsigned long flags;
- asm volatile(ALTERNATIVE(
+ asm volatile(ALTERNATIVE_IF(
"mrs %0, daif",
__mrs_s("%0", SYS_ICC_PMR_EL1),
- ARM64_HAS_IRQ_PRIO_MASKING)
+ ARM64_HAS_IRQ_PRIO_MASKING,
+ CONFIG_ARM64_PSEUDO_NMI)
: "=&r" (flags)
:
: "memory");
@@ -84,10 +87,11 @@
{
int res;
- asm volatile(ALTERNATIVE(
+ asm volatile(ALTERNATIVE_IF(
"and %w0, %w1, #" __stringify(PSR_I_BIT),
"eor %w0, %w1, #" __stringify(GIC_PRIO_IRQON),
- ARM64_HAS_IRQ_PRIO_MASKING)
+ ARM64_HAS_IRQ_PRIO_MASKING,
+ CONFIG_ARM64_PSEUDO_NMI)
: "=&r" (res)
: "r" ((int) flags)
: "memory");
