| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2019 NXP |
| * Dong Aisheng <aisheng.dong@nxp.com> |
| */ |
| |
| #include <dt-bindings/firmware/imx/rsrc.h> |
| |
| gpu0_subsys: bus@53000000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x53000000 0x0 0x53000000 0x1000000>; |
| |
| gpu_3d0: gpu@53100000 { |
| compatible = "vivante,gc"; |
| reg = <0x53100000 0x40000>; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; |
| clock-names = "core", "shader"; |
| assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, |
| <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; |
| assigned-clock-rates = <700000000>, <850000000>; |
| power-domains = <&pd IMX_SC_R_GPU_0_PID0>; |
| }; |
| }; |
