| Broadcom iProc I2C controller |
| |
| Required properties: |
| |
| - compatible: |
| Must be "brcm,iproc-i2c" or "brcm,iproc-nic-i2c" |
| |
| - reg: |
| Define the base and range of the I/O address space that contain the iProc |
| I2C controller registers |
| |
| - clock-frequency: |
| This is the I2C bus clock. Need to be either 100000 or 400000 |
| |
| - #address-cells: |
| Always 1 (for I2C addresses) |
| |
| - #size-cells: |
| Always 0 |
| |
| Optional properties: |
| |
| - interrupts: |
| Should contain the I2C interrupt. For certain revisions of the I2C |
| controller, I2C interrupt is unwired to the interrupt controller. In such |
| case, this property should be left unspecified, and driver will fall back |
| to polling mode |
| |
| - brcm,ape-hsls-addr-mask: |
| Required for "brcm,iproc-nic-i2c". Host view of address mask into the |
| 'APE' co-processor. Value must be unsigned, 32-bit |
| |
| Example: |
| i2c0: i2c@18008000 { |
| compatible = "brcm,iproc-i2c"; |
| reg = <0x18008000 0x100>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; |
| clock-frequency = <100000>; |
| |
| codec: wm8750@1a { |
| compatible = "wlf,wm8750"; |
| reg = <0x1a>; |
| }; |
| }; |
