/*
 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 SD card slot */
	};

	chosen { };

	memory {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0 0 0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		tz-apps@86000000 {
			reg = <0x0 0x86000000 0x0 0x300000>;
			no-map;
		};

		smem_mem: smem_region@86300000 {
			reg = <0x0 0x86300000 0x0 0x100000>;
			no-map;
		};

		hypervisor@86400000 {
			reg = <0x0 0x86400000 0x0 0x100000>;
			no-map;
		};

		tz@86500000 {
			reg = <0x0 0x86500000 0x0 0x180000>;
			no-map;
		};

		reserved@8668000 {
			reg = <0x0 0x86680000 0x0 0x80000>;
			no-map;
		};

		rmtfs@86700000 {
			compatible = "qcom,rmtfs-mem";
			reg = <0x0 0x86700000 0x0 0xe0000>;
			no-map;

			qcom,client-id = <1>;
		};

		rfsa@867e00000 {
			reg = <0x0 0x867e0000 0x0 0x20000>;
			no-map;
		};

		mpss_mem: mpss@86800000 {
			reg = <0x0 0x86800000 0x0 0x2b00000>;
			no-map;
		};

		wcnss_mem: wcnss@89300000 {
			reg = <0x0 0x89300000 0x0 0x600000>;
			no-map;
		};

		venus_mem: venus@89900000 {
			reg = <0x0 0x89900000 0x0 0x600000>;
			no-map;
		};

		mba_mem: mba@8ea00000 {
			no-map;
			reg = <0 0x8ea00000 0 0x100000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SPC>;
			clocks = <&apcs 0>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SPC>;
			clocks = <&apcs 0>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x2>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SPC>;
			clocks = <&apcs 0>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x3>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SPC>;
			clocks = <&apcs 0>;
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
		};

		L2_0: l2-cache {
		      compatible = "cache";
		      cache-level = <2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x40000002>;
				entry-latency-us = <130>;
				exit-latency-us = <150>;
				min-residency-us = <2000>;
				local-timer-stop;
			};
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
	};

	thermal-zones {
		cpu-thermal0 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 4>;

			trips {
				cpu_alert0: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		cpu-thermal1 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 3>;

			trips {
				cpu_alert1: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit1: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert1>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

	};

	cpu_opp_table: cpu_opp_table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
		};
		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
		};
		opp-998400000 {
			opp-hz = /bits/ 64 <998400000>;
		};
	};

	gpu_opp_table: opp_table {
		compatible = "operating-points-v2";

		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
		};
		opp-19200000 {
			opp-hz = /bits/ 64 <19200000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	smem {
		compatible = "qcom,smem";

		memory-region = <&smem_mem>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		hwlocks = <&tcsr_mutex 3>;
	};

	firmware {
		scm: scm {
			compatible = "qcom,scm";
			clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
			clock-names = "core", "bus", "iface";
			#reset-cells = <1>;

			qcom,dload-mode = <&tcsr 0x6100>;
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		restart@4ab000 {
			compatible = "qcom,pshold";
			reg = <0x4ab000 0x4>;
		};

		msmgpio: pinctrl@1000000 {
			compatible = "qcom,msm8916-pinctrl";
			reg = <0x1000000 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gcc: clock-controller@1800000 {
			compatible = "qcom,gcc-msm8916";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x1800000 0x80000>;
		};

		tcsr_mutex_regs: syscon@1905000 {
			compatible = "syscon";
			reg = <0x1905000 0x20000>;
		};

		tcsr: syscon@1937000 {
			compatible = "qcom,tcsr-msm8916", "syscon";
			reg = <0x1937000 0x30000>;
		};

		tcsr_mutex: hwlock {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_regs 0 0x1000>;
			#hwlock-cells = <1>;
		};

		rpm_msg_ram: memory@60000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x60000 0x8000>;
		};

		blsp1_uart1: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		a53pll: clock@b016000 {
			compatible = "qcom,msm8916-a53pll";
			reg = <0xb016000 0x40>;
			#clock-cells = <0>;
		};

		apcs: mailbox@b011000 {
			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
			reg = <0xb011000 0x1000>;
			#mbox-cells = <1>;
			clocks = <&a53pll>;
			#clock-cells = <0>;
		};

		blsp1_uart2: serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78b0000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		blsp_dma: dma@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x23000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		blsp_spi1: spi@78b5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b5000 0x500>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi1_default>;
			pinctrl-1 = <&spi1_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi2: spi@78b6000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b6000 0x500>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 7>, <&blsp_dma 6>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi2_default>;
			pinctrl-1 = <&spi2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi3: spi@78b7000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b7000 0x500>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi3_default>;
			pinctrl-1 = <&spi3_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi4: spi@78b8000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b8000 0x500>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 11>, <&blsp_dma 10>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi4_default>;
			pinctrl-1 = <&spi4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi5: spi@78b9000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b9000 0x500>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 13>, <&blsp_dma 12>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi5_default>;
			pinctrl-1 = <&spi5_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi6: spi@78ba000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078ba000 0x500>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 15>, <&blsp_dma 14>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi6_default>;
			pinctrl-1 = <&spi6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c2: i2c@78b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b6000 0x500>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c2_default>;
			pinctrl-1 = <&i2c2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c4: i2c@78b8000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b8000 0x500>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c4_default>;
			pinctrl-1 = <&i2c4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c6: i2c@78ba000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078ba000 0x500>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c6_default>;
			pinctrl-1 = <&i2c6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		lpass: lpass@7708000 {
			status = "disabled";
			compatible = "qcom,lpass-cpu-apq8016";
			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;

			clock-names = "ahbix-clk",
					"pcnoc-mport-clk",
					"pcnoc-sway-clk",
					"mi2s-bit-clk0",
					"mi2s-bit-clk1",
					"mi2s-bit-clk2",
					"mi2s-bit-clk3";
			#sound-dai-cells = <1>;

			interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "lpass-irq-lpaif";
			reg = <0x07708000 0x10000>;
			reg-names = "lpass-lpaif";
		};

                lpass_codec: codec{
			compatible = "qcom,msm8916-wcd-digital-codec";
			reg = <0x0771c000 0x400>;
			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
				 <&gcc GCC_CODEC_DIGCODEC_CLK>;
			clock-names = "ahbix-clk", "mclk";
			#sound-dai-cells = <1>;
                };

		sdhc_1: sdhci@7824000 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
				 <&gcc GCC_SDCC1_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";
			mmc-ddr-1_8v;
			bus-width = <8>;
			non-removable;
			status = "disabled";
		};

		sdhc_2: sdhci@7864000 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
				 <&gcc GCC_SDCC2_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";
			bus-width = <4>;
			status = "disabled";
		};

		otg: usb@78d9000 {
			compatible = "qcom,ci-hdrc";
			reg = <0x78d9000 0x200>,
			      <0x78d9200 0x200>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
			clock-names = "iface", "core";
			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
			assigned-clock-rates = <80000000>;
			resets = <&gcc GCC_USB_HS_BCR>;
			reset-names = "core";
			phy_type = "ulpi";
			dr_mode = "otg";
			ahb-burst-config = <0>;
			phy-names = "usb-phy";
			phys = <&usb_hs_phy>;
			status = "disabled";
			#reset-cells = <1>;

			ulpi {
				usb_hs_phy: phy {
					compatible = "qcom,usb-hs-phy-msm8916",
						     "qcom,usb-hs-phy";
					#phy-cells = <0>;
					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
					clock-names = "ref", "sleep";
					resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
					reset-names = "phy", "por";
					qcom,init-seq = /bits/ 8 <0x0 0x44
						0x1 0x6b 0x2 0x24 0x3 0x13>;
				};
			};
		};

		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
		};

		timer@b020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xb020000 0x1000>;
			clock-frequency = <19200000>;

			frame@b021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb021000 0x1000>,
				      <0xb022000 0x1000>;
			};

			frame@b023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb023000 0x1000>;
				status = "disabled";
			};

			frame@b024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb024000 0x1000>;
				status = "disabled";
			};

			frame@b025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb025000 0x1000>;
				status = "disabled";
			};

			frame@b026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb026000 0x1000>;
				status = "disabled";
			};

			frame@b027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb027000 0x1000>;
				status = "disabled";
			};

			frame@b028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb028000 0x1000>;
				status = "disabled";
			};
		};

		spmi_bus: spmi@200f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x200f000 0x001000>,
			      <0x2400000 0x400000>,
			      <0x2c00000 0x400000>,
			      <0x3800000 0x200000>,
			      <0x200a000 0x002100>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		rng@22000 {
			compatible = "qcom,prng";
			reg = <0x00022000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		qfprom: qfprom@5c000 {
			compatible = "qcom,qfprom";
			reg = <0x5c000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			tsens_caldata: caldata@d0 {
				reg = <0xd0 0x8>;
			};
			tsens_calsel: calsel@ec {
				reg = <0xec 0x4>;
			};
		};

		tsens: thermal-sensor@4a8000 {
			compatible = "qcom,msm8916-tsens";
			reg = <0x4a8000 0x2000>;
			nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
			nvmem-cell-names = "calib", "calib_sel";
			#thermal-sensor-cells = <1>;
		};

		apps_iommu: iommu@1ef0000 {
			#address-cells = <1>;
			#size-cells = <1>;
			#iommu-cells = <1>;
			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
			ranges = <0 0x1e20000 0x40000>;
			reg = <0x1ef0000 0x3000>;
			clocks = <&gcc GCC_SMMU_CFG_CLK>,
				 <&gcc GCC_APSS_TCU_CLK>;
			clock-names = "iface", "bus";
			qcom,iommu-secure-id = <17>;

			// mdp_0:
			iommu-ctx@4000 {
				compatible = "qcom,msm-iommu-v1-ns";
				reg = <0x4000 0x1000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			};

			// venus_ns:
			iommu-ctx@5000 {
				compatible = "qcom,msm-iommu-v1-sec";
				reg = <0x5000 0x1000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpu_iommu: iommu@1f08000 {
			#address-cells = <1>;
			#size-cells = <1>;
			#iommu-cells = <1>;
			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
			ranges = <0 0x1f08000 0x10000>;
			clocks = <&gcc GCC_SMMU_CFG_CLK>,
				 <&gcc GCC_GFX_TCU_CLK>;
			clock-names = "iface", "bus";
			qcom,iommu-secure-id = <18>;

			// gfx3d_user:
			iommu-ctx@1000 {
				compatible = "qcom,msm-iommu-v1-ns";
				reg = <0x1000 0x1000>;
				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
			};

			// gfx3d_priv:
			iommu-ctx@2000 {
				compatible = "qcom,msm-iommu-v1-ns";
				reg = <0x2000 0x1000>;
				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpu@1c00000 {
			compatible = "qcom,adreno-306.0", "qcom,adreno";
			reg = <0x01c00000 0x20000>;
			reg-names = "kgsl_3d0_reg_memory";
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "kgsl_3d0_irq";
			clock-names =
			    "core",
			    "iface",
			    "mem",
			    "mem_iface",
			    "alt_mem_iface",
			    "gfx3d";
			clocks =
			    <&gcc GCC_OXILI_GFX3D_CLK>,
			    <&gcc GCC_OXILI_AHB_CLK>,
			    <&gcc GCC_OXILI_GMEM_CLK>,
			    <&gcc GCC_BIMC_GFX_CLK>,
			    <&gcc GCC_BIMC_GPU_CLK>,
			    <&gcc GFX3D_CLK_SRC>;
			power-domains = <&gcc OXILI_GDSC>;
			operating-points-v2 = <&gpu_opp_table>;
			iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
		};

		mdss: mdss@1a00000 {
			compatible = "qcom,mdss";
			reg = <0x1a00000 0x1000>,
			      <0x1ac8000 0x3000>;
			reg-names = "mdss_phys", "vbif_phys";

			power-domains = <&gcc MDSS_GDSC>;

			clocks = <&gcc GCC_MDSS_AHB_CLK>,
				 <&gcc GCC_MDSS_AXI_CLK>,
				 <&gcc GCC_MDSS_VSYNC_CLK>;
			clock-names = "iface",
				      "bus",
				      "vsync";

			interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;
			#interrupt-cells = <1>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			mdp: mdp@1a01000 {
				compatible = "qcom,mdp5";
				reg = <0x1a01000 0x89000>;
				reg-names = "mdp_phys";

				interrupt-parent = <&mdss>;
				interrupts = <0 0>;

				clocks = <&gcc GCC_MDSS_AHB_CLK>,
					 <&gcc GCC_MDSS_AXI_CLK>,
					 <&gcc GCC_MDSS_MDP_CLK>,
					 <&gcc GCC_MDSS_VSYNC_CLK>;
				clock-names = "iface",
					      "bus",
					      "core",
					      "vsync";

				iommus = <&apps_iommu 4>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						mdp5_intf1_out: endpoint {
							remote-endpoint = <&dsi0_in>;
						};
					};
				};
			};

			dsi0: dsi@1a98000 {
				compatible = "qcom,mdss-dsi-ctrl";
				reg = <0x1a98000 0x25c>;
				reg-names = "dsi_ctrl";

				interrupt-parent = <&mdss>;
				interrupts = <4 0>;

				assigned-clocks = <&gcc BYTE0_CLK_SRC>,
						  <&gcc PCLK0_CLK_SRC>;
				assigned-clock-parents = <&dsi_phy0 0>,
							 <&dsi_phy0 1>;

				clocks = <&gcc GCC_MDSS_MDP_CLK>,
					 <&gcc GCC_MDSS_AHB_CLK>,
					 <&gcc GCC_MDSS_AXI_CLK>,
					 <&gcc GCC_MDSS_BYTE0_CLK>,
					 <&gcc GCC_MDSS_PCLK0_CLK>,
					 <&gcc GCC_MDSS_ESC0_CLK>;
				clock-names = "mdp_core",
					      "iface",
					      "bus",
					      "byte",
					      "pixel",
					      "core";
				phys = <&dsi_phy0>;
				phy-names = "dsi-phy";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						dsi0_in: endpoint {
							remote-endpoint = <&mdp5_intf1_out>;
						};
					};

					port@1 {
						reg = <1>;
						dsi0_out: endpoint {
						};
					};
				};
			};

			dsi_phy0: dsi-phy@1a98300 {
				compatible = "qcom,dsi-phy-28nm-lp";
				reg = <0x1a98300 0xd4>,
				      <0x1a98500 0x280>,
				      <0x1a98780 0x30>;
				reg-names = "dsi_pll",
					    "dsi_phy",
					    "dsi_phy_regulator";

				#clock-cells = <1>;
				#phy-cells = <0>;

				clocks = <&gcc GCC_MDSS_AHB_CLK>;
				clock-names = "iface";
			};
		};


		hexagon@4080000 {
			compatible = "qcom,q6v5-pil";
			reg = <0x04080000 0x100>,
			      <0x04020000 0x040>;

			reg-names = "qdsp6", "rmb";

			interrupts-extended = <&intc 0 24 1>,
					      <&hexagon_smp2p_in 0 0>,
					      <&hexagon_smp2p_in 1 0>,
					      <&hexagon_smp2p_in 2 0>,
					      <&hexagon_smp2p_in 3 0>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
				 <&xo_board>;
			clock-names = "iface", "bus", "mem", "xo";

			qcom,smem-states = <&hexagon_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			resets = <&scm 0>;
			reset-names = "mss_restart";

			cx-supply = <&pm8916_s1>;
			mx-supply = <&pm8916_l3>;
			pll-supply = <&pm8916_l7>;

			qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;

			status = "disabled";

			mba {
				memory-region = <&mba_mem>;
			};

			mpss {
				memory-region = <&mpss_mem>;
			};

			smd-edge {
				interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;

				qcom,smd-edge = <0>;
				qcom,ipc = <&apcs 8 12>;
				qcom,remote-pid = <1>;

				label = "hexagon";
			};
		};

		pronto: wcnss@a21b000 {
			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
			reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
			reg-names = "ccu", "dxe", "pmu";

			memory-region = <&wcnss_mem>;

			interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

			vddmx-supply = <&pm8916_l3>;
			vddpx-supply = <&pm8916_l7>;

			qcom,state = <&wcnss_smp2p_out 0>;
			qcom,state-names = "stop";

			pinctrl-names = "default";
			pinctrl-0 = <&wcnss_pin_a>;

			status = "disabled";

			iris {
				compatible = "qcom,wcn3620";

				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
				clock-names = "xo";

				vddxo-supply = <&pm8916_l7>;
				vddrfa-supply = <&pm8916_s3>;
				vddpa-supply = <&pm8916_l9>;
				vdddig-supply = <&pm8916_l5>;
			};

			smd-edge {
				interrupts = <0 142 1>;

				qcom,ipc = <&apcs 8 17>;
				qcom,smd-edge = <6>;
				qcom,remote-pid = <4>;

				label = "pronto";

				wcnss {
					compatible = "qcom,wcnss";
					qcom,smd-channels = "WCNSS_CTRL";

					qcom,mmio = <&pronto>;

					bt {
						compatible = "qcom,wcnss-bt";
					};

					wifi {
						compatible = "qcom,wcnss-wlan";

						interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
							     <0 146 IRQ_TYPE_LEVEL_HIGH>;
						interrupt-names = "tx", "rx";

						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
					};
				};
			};
		};

		tpiu@820000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0x820000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				port {
					tpiu_in: endpoint {
						remote-endpoint = <&replicator_out1>;
					};
				};
			};
		};

		funnel@821000 {
			compatible = "arm,coresight-funnel", "arm,primecell";
			reg = <0x821000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				/*
				 * Not described input ports:
				 * 0 - connected to Resource and Power Manger CPU ETM
				 * 1 - not-connected
				 * 2 - connected to Modem CPU ETM
				 * 3 - not-connected
				 * 5 - not-connected
				 * 6 - connected trought funnel to Wireless CPU ETM
				 * 7 - connected to STM component
				 */

				port@4 {
					reg = <4>;
					funnel0_in4: endpoint {
						remote-endpoint = <&funnel1_out>;
					};
				};
			};

			out-ports {
				port {
					funnel0_out: endpoint {
						remote-endpoint = <&etf_in>;
					};
				};
			};
		};

		replicator@824000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0x824000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			out-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					replicator_out0: endpoint {
						remote-endpoint = <&etr_in>;
					};
				};
				port@1 {
					reg = <1>;
					replicator_out1: endpoint {
						remote-endpoint = <&tpiu_in>;
					};
				};
			};

			in-ports {
				port {
					replicator_in: endpoint {
						remote-endpoint = <&etf_out>;
					};
				};
			};
		};

		etf@825000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x825000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				port {
					etf_in: endpoint {
						remote-endpoint = <&funnel0_out>;
					};
				};
			};

			out-ports {
				port {
					etf_out: endpoint {
						remote-endpoint = <&replicator_in>;
					};
				};
			};
		};

		etr@826000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x826000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				port {
					etr_in: endpoint {
						remote-endpoint = <&replicator_out0>;
					};
				};
			};
		};

		funnel@841000 {	/* APSS funnel only 4 inputs are used */
			compatible = "arm,coresight-funnel", "arm,primecell";
			reg = <0x841000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					funnel1_in0: endpoint {
						remote-endpoint = <&etm0_out>;
					};
				};
				port@1 {
					reg = <1>;
					funnel1_in1: endpoint {
						remote-endpoint = <&etm1_out>;
					};
				};
				port@2 {
					reg = <2>;
					funnel1_in2: endpoint {
						remote-endpoint = <&etm2_out>;
					};
				};
				port@3 {
					reg = <3>;
					funnel1_in3: endpoint {
						remote-endpoint = <&etm3_out>;
					};
				};
			};

			out-ports {
				port {
					funnel1_out: endpoint {
						remote-endpoint = <&funnel0_in4>;
					};
				};
			};
		};

		debug@850000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			reg = <0x850000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU0>;
		};

		debug@852000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			reg = <0x852000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU1>;
		};

		debug@854000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			reg = <0x854000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU2>;
		};

		debug@856000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			reg = <0x856000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU3>;
		};

		etm@85c000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x85c000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU0>;

			out-ports {
				port {
					etm0_out: endpoint {
						remote-endpoint = <&funnel1_in0>;
					};
				};
			};
		};

		etm@85d000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x85d000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU1>;

			out-ports {
				port {
					etm1_out: endpoint {
						remote-endpoint = <&funnel1_in1>;
					};
				};
			};
		};

		etm@85e000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x85e000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU2>;

			out-ports {
				port {
					etm2_out: endpoint {
						remote-endpoint = <&funnel1_in2>;
					};
				};
			};
		};

		etm@85f000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x85f000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU3>;

			out-ports {
				port {
					etm3_out: endpoint {
						remote-endpoint = <&funnel1_in3>;
					};
				};
			};
		};

		venus: video-codec@1d00000 {
			compatible = "qcom,msm8916-venus";
			reg = <0x01d00000 0xff000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&gcc VENUS_GDSC>;
			clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
				 <&gcc GCC_VENUS0_AHB_CLK>,
				 <&gcc GCC_VENUS0_AXI_CLK>;
			clock-names = "core", "iface", "bus";
			iommus = <&apps_iommu 5>;
			memory-region = <&venus_mem>;
			status = "okay";

			video-decoder {
				compatible = "venus-decoder";
			};

			video-encoder {
				compatible = "venus-encoder";
			};
		};
	};

	smd {
		compatible = "qcom,smd";

		rpm {
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			rpm_requests {
				compatible = "qcom,rpm-msm8916";
				qcom,smd-channels = "rpm_requests";

				rpmcc: qcom,rpmcc {
					compatible = "qcom,rpmcc-msm8916";
					#clock-cells = <1>;
				};

				smd_rpm_regulators: pm8916-regulators {
					compatible = "qcom,rpm-pm8916-regulators";

					pm8916_s1: s1 {};
					pm8916_s3: s3 {};
					pm8916_s4: s4 {};

					pm8916_l1: l1 {};
					pm8916_l2: l2 {};
					pm8916_l3: l3 {};
					pm8916_l4: l4 {};
					pm8916_l5: l5 {};
					pm8916_l6: l6 {};
					pm8916_l7: l7 {};
					pm8916_l8: l8 {};
					pm8916_l9: l9 {};
					pm8916_l10: l10 {};
					pm8916_l11: l11 {};
					pm8916_l12: l12 {};
					pm8916_l13: l13 {};
					pm8916_l14: l14 {};
					pm8916_l15: l15 {};
					pm8916_l16: l16 {};
					pm8916_l17: l17 {};
					pm8916_l18: l18 {};
				};
			};
		};
	};

	hexagon-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;

		interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs 8 14>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		hexagon_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";

			#qcom,smem-state-cells = <1>;
		};

		hexagon_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	wcnss-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <451>, <431>;

		interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs 8 18>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <4>;

		wcnss_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";

			#qcom,smem-state-cells = <1>;
		};

		wcnss_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smsm {
		compatible = "qcom,smsm";

		#address-cells = <1>;
		#size-cells = <0>;

		qcom,ipc-1 = <&apcs 8 13>;
		qcom,ipc-3 = <&apcs 8 19>;

		apps_smsm: apps@0 {
			reg = <0>;

			#qcom,smem-state-cells = <1>;
		};

		hexagon_smsm: hexagon@1 {
			reg = <1>;
			interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		wcnss_smsm: wcnss@6 {
			reg = <6>;
			interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};
};

#include "msm8916-pins.dtsi"