/*
 * Device Tree Source for the Alt board
 *
 * Copyright (C) 2014 Renesas Electronics Corporation
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/dts-v1/;
#include "r8a7794.dtsi"

/ {
	model = "Alt";
	compatible = "renesas,alt", "renesas,r8a7794";

	aliases {
		serial0 = &scif2;
	};

	chosen {
		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x40000000>;
	};

	lbsc {
		#address-cells = <1>;
		#size-cells = <1>;
	};

	vga-encoder {
		compatible = "adi,adv7123";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				adv7123_in: endpoint {
					remote-endpoint = <&du_out_rgb1>;
				};
			};
			port@1 {
				reg = <1>;
				adv7123_out: endpoint {
					remote-endpoint = <&vga_in>;
				};
			};
		};
	};

	vga {
		compatible = "vga-connector";

		port {
			vga_in: endpoint {
				remote-endpoint = <&adv7123_out>;
			};
		};
	};

	x2_clk: x2-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <74250000>;
	};

	x13_clk: x13-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <148500000>;
	};
};

&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&mstp7_clks R8A7794_CLK_DU0>,
		 <&mstp7_clks R8A7794_CLK_DU0>,
		 <&x13_clk>, <&x2_clk>;
	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";

	ports {
		port@1 {
			endpoint {
				remote-endpoint = <&adv7123_in>;
			};
		};
	};
};

&extal_clk {
	clock-frequency = <20000000>;
};

&pfc {
	du_pins: du {
		renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
		renesas,function = "du";
	};

	scif2_pins: serial2 {
		renesas,groups = "scif2_data";
		renesas,function = "scif2";
	};

	ether_pins: ether {
		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
		renesas,function = "eth";
	};

	phy1_pins: phy1 {
		renesas,groups = "intc_irq8";
		renesas,function = "intc";
	};

	i2c1_pins: i2c1 {
		renesas,groups = "i2c1";
		renesas,function = "i2c1";
	};

	vin0_pins: vin0 {
		renesas,groups = "vin0_data8", "vin0_clk";
		renesas,function = "vin0";
	};
};

&cmt0 {
	status = "okay";
};

&ether {
	pinctrl-0 = <&ether_pins &phy1_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy1>;
	renesas,ether-link-active-low;
	status = "okay";

	phy1: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&irqc0>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		micrel,led-mode = <1>;
	};
};

&i2c1 {
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	composite-in@20 {
		compatible = "adi,adv7180";
		reg = <0x20>;
		remote = <&vin0>;

		port {
			adv7180: endpoint {
				bus-width = <8>;
				remote-endpoint = <&vin0ep>;
			};
		};
	};
};

&vin0 {
	status = "okay";
	pinctrl-0 = <&vin0_pins>;
	pinctrl-names = "default";

	port {
		#address-cells = <1>;
		#size-cells = <0>;

		vin0ep: endpoint {
			remote-endpoint = <&adv7180>;
			bus-width = <8>;
		};
	};
};

&scif2 {
	pinctrl-0 = <&scif2_pins>;
	pinctrl-names = "default";

	status = "okay";
};