blob: 793adda560c3c3364c2053cdb152974fc2a2f02b [file] [log] [blame]
Graeme Gregory518fb722011-05-02 16:20:08 -05001/*
2 * tps65910.c -- TI tps65910
3 *
4 * Copyright 2010 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
Graeme Gregory518fb722011-05-02 16:20:08 -050023#include <linux/slab.h>
24#include <linux/gpio.h>
25#include <linux/mfd/tps65910.h>
Rhyland Klein67901782012-05-08 11:42:41 -070026#include <linux/regulator/of_regulator.h>
Graeme Gregory518fb722011-05-02 16:20:08 -050027
Graeme Gregory518fb722011-05-02 16:20:08 -050028#define TPS65910_SUPPLY_STATE_ENABLED 0x1
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +053029#define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \
30 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \
Laxman Dewanganf30b0712012-03-07 18:21:49 +053031 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \
32 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
Graeme Gregory518fb722011-05-02 16:20:08 -050033
Axel Lind9fe28f2012-06-21 18:48:00 +080034/* supported VIO voltages in microvolts */
35static const unsigned int VIO_VSEL_table[] = {
36 1500000, 1800000, 2500000, 3300000,
Graeme Gregory518fb722011-05-02 16:20:08 -050037};
38
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -050039/* VSEL tables for TPS65910 specific LDOs and dcdc's */
40
Axel Lind9fe28f2012-06-21 18:48:00 +080041/* supported VDD3 voltages in microvolts */
42static const unsigned int VDD3_VSEL_table[] = {
43 5000000,
Graeme Gregory518fb722011-05-02 16:20:08 -050044};
45
Axel Lind9fe28f2012-06-21 18:48:00 +080046/* supported VDIG1 voltages in microvolts */
47static const unsigned int VDIG1_VSEL_table[] = {
48 1200000, 1500000, 1800000, 2700000,
Graeme Gregory518fb722011-05-02 16:20:08 -050049};
50
Axel Lind9fe28f2012-06-21 18:48:00 +080051/* supported VDIG2 voltages in microvolts */
52static const unsigned int VDIG2_VSEL_table[] = {
53 1000000, 1100000, 1200000, 1800000,
Graeme Gregory518fb722011-05-02 16:20:08 -050054};
55
Axel Lind9fe28f2012-06-21 18:48:00 +080056/* supported VPLL voltages in microvolts */
57static const unsigned int VPLL_VSEL_table[] = {
58 1000000, 1100000, 1800000, 2500000,
Graeme Gregory518fb722011-05-02 16:20:08 -050059};
60
Axel Lind9fe28f2012-06-21 18:48:00 +080061/* supported VDAC voltages in microvolts */
62static const unsigned int VDAC_VSEL_table[] = {
63 1800000, 2600000, 2800000, 2850000,
Graeme Gregory518fb722011-05-02 16:20:08 -050064};
65
Axel Lind9fe28f2012-06-21 18:48:00 +080066/* supported VAUX1 voltages in microvolts */
67static const unsigned int VAUX1_VSEL_table[] = {
68 1800000, 2500000, 2800000, 2850000,
Graeme Gregory518fb722011-05-02 16:20:08 -050069};
70
Axel Lind9fe28f2012-06-21 18:48:00 +080071/* supported VAUX2 voltages in microvolts */
72static const unsigned int VAUX2_VSEL_table[] = {
73 1800000, 2800000, 2900000, 3300000,
Graeme Gregory518fb722011-05-02 16:20:08 -050074};
75
Axel Lind9fe28f2012-06-21 18:48:00 +080076/* supported VAUX33 voltages in microvolts */
77static const unsigned int VAUX33_VSEL_table[] = {
78 1800000, 2000000, 2800000, 3300000,
Graeme Gregory518fb722011-05-02 16:20:08 -050079};
80
Axel Lind9fe28f2012-06-21 18:48:00 +080081/* supported VMMC voltages in microvolts */
82static const unsigned int VMMC_VSEL_table[] = {
83 1800000, 2800000, 3000000, 3300000,
Graeme Gregory518fb722011-05-02 16:20:08 -050084};
85
86struct tps_info {
87 const char *name;
Laxman Dewangan19228a62012-07-06 14:13:12 +053088 const char *vin_name;
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +053089 u8 n_voltages;
Axel Lind9fe28f2012-06-21 18:48:00 +080090 const unsigned int *voltage_table;
Laxman Dewangan0651eed2012-03-13 11:35:20 +053091 int enable_time_us;
Graeme Gregory518fb722011-05-02 16:20:08 -050092};
93
94static struct tps_info tps65910_regs[] = {
95 {
Laxman Dewangan33a69432012-05-19 20:04:06 +053096 .name = "vrtc",
Laxman Dewangan19228a62012-07-06 14:13:12 +053097 .vin_name = "vcc7",
Laxman Dewangan0651eed2012-03-13 11:35:20 +053098 .enable_time_us = 2200,
Graeme Gregory518fb722011-05-02 16:20:08 -050099 },
100 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530101 .name = "vio",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530102 .vin_name = "vccio",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530103 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
104 .voltage_table = VIO_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530105 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500106 },
107 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530108 .name = "vdd1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530109 .vin_name = "vcc1",
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530110 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500111 },
112 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530113 .name = "vdd2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530114 .vin_name = "vcc2",
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530115 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500116 },
117 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530118 .name = "vdd3",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530119 .n_voltages = ARRAY_SIZE(VDD3_VSEL_table),
120 .voltage_table = VDD3_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530121 .enable_time_us = 200,
Graeme Gregory518fb722011-05-02 16:20:08 -0500122 },
123 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530124 .name = "vdig1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530125 .vin_name = "vcc6",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530126 .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table),
127 .voltage_table = VDIG1_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530128 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500129 },
130 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530131 .name = "vdig2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530132 .vin_name = "vcc6",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530133 .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table),
134 .voltage_table = VDIG2_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530135 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500136 },
137 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530138 .name = "vpll",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530139 .vin_name = "vcc5",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530140 .n_voltages = ARRAY_SIZE(VPLL_VSEL_table),
141 .voltage_table = VPLL_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530142 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500143 },
144 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530145 .name = "vdac",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530146 .vin_name = "vcc5",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530147 .n_voltages = ARRAY_SIZE(VDAC_VSEL_table),
148 .voltage_table = VDAC_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530149 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500150 },
151 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530152 .name = "vaux1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530153 .vin_name = "vcc4",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530154 .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table),
155 .voltage_table = VAUX1_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530156 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500157 },
158 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530159 .name = "vaux2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530160 .vin_name = "vcc4",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530161 .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table),
162 .voltage_table = VAUX2_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530163 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500164 },
165 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530166 .name = "vaux33",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530167 .vin_name = "vcc3",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530168 .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table),
169 .voltage_table = VAUX33_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530170 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500171 },
172 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530173 .name = "vmmc",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530174 .vin_name = "vcc3",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530175 .n_voltages = ARRAY_SIZE(VMMC_VSEL_table),
176 .voltage_table = VMMC_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530177 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500178 },
179};
180
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500181static struct tps_info tps65911_regs[] = {
182 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530183 .name = "vrtc",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530184 .vin_name = "vcc7",
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530185 .enable_time_us = 2200,
Laxman Dewanganc2f8efd2012-01-18 20:46:56 +0530186 },
187 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530188 .name = "vio",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530189 .vin_name = "vccio",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530190 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
191 .voltage_table = VIO_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530192 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500193 },
194 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530195 .name = "vdd1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530196 .vin_name = "vcc1",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530197 .n_voltages = 0x4C,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530198 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500199 },
200 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530201 .name = "vdd2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530202 .vin_name = "vcc2",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530203 .n_voltages = 0x4C,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530204 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500205 },
206 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530207 .name = "vddctrl",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530208 .n_voltages = 0x44,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530209 .enable_time_us = 900,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500210 },
211 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530212 .name = "ldo1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530213 .vin_name = "vcc6",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530214 .n_voltages = 0x33,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530215 .enable_time_us = 420,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500216 },
217 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530218 .name = "ldo2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530219 .vin_name = "vcc6",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530220 .n_voltages = 0x33,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530221 .enable_time_us = 420,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500222 },
223 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530224 .name = "ldo3",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530225 .vin_name = "vcc5",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530226 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530227 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500228 },
229 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530230 .name = "ldo4",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530231 .vin_name = "vcc5",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530232 .n_voltages = 0x33,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530233 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500234 },
235 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530236 .name = "ldo5",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530237 .vin_name = "vcc4",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530238 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530239 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500240 },
241 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530242 .name = "ldo6",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530243 .vin_name = "vcc3",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530244 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530245 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500246 },
247 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530248 .name = "ldo7",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530249 .vin_name = "vcc3",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530250 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530251 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500252 },
253 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530254 .name = "ldo8",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530255 .vin_name = "vcc3",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530256 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530257 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500258 },
259};
260
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530261#define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits))
262static unsigned int tps65910_ext_sleep_control[] = {
263 0,
264 EXT_CONTROL_REG_BITS(VIO, 1, 0),
265 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
266 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
267 EXT_CONTROL_REG_BITS(VDD3, 1, 3),
268 EXT_CONTROL_REG_BITS(VDIG1, 0, 1),
269 EXT_CONTROL_REG_BITS(VDIG2, 0, 2),
270 EXT_CONTROL_REG_BITS(VPLL, 0, 6),
271 EXT_CONTROL_REG_BITS(VDAC, 0, 7),
272 EXT_CONTROL_REG_BITS(VAUX1, 0, 3),
273 EXT_CONTROL_REG_BITS(VAUX2, 0, 4),
274 EXT_CONTROL_REG_BITS(VAUX33, 0, 5),
275 EXT_CONTROL_REG_BITS(VMMC, 0, 0),
276};
277
278static unsigned int tps65911_ext_sleep_control[] = {
279 0,
280 EXT_CONTROL_REG_BITS(VIO, 1, 0),
281 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
282 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
283 EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3),
284 EXT_CONTROL_REG_BITS(LDO1, 0, 1),
285 EXT_CONTROL_REG_BITS(LDO2, 0, 2),
286 EXT_CONTROL_REG_BITS(LDO3, 0, 7),
287 EXT_CONTROL_REG_BITS(LDO4, 0, 6),
288 EXT_CONTROL_REG_BITS(LDO5, 0, 3),
289 EXT_CONTROL_REG_BITS(LDO6, 0, 0),
290 EXT_CONTROL_REG_BITS(LDO7, 0, 5),
291 EXT_CONTROL_REG_BITS(LDO8, 0, 4),
292};
293
Graeme Gregory518fb722011-05-02 16:20:08 -0500294struct tps65910_reg {
Axel Lin39aa9b62011-07-11 09:57:43 +0800295 struct regulator_desc *desc;
Graeme Gregory518fb722011-05-02 16:20:08 -0500296 struct tps65910 *mfd;
Axel Lin39aa9b62011-07-11 09:57:43 +0800297 struct regulator_dev **rdev;
298 struct tps_info **info;
Axel Lin39aa9b62011-07-11 09:57:43 +0800299 int num_regulators;
Graeme Gregory518fb722011-05-02 16:20:08 -0500300 int mode;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500301 int (*get_ctrl_reg)(int);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530302 unsigned int *ext_sleep_control;
303 unsigned int board_ext_control[TPS65910_NUM_REGS];
Graeme Gregory518fb722011-05-02 16:20:08 -0500304};
305
Graeme Gregory518fb722011-05-02 16:20:08 -0500306static int tps65910_get_ctrl_register(int id)
307{
308 switch (id) {
309 case TPS65910_REG_VRTC:
310 return TPS65910_VRTC;
311 case TPS65910_REG_VIO:
312 return TPS65910_VIO;
313 case TPS65910_REG_VDD1:
314 return TPS65910_VDD1;
315 case TPS65910_REG_VDD2:
316 return TPS65910_VDD2;
317 case TPS65910_REG_VDD3:
318 return TPS65910_VDD3;
319 case TPS65910_REG_VDIG1:
320 return TPS65910_VDIG1;
321 case TPS65910_REG_VDIG2:
322 return TPS65910_VDIG2;
323 case TPS65910_REG_VPLL:
324 return TPS65910_VPLL;
325 case TPS65910_REG_VDAC:
326 return TPS65910_VDAC;
327 case TPS65910_REG_VAUX1:
328 return TPS65910_VAUX1;
329 case TPS65910_REG_VAUX2:
330 return TPS65910_VAUX2;
331 case TPS65910_REG_VAUX33:
332 return TPS65910_VAUX33;
333 case TPS65910_REG_VMMC:
334 return TPS65910_VMMC;
335 default:
336 return -EINVAL;
337 }
338}
339
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500340static int tps65911_get_ctrl_register(int id)
341{
342 switch (id) {
343 case TPS65910_REG_VRTC:
344 return TPS65910_VRTC;
345 case TPS65910_REG_VIO:
346 return TPS65910_VIO;
347 case TPS65910_REG_VDD1:
348 return TPS65910_VDD1;
349 case TPS65910_REG_VDD2:
350 return TPS65910_VDD2;
351 case TPS65911_REG_VDDCTRL:
352 return TPS65911_VDDCTRL;
353 case TPS65911_REG_LDO1:
354 return TPS65911_LDO1;
355 case TPS65911_REG_LDO2:
356 return TPS65911_LDO2;
357 case TPS65911_REG_LDO3:
358 return TPS65911_LDO3;
359 case TPS65911_REG_LDO4:
360 return TPS65911_LDO4;
361 case TPS65911_REG_LDO5:
362 return TPS65911_LDO5;
363 case TPS65911_REG_LDO6:
364 return TPS65911_LDO6;
365 case TPS65911_REG_LDO7:
366 return TPS65911_LDO7;
367 case TPS65911_REG_LDO8:
368 return TPS65911_LDO8;
369 default:
370 return -EINVAL;
371 }
372}
373
Graeme Gregory518fb722011-05-02 16:20:08 -0500374static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode)
375{
376 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
377 struct tps65910 *mfd = pmic->mfd;
378 int reg, value, id = rdev_get_id(dev);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500379
380 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500381 if (reg < 0)
382 return reg;
383
384 switch (mode) {
385 case REGULATOR_MODE_NORMAL:
Axel Linfaa95fd2012-07-11 19:44:13 +0800386 return tps65910_reg_update_bits(pmic->mfd, reg,
387 LDO_ST_MODE_BIT | LDO_ST_ON_BIT,
388 LDO_ST_ON_BIT);
Graeme Gregory518fb722011-05-02 16:20:08 -0500389 case REGULATOR_MODE_IDLE:
390 value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT;
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700391 return tps65910_reg_set_bits(mfd, reg, value);
Graeme Gregory518fb722011-05-02 16:20:08 -0500392 case REGULATOR_MODE_STANDBY:
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700393 return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT);
Graeme Gregory518fb722011-05-02 16:20:08 -0500394 }
395
396 return -EINVAL;
397}
398
399static unsigned int tps65910_get_mode(struct regulator_dev *dev)
400{
401 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Linfaa95fd2012-07-11 19:44:13 +0800402 int ret, reg, value, id = rdev_get_id(dev);
Graeme Gregory518fb722011-05-02 16:20:08 -0500403
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500404 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500405 if (reg < 0)
406 return reg;
407
Axel Linfaa95fd2012-07-11 19:44:13 +0800408 ret = tps65910_reg_read(pmic->mfd, reg, &value);
409 if (ret < 0)
410 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500411
Axel Lin58599392012-03-13 07:15:27 +0800412 if (!(value & LDO_ST_ON_BIT))
Graeme Gregory518fb722011-05-02 16:20:08 -0500413 return REGULATOR_MODE_STANDBY;
414 else if (value & LDO_ST_MODE_BIT)
415 return REGULATOR_MODE_IDLE;
416 else
417 return REGULATOR_MODE_NORMAL;
418}
419
Laxman Dewangan18039e02012-03-14 13:00:58 +0530420static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev)
Graeme Gregory518fb722011-05-02 16:20:08 -0500421{
422 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Linfaa95fd2012-07-11 19:44:13 +0800423 int ret, id = rdev_get_id(dev);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500424 int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0;
Graeme Gregory518fb722011-05-02 16:20:08 -0500425
426 switch (id) {
427 case TPS65910_REG_VDD1:
Axel Linfaa95fd2012-07-11 19:44:13 +0800428 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_OP, &opvsel);
429 if (ret < 0)
430 return ret;
431 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1, &mult);
432 if (ret < 0)
433 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500434 mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
Axel Linfaa95fd2012-07-11 19:44:13 +0800435 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_SR, &srvsel);
436 if (ret < 0)
437 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500438 sr = opvsel & VDD1_OP_CMD_MASK;
439 opvsel &= VDD1_OP_SEL_MASK;
440 srvsel &= VDD1_SR_SEL_MASK;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500441 vselmax = 75;
Graeme Gregory518fb722011-05-02 16:20:08 -0500442 break;
443 case TPS65910_REG_VDD2:
Axel Linfaa95fd2012-07-11 19:44:13 +0800444 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_OP, &opvsel);
445 if (ret < 0)
446 return ret;
447 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2, &mult);
448 if (ret < 0)
449 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500450 mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT;
Axel Linfaa95fd2012-07-11 19:44:13 +0800451 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_SR, &srvsel);
452 if (ret < 0)
453 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500454 sr = opvsel & VDD2_OP_CMD_MASK;
455 opvsel &= VDD2_OP_SEL_MASK;
456 srvsel &= VDD2_SR_SEL_MASK;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500457 vselmax = 75;
458 break;
459 case TPS65911_REG_VDDCTRL:
Axel Linfaa95fd2012-07-11 19:44:13 +0800460 ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_OP,
461 &opvsel);
462 if (ret < 0)
463 return ret;
464 ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_SR,
465 &srvsel);
466 if (ret < 0)
467 return ret;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500468 sr = opvsel & VDDCTRL_OP_CMD_MASK;
469 opvsel &= VDDCTRL_OP_SEL_MASK;
470 srvsel &= VDDCTRL_SR_SEL_MASK;
471 vselmax = 64;
Graeme Gregory518fb722011-05-02 16:20:08 -0500472 break;
473 }
474
475 /* multiplier 0 == 1 but 2,3 normal */
476 if (!mult)
477 mult=1;
478
479 if (sr) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500480 /* normalise to valid range */
481 if (srvsel < 3)
482 srvsel = 3;
483 if (srvsel > vselmax)
484 srvsel = vselmax;
Laxman Dewangan18039e02012-03-14 13:00:58 +0530485 return srvsel - 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500486 } else {
487
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500488 /* normalise to valid range*/
489 if (opvsel < 3)
490 opvsel = 3;
491 if (opvsel > vselmax)
492 opvsel = vselmax;
Laxman Dewangan18039e02012-03-14 13:00:58 +0530493 return opvsel - 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500494 }
Laxman Dewangan18039e02012-03-14 13:00:58 +0530495 return -EINVAL;
Graeme Gregory518fb722011-05-02 16:20:08 -0500496}
497
Axel Lin1f904fd2012-05-09 09:22:47 +0800498static int tps65910_get_voltage_sel(struct regulator_dev *dev)
Graeme Gregory518fb722011-05-02 16:20:08 -0500499{
500 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Linfaa95fd2012-07-11 19:44:13 +0800501 int ret, reg, value, id = rdev_get_id(dev);
Graeme Gregory518fb722011-05-02 16:20:08 -0500502
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500503 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500504 if (reg < 0)
505 return reg;
506
Axel Linfaa95fd2012-07-11 19:44:13 +0800507 ret = tps65910_reg_read(pmic->mfd, reg, &value);
508 if (ret < 0)
509 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500510
511 switch (id) {
512 case TPS65910_REG_VIO:
513 case TPS65910_REG_VDIG1:
514 case TPS65910_REG_VDIG2:
515 case TPS65910_REG_VPLL:
516 case TPS65910_REG_VDAC:
517 case TPS65910_REG_VAUX1:
518 case TPS65910_REG_VAUX2:
519 case TPS65910_REG_VAUX33:
520 case TPS65910_REG_VMMC:
521 value &= LDO_SEL_MASK;
522 value >>= LDO_SEL_SHIFT;
523 break;
524 default:
525 return -EINVAL;
526 }
527
Axel Lin1f904fd2012-05-09 09:22:47 +0800528 return value;
Graeme Gregory518fb722011-05-02 16:20:08 -0500529}
530
531static int tps65910_get_voltage_vdd3(struct regulator_dev *dev)
532{
Axel Lind9fe28f2012-06-21 18:48:00 +0800533 return dev->desc->volt_table[0];
Graeme Gregory518fb722011-05-02 16:20:08 -0500534}
535
Axel Lin1f904fd2012-05-09 09:22:47 +0800536static int tps65911_get_voltage_sel(struct regulator_dev *dev)
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500537{
538 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Linfaa95fd2012-07-11 19:44:13 +0800539 int ret, id = rdev_get_id(dev);
540 unsigned int value, reg;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500541
542 reg = pmic->get_ctrl_reg(id);
543
Axel Linfaa95fd2012-07-11 19:44:13 +0800544 ret = tps65910_reg_read(pmic->mfd, reg, &value);
545 if (ret < 0)
546 return ret;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500547
548 switch (id) {
549 case TPS65911_REG_LDO1:
550 case TPS65911_REG_LDO2:
551 case TPS65911_REG_LDO4:
552 value &= LDO1_SEL_MASK;
553 value >>= LDO_SEL_SHIFT;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500554 break;
555 case TPS65911_REG_LDO3:
556 case TPS65911_REG_LDO5:
557 case TPS65911_REG_LDO6:
558 case TPS65911_REG_LDO7:
559 case TPS65911_REG_LDO8:
560 value &= LDO3_SEL_MASK;
561 value >>= LDO_SEL_SHIFT;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500562 break;
563 case TPS65910_REG_VIO:
Laxman Dewangane882eae2012-02-17 18:56:11 +0530564 value &= LDO_SEL_MASK;
565 value >>= LDO_SEL_SHIFT;
Axel Lin1f904fd2012-05-09 09:22:47 +0800566 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500567 default:
568 return -EINVAL;
569 }
570
Axel Lin1f904fd2012-05-09 09:22:47 +0800571 return value;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500572}
573
Axel Lin94732b92012-03-09 10:22:20 +0800574static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
575 unsigned selector)
Graeme Gregory518fb722011-05-02 16:20:08 -0500576{
577 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
578 int id = rdev_get_id(dev), vsel;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500579 int dcdc_mult = 0;
Graeme Gregory518fb722011-05-02 16:20:08 -0500580
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500581 switch (id) {
582 case TPS65910_REG_VDD1:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530583 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500584 if (dcdc_mult == 1)
585 dcdc_mult--;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530586 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500587
Axel Linfaa95fd2012-07-11 19:44:13 +0800588 tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD1,
589 VDD1_VGAIN_SEL_MASK,
590 dcdc_mult << VDD1_VGAIN_SEL_SHIFT);
591 tps65910_reg_write(pmic->mfd, TPS65910_VDD1_OP, vsel);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500592 break;
593 case TPS65910_REG_VDD2:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530594 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500595 if (dcdc_mult == 1)
596 dcdc_mult--;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530597 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500598
Axel Linfaa95fd2012-07-11 19:44:13 +0800599 tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD2,
600 VDD1_VGAIN_SEL_MASK,
601 dcdc_mult << VDD2_VGAIN_SEL_SHIFT);
602 tps65910_reg_write(pmic->mfd, TPS65910_VDD2_OP, vsel);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500603 break;
604 case TPS65911_REG_VDDCTRL:
Laxman Dewanganc4632ae2012-03-07 16:39:05 +0530605 vsel = selector + 3;
Axel Linfaa95fd2012-07-11 19:44:13 +0800606 tps65910_reg_write(pmic->mfd, TPS65911_VDDCTRL_OP, vsel);
Graeme Gregory518fb722011-05-02 16:20:08 -0500607 }
608
609 return 0;
610}
611
Axel Lin94732b92012-03-09 10:22:20 +0800612static int tps65910_set_voltage_sel(struct regulator_dev *dev,
613 unsigned selector)
Graeme Gregory518fb722011-05-02 16:20:08 -0500614{
615 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
616 int reg, id = rdev_get_id(dev);
617
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500618 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500619 if (reg < 0)
620 return reg;
621
622 switch (id) {
623 case TPS65910_REG_VIO:
624 case TPS65910_REG_VDIG1:
625 case TPS65910_REG_VDIG2:
626 case TPS65910_REG_VPLL:
627 case TPS65910_REG_VDAC:
628 case TPS65910_REG_VAUX1:
629 case TPS65910_REG_VAUX2:
630 case TPS65910_REG_VAUX33:
631 case TPS65910_REG_VMMC:
Axel Linfaa95fd2012-07-11 19:44:13 +0800632 return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK,
633 selector << LDO_SEL_SHIFT);
Graeme Gregory518fb722011-05-02 16:20:08 -0500634 }
635
636 return -EINVAL;
637}
638
Axel Lin94732b92012-03-09 10:22:20 +0800639static int tps65911_set_voltage_sel(struct regulator_dev *dev,
640 unsigned selector)
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500641{
642 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
643 int reg, id = rdev_get_id(dev);
644
645 reg = pmic->get_ctrl_reg(id);
646 if (reg < 0)
647 return reg;
648
649 switch (id) {
650 case TPS65911_REG_LDO1:
651 case TPS65911_REG_LDO2:
652 case TPS65911_REG_LDO4:
Axel Linfaa95fd2012-07-11 19:44:13 +0800653 return tps65910_reg_update_bits(pmic->mfd, reg, LDO1_SEL_MASK,
654 selector << LDO_SEL_SHIFT);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500655 case TPS65911_REG_LDO3:
656 case TPS65911_REG_LDO5:
657 case TPS65911_REG_LDO6:
658 case TPS65911_REG_LDO7:
659 case TPS65911_REG_LDO8:
Axel Linfaa95fd2012-07-11 19:44:13 +0800660 return tps65910_reg_update_bits(pmic->mfd, reg, LDO3_SEL_MASK,
661 selector << LDO_SEL_SHIFT);
Laxman Dewangane882eae2012-02-17 18:56:11 +0530662 case TPS65910_REG_VIO:
Axel Linfaa95fd2012-07-11 19:44:13 +0800663 return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK,
664 selector << LDO_SEL_SHIFT);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500665 }
666
667 return -EINVAL;
668}
669
670
Graeme Gregory518fb722011-05-02 16:20:08 -0500671static int tps65910_list_voltage_dcdc(struct regulator_dev *dev,
672 unsigned selector)
673{
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500674 int volt, mult = 1, id = rdev_get_id(dev);
Graeme Gregory518fb722011-05-02 16:20:08 -0500675
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500676 switch (id) {
677 case TPS65910_REG_VDD1:
678 case TPS65910_REG_VDD2:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530679 mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500680 volt = VDD1_2_MIN_VOLT +
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530681 (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET;
Axel Lind04156b2011-07-10 21:44:09 +0800682 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500683 case TPS65911_REG_VDDCTRL:
684 volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET);
Axel Lind04156b2011-07-10 21:44:09 +0800685 break;
686 default:
687 BUG();
688 return -EINVAL;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500689 }
Graeme Gregory518fb722011-05-02 16:20:08 -0500690
691 return volt * 100 * mult;
692}
693
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500694static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector)
695{
696 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
697 int step_mv = 0, id = rdev_get_id(dev);
698
699 switch(id) {
700 case TPS65911_REG_LDO1:
701 case TPS65911_REG_LDO2:
702 case TPS65911_REG_LDO4:
703 /* The first 5 values of the selector correspond to 1V */
704 if (selector < 5)
705 selector = 0;
706 else
707 selector -= 4;
708
709 step_mv = 50;
710 break;
711 case TPS65911_REG_LDO3:
712 case TPS65911_REG_LDO5:
713 case TPS65911_REG_LDO6:
714 case TPS65911_REG_LDO7:
715 case TPS65911_REG_LDO8:
716 /* The first 3 values of the selector correspond to 1V */
717 if (selector < 3)
718 selector = 0;
719 else
720 selector -= 2;
721
722 step_mv = 100;
723 break;
724 case TPS65910_REG_VIO:
Axel Lind9fe28f2012-06-21 18:48:00 +0800725 return pmic->info[id]->voltage_table[selector];
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500726 default:
727 return -EINVAL;
728 }
729
730 return (LDO_MIN_VOLT + selector * step_mv) * 1000;
731}
732
Graeme Gregory518fb722011-05-02 16:20:08 -0500733/* Regulator ops (except VRTC) */
734static struct regulator_ops tps65910_ops_dcdc = {
Axel Lina40a9c42012-04-17 14:34:46 +0800735 .is_enabled = regulator_is_enabled_regmap,
736 .enable = regulator_enable_regmap,
737 .disable = regulator_disable_regmap,
Graeme Gregory518fb722011-05-02 16:20:08 -0500738 .set_mode = tps65910_set_mode,
739 .get_mode = tps65910_get_mode,
Laxman Dewangan18039e02012-03-14 13:00:58 +0530740 .get_voltage_sel = tps65910_get_voltage_dcdc_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800741 .set_voltage_sel = tps65910_set_voltage_dcdc_sel,
Axel Lin01bc3a12012-06-20 22:40:10 +0800742 .set_voltage_time_sel = regulator_set_voltage_time_sel,
Graeme Gregory518fb722011-05-02 16:20:08 -0500743 .list_voltage = tps65910_list_voltage_dcdc,
744};
745
746static struct regulator_ops tps65910_ops_vdd3 = {
Axel Lina40a9c42012-04-17 14:34:46 +0800747 .is_enabled = regulator_is_enabled_regmap,
748 .enable = regulator_enable_regmap,
749 .disable = regulator_disable_regmap,
Graeme Gregory518fb722011-05-02 16:20:08 -0500750 .set_mode = tps65910_set_mode,
751 .get_mode = tps65910_get_mode,
752 .get_voltage = tps65910_get_voltage_vdd3,
Axel Lind9fe28f2012-06-21 18:48:00 +0800753 .list_voltage = regulator_list_voltage_table,
Graeme Gregory518fb722011-05-02 16:20:08 -0500754};
755
756static struct regulator_ops tps65910_ops = {
Axel Lina40a9c42012-04-17 14:34:46 +0800757 .is_enabled = regulator_is_enabled_regmap,
758 .enable = regulator_enable_regmap,
759 .disable = regulator_disable_regmap,
Graeme Gregory518fb722011-05-02 16:20:08 -0500760 .set_mode = tps65910_set_mode,
761 .get_mode = tps65910_get_mode,
Axel Lin1f904fd2012-05-09 09:22:47 +0800762 .get_voltage_sel = tps65910_get_voltage_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800763 .set_voltage_sel = tps65910_set_voltage_sel,
Axel Lind9fe28f2012-06-21 18:48:00 +0800764 .list_voltage = regulator_list_voltage_table,
Graeme Gregory518fb722011-05-02 16:20:08 -0500765};
766
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500767static struct regulator_ops tps65911_ops = {
Axel Lina40a9c42012-04-17 14:34:46 +0800768 .is_enabled = regulator_is_enabled_regmap,
769 .enable = regulator_enable_regmap,
770 .disable = regulator_disable_regmap,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500771 .set_mode = tps65910_set_mode,
772 .get_mode = tps65910_get_mode,
Axel Lin1f904fd2012-05-09 09:22:47 +0800773 .get_voltage_sel = tps65911_get_voltage_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800774 .set_voltage_sel = tps65911_set_voltage_sel,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500775 .list_voltage = tps65911_list_voltage,
776};
777
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530778static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
779 int id, int ext_sleep_config)
780{
781 struct tps65910 *mfd = pmic->mfd;
782 u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF;
783 u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF);
784 int ret;
785
786 /*
787 * Regulator can not be control from multiple external input EN1, EN2
788 * and EN3 together.
789 */
790 if (ext_sleep_config & EXT_SLEEP_CONTROL) {
791 int en_count;
792 en_count = ((ext_sleep_config &
793 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0);
794 en_count += ((ext_sleep_config &
795 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0);
796 en_count += ((ext_sleep_config &
797 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0);
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530798 en_count += ((ext_sleep_config &
799 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530800 if (en_count > 1) {
801 dev_err(mfd->dev,
802 "External sleep control flag is not proper\n");
803 return -EINVAL;
804 }
805 }
806
807 pmic->board_ext_control[id] = ext_sleep_config;
808
809 /* External EN1 control */
810 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700811 ret = tps65910_reg_set_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530812 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
813 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700814 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530815 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
816 if (ret < 0) {
817 dev_err(mfd->dev,
818 "Error in configuring external control EN1\n");
819 return ret;
820 }
821
822 /* External EN2 control */
823 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700824 ret = tps65910_reg_set_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530825 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
826 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700827 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530828 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
829 if (ret < 0) {
830 dev_err(mfd->dev,
831 "Error in configuring external control EN2\n");
832 return ret;
833 }
834
835 /* External EN3 control for TPS65910 LDO only */
836 if ((tps65910_chip_id(mfd) == TPS65910) &&
837 (id >= TPS65910_REG_VDIG1)) {
838 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700839 ret = tps65910_reg_set_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530840 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
841 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700842 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530843 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
844 if (ret < 0) {
845 dev_err(mfd->dev,
846 "Error in configuring external control EN3\n");
847 return ret;
848 }
849 }
850
851 /* Return if no external control is selected */
852 if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) {
853 /* Clear all sleep controls */
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700854 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530855 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
856 if (!ret)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700857 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530858 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
859 if (ret < 0)
860 dev_err(mfd->dev,
861 "Error in configuring SLEEP register\n");
862 return ret;
863 }
864
865 /*
866 * For regulator that has separate operational and sleep register make
867 * sure that operational is used and clear sleep register to turn
868 * regulator off when external control is inactive
869 */
870 if ((id == TPS65910_REG_VDD1) ||
871 (id == TPS65910_REG_VDD2) ||
872 ((id == TPS65911_REG_VDDCTRL) &&
873 (tps65910_chip_id(mfd) == TPS65911))) {
874 int op_reg_add = pmic->get_ctrl_reg(id) + 1;
875 int sr_reg_add = pmic->get_ctrl_reg(id) + 2;
Axel Linfaa95fd2012-07-11 19:44:13 +0800876 int opvsel, srvsel;
877
878 ret = tps65910_reg_read(pmic->mfd, op_reg_add, &opvsel);
879 if (ret < 0)
880 return ret;
881 ret = tps65910_reg_read(pmic->mfd, sr_reg_add, &srvsel);
882 if (ret < 0)
883 return ret;
884
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530885 if (opvsel & VDD1_OP_CMD_MASK) {
886 u8 reg_val = srvsel & VDD1_OP_SEL_MASK;
Axel Linfaa95fd2012-07-11 19:44:13 +0800887
888 ret = tps65910_reg_write(pmic->mfd, op_reg_add,
889 reg_val);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530890 if (ret < 0) {
891 dev_err(mfd->dev,
892 "Error in configuring op register\n");
893 return ret;
894 }
895 }
Axel Linfaa95fd2012-07-11 19:44:13 +0800896 ret = tps65910_reg_write(pmic->mfd, sr_reg_add, 0);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530897 if (ret < 0) {
898 dev_err(mfd->dev, "Error in settting sr register\n");
899 return ret;
900 }
901 }
902
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700903 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530904 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530905 if (!ret) {
906 if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700907 ret = tps65910_reg_set_bits(mfd,
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530908 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
909 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700910 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530911 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
912 }
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530913 if (ret < 0)
914 dev_err(mfd->dev,
915 "Error in configuring SLEEP register\n");
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530916
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530917 return ret;
918}
919
Rhyland Klein67901782012-05-08 11:42:41 -0700920#ifdef CONFIG_OF
921
922static struct of_regulator_match tps65910_matches[] = {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530923 { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] },
924 { .name = "vio", .driver_data = (void *) &tps65910_regs[1] },
925 { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] },
926 { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] },
927 { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] },
928 { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] },
929 { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] },
930 { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] },
931 { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] },
932 { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] },
933 { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] },
934 { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] },
935 { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] },
Rhyland Klein67901782012-05-08 11:42:41 -0700936};
937
938static struct of_regulator_match tps65911_matches[] = {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530939 { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] },
940 { .name = "vio", .driver_data = (void *) &tps65911_regs[1] },
941 { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] },
942 { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] },
943 { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] },
944 { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] },
945 { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] },
946 { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] },
947 { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] },
948 { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] },
949 { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] },
950 { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] },
951 { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] },
Rhyland Klein67901782012-05-08 11:42:41 -0700952};
953
954static struct tps65910_board *tps65910_parse_dt_reg_data(
Laxman Dewangan84df8c12012-05-20 21:48:50 +0530955 struct platform_device *pdev,
956 struct of_regulator_match **tps65910_reg_matches)
Rhyland Klein67901782012-05-08 11:42:41 -0700957{
958 struct tps65910_board *pmic_plat_data;
959 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
960 struct device_node *np = pdev->dev.parent->of_node;
961 struct device_node *regulators;
962 struct of_regulator_match *matches;
963 unsigned int prop;
964 int idx = 0, ret, count;
965
966 pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data),
967 GFP_KERNEL);
968
969 if (!pmic_plat_data) {
970 dev_err(&pdev->dev, "Failure to alloc pdata for regulators.\n");
971 return NULL;
972 }
973
974 regulators = of_find_node_by_name(np, "regulators");
Laxman Dewangan92ab9532012-05-20 21:48:49 +0530975 if (!regulators) {
976 dev_err(&pdev->dev, "regulator node not found\n");
977 return NULL;
978 }
Rhyland Klein67901782012-05-08 11:42:41 -0700979
980 switch (tps65910_chip_id(tps65910)) {
981 case TPS65910:
982 count = ARRAY_SIZE(tps65910_matches);
983 matches = tps65910_matches;
984 break;
985 case TPS65911:
986 count = ARRAY_SIZE(tps65911_matches);
987 matches = tps65911_matches;
988 break;
989 default:
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +0530990 dev_err(&pdev->dev, "Invalid tps chip version\n");
Rhyland Klein67901782012-05-08 11:42:41 -0700991 return NULL;
992 }
993
994 ret = of_regulator_match(pdev->dev.parent, regulators, matches, count);
995 if (ret < 0) {
996 dev_err(&pdev->dev, "Error parsing regulator init data: %d\n",
997 ret);
998 return NULL;
999 }
1000
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301001 *tps65910_reg_matches = matches;
1002
Rhyland Klein67901782012-05-08 11:42:41 -07001003 for (idx = 0; idx < count; idx++) {
1004 if (!matches[idx].init_data || !matches[idx].of_node)
1005 continue;
1006
1007 pmic_plat_data->tps65910_pmic_init_data[idx] =
1008 matches[idx].init_data;
1009
1010 ret = of_property_read_u32(matches[idx].of_node,
1011 "ti,regulator-ext-sleep-control", &prop);
1012 if (!ret)
1013 pmic_plat_data->regulator_ext_sleep_control[idx] = prop;
Laxman Dewangan19228a62012-07-06 14:13:12 +05301014
Rhyland Klein67901782012-05-08 11:42:41 -07001015 }
1016
1017 return pmic_plat_data;
1018}
1019#else
1020static inline struct tps65910_board *tps65910_parse_dt_reg_data(
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301021 struct platform_device *pdev,
1022 struct of_regulator_match **tps65910_reg_matches)
Rhyland Klein67901782012-05-08 11:42:41 -07001023{
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301024 *tps65910_reg_matches = NULL;
Mark Brown74ea0e52012-06-15 19:04:33 +01001025 return NULL;
Rhyland Klein67901782012-05-08 11:42:41 -07001026}
1027#endif
1028
Graeme Gregory518fb722011-05-02 16:20:08 -05001029static __devinit int tps65910_probe(struct platform_device *pdev)
1030{
1031 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
Mark Brownc172708d2012-04-04 00:50:22 +01001032 struct regulator_config config = { };
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001033 struct tps_info *info;
Graeme Gregory518fb722011-05-02 16:20:08 -05001034 struct regulator_init_data *reg_data;
1035 struct regulator_dev *rdev;
1036 struct tps65910_reg *pmic;
1037 struct tps65910_board *pmic_plat_data;
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301038 struct of_regulator_match *tps65910_reg_matches = NULL;
Graeme Gregory518fb722011-05-02 16:20:08 -05001039 int i, err;
1040
1041 pmic_plat_data = dev_get_platdata(tps65910->dev);
Rhyland Klein67901782012-05-08 11:42:41 -07001042 if (!pmic_plat_data && tps65910->dev->of_node)
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301043 pmic_plat_data = tps65910_parse_dt_reg_data(pdev,
1044 &tps65910_reg_matches);
Rhyland Klein67901782012-05-08 11:42:41 -07001045
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301046 if (!pmic_plat_data) {
1047 dev_err(&pdev->dev, "Platform data not found\n");
Graeme Gregory518fb722011-05-02 16:20:08 -05001048 return -EINVAL;
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301049 }
Graeme Gregory518fb722011-05-02 16:20:08 -05001050
Axel Lin9eb0c422012-04-11 14:40:18 +08001051 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301052 if (!pmic) {
1053 dev_err(&pdev->dev, "Memory allocation failed for pmic\n");
Graeme Gregory518fb722011-05-02 16:20:08 -05001054 return -ENOMEM;
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301055 }
Graeme Gregory518fb722011-05-02 16:20:08 -05001056
Graeme Gregory518fb722011-05-02 16:20:08 -05001057 pmic->mfd = tps65910;
1058 platform_set_drvdata(pdev, pmic);
1059
1060 /* Give control of all register to control port */
Rhyland Klein3f7e8272012-05-08 11:42:38 -07001061 tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL,
Graeme Gregory518fb722011-05-02 16:20:08 -05001062 DEVCTRL_SR_CTL_I2C_SEL_MASK);
1063
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001064 switch(tps65910_chip_id(tps65910)) {
1065 case TPS65910:
1066 pmic->get_ctrl_reg = &tps65910_get_ctrl_register;
Axel Lin39aa9b62011-07-11 09:57:43 +08001067 pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301068 pmic->ext_sleep_control = tps65910_ext_sleep_control;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001069 info = tps65910_regs;
Axel Lind04156b2011-07-10 21:44:09 +08001070 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001071 case TPS65911:
1072 pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
Axel Lin39aa9b62011-07-11 09:57:43 +08001073 pmic->num_regulators = ARRAY_SIZE(tps65911_regs);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301074 pmic->ext_sleep_control = tps65911_ext_sleep_control;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001075 info = tps65911_regs;
Axel Lind04156b2011-07-10 21:44:09 +08001076 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001077 default:
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301078 dev_err(&pdev->dev, "Invalid tps chip version\n");
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001079 return -ENODEV;
1080 }
1081
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301082 pmic->desc = devm_kzalloc(&pdev->dev, pmic->num_regulators *
Axel Lin39aa9b62011-07-11 09:57:43 +08001083 sizeof(struct regulator_desc), GFP_KERNEL);
1084 if (!pmic->desc) {
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301085 dev_err(&pdev->dev, "Memory alloc fails for desc\n");
1086 return -ENOMEM;
Axel Lin39aa9b62011-07-11 09:57:43 +08001087 }
1088
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301089 pmic->info = devm_kzalloc(&pdev->dev, pmic->num_regulators *
Axel Lin39aa9b62011-07-11 09:57:43 +08001090 sizeof(struct tps_info *), GFP_KERNEL);
1091 if (!pmic->info) {
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301092 dev_err(&pdev->dev, "Memory alloc fails for info\n");
1093 return -ENOMEM;
Axel Lin39aa9b62011-07-11 09:57:43 +08001094 }
1095
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301096 pmic->rdev = devm_kzalloc(&pdev->dev, pmic->num_regulators *
Axel Lin39aa9b62011-07-11 09:57:43 +08001097 sizeof(struct regulator_dev *), GFP_KERNEL);
1098 if (!pmic->rdev) {
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301099 dev_err(&pdev->dev, "Memory alloc fails for rdev\n");
1100 return -ENOMEM;
Axel Lin39aa9b62011-07-11 09:57:43 +08001101 }
1102
Kyle Mannac1fc1482011-11-03 12:08:06 -05001103 for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS;
1104 i++, info++) {
1105
1106 reg_data = pmic_plat_data->tps65910_pmic_init_data[i];
1107
1108 /* Regulator API handles empty constraints but not NULL
1109 * constraints */
1110 if (!reg_data)
1111 continue;
1112
Graeme Gregory518fb722011-05-02 16:20:08 -05001113 /* Register the regulators */
1114 pmic->info[i] = info;
1115
1116 pmic->desc[i].name = info->name;
Laxman Dewangand2cfdb02012-07-17 11:34:06 +05301117 pmic->desc[i].supply_name = info->vin_name;
Axel Lin77fa44d2011-05-12 13:47:50 +08001118 pmic->desc[i].id = i;
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +05301119 pmic->desc[i].n_voltages = info->n_voltages;
Axel Lin94f48ab2012-07-04 09:59:17 +08001120 pmic->desc[i].enable_time = info->enable_time_us;
Graeme Gregory518fb722011-05-02 16:20:08 -05001121
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001122 if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) {
Graeme Gregory518fb722011-05-02 16:20:08 -05001123 pmic->desc[i].ops = &tps65910_ops_dcdc;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +05301124 pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE *
1125 VDD1_2_NUM_VOLT_COARSE;
Axel Lin01bc3a12012-06-20 22:40:10 +08001126 pmic->desc[i].ramp_delay = 12500;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001127 } else if (i == TPS65910_REG_VDD3) {
Axel Lin01bc3a12012-06-20 22:40:10 +08001128 if (tps65910_chip_id(tps65910) == TPS65910) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001129 pmic->desc[i].ops = &tps65910_ops_vdd3;
Axel Lind9fe28f2012-06-21 18:48:00 +08001130 pmic->desc[i].volt_table = info->voltage_table;
Axel Lin01bc3a12012-06-20 22:40:10 +08001131 } else {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001132 pmic->desc[i].ops = &tps65910_ops_dcdc;
Axel Lin01bc3a12012-06-20 22:40:10 +08001133 pmic->desc[i].ramp_delay = 5000;
1134 }
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001135 } else {
Axel Lind9fe28f2012-06-21 18:48:00 +08001136 if (tps65910_chip_id(tps65910) == TPS65910) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001137 pmic->desc[i].ops = &tps65910_ops;
Axel Lind9fe28f2012-06-21 18:48:00 +08001138 pmic->desc[i].volt_table = info->voltage_table;
1139 } else {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001140 pmic->desc[i].ops = &tps65911_ops;
Axel Lind9fe28f2012-06-21 18:48:00 +08001141 }
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001142 }
Graeme Gregory518fb722011-05-02 16:20:08 -05001143
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301144 err = tps65910_set_ext_sleep_config(pmic, i,
1145 pmic_plat_data->regulator_ext_sleep_control[i]);
1146 /*
1147 * Failing on regulator for configuring externally control
1148 * is not a serious issue, just throw warning.
1149 */
1150 if (err < 0)
1151 dev_warn(tps65910->dev,
1152 "Failed to initialise ext control config\n");
1153
Graeme Gregory518fb722011-05-02 16:20:08 -05001154 pmic->desc[i].type = REGULATOR_VOLTAGE;
1155 pmic->desc[i].owner = THIS_MODULE;
Axel Lina40a9c42012-04-17 14:34:46 +08001156 pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i);
1157 pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED;
Graeme Gregory518fb722011-05-02 16:20:08 -05001158
Mark Brownc172708d2012-04-04 00:50:22 +01001159 config.dev = tps65910->dev;
1160 config.init_data = reg_data;
1161 config.driver_data = pmic;
Axel Lina40a9c42012-04-17 14:34:46 +08001162 config.regmap = tps65910->regmap;
Mark Brownc172708d2012-04-04 00:50:22 +01001163
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301164 if (tps65910_reg_matches)
1165 config.of_node = tps65910_reg_matches[i].of_node;
Rhyland Klein67901782012-05-08 11:42:41 -07001166
Mark Brownc172708d2012-04-04 00:50:22 +01001167 rdev = regulator_register(&pmic->desc[i], &config);
Graeme Gregory518fb722011-05-02 16:20:08 -05001168 if (IS_ERR(rdev)) {
1169 dev_err(tps65910->dev,
1170 "failed to register %s regulator\n",
1171 pdev->name);
1172 err = PTR_ERR(rdev);
Axel Lin39aa9b62011-07-11 09:57:43 +08001173 goto err_unregister_regulator;
Graeme Gregory518fb722011-05-02 16:20:08 -05001174 }
1175
1176 /* Save regulator for cleanup */
1177 pmic->rdev[i] = rdev;
1178 }
1179 return 0;
1180
Axel Lin39aa9b62011-07-11 09:57:43 +08001181err_unregister_regulator:
Graeme Gregory518fb722011-05-02 16:20:08 -05001182 while (--i >= 0)
1183 regulator_unregister(pmic->rdev[i]);
Graeme Gregory518fb722011-05-02 16:20:08 -05001184 return err;
1185}
1186
1187static int __devexit tps65910_remove(struct platform_device *pdev)
1188{
Axel Lin39aa9b62011-07-11 09:57:43 +08001189 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
Graeme Gregory518fb722011-05-02 16:20:08 -05001190 int i;
1191
Axel Lin39aa9b62011-07-11 09:57:43 +08001192 for (i = 0; i < pmic->num_regulators; i++)
1193 regulator_unregister(pmic->rdev[i]);
Graeme Gregory518fb722011-05-02 16:20:08 -05001194
Graeme Gregory518fb722011-05-02 16:20:08 -05001195 return 0;
1196}
1197
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301198static void tps65910_shutdown(struct platform_device *pdev)
1199{
1200 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
1201 int i;
1202
1203 /*
1204 * Before bootloader jumps to kernel, it makes sure that required
1205 * external control signals are in desired state so that given rails
1206 * can be configure accordingly.
1207 * If rails are configured to be controlled from external control
1208 * then before shutting down/rebooting the system, the external
1209 * control configuration need to be remove from the rails so that
1210 * its output will be available as per register programming even
1211 * if external controls are removed. This is require when the POR
1212 * value of the control signals are not in active state and before
1213 * bootloader initializes it, the system requires the rail output
1214 * to be active for booting.
1215 */
1216 for (i = 0; i < pmic->num_regulators; i++) {
1217 int err;
1218 if (!pmic->rdev[i])
1219 continue;
1220
1221 err = tps65910_set_ext_sleep_config(pmic, i, 0);
1222 if (err < 0)
1223 dev_err(&pdev->dev,
1224 "Error in clearing external control\n");
1225 }
1226}
1227
Graeme Gregory518fb722011-05-02 16:20:08 -05001228static struct platform_driver tps65910_driver = {
1229 .driver = {
1230 .name = "tps65910-pmic",
1231 .owner = THIS_MODULE,
1232 },
1233 .probe = tps65910_probe,
1234 .remove = __devexit_p(tps65910_remove),
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301235 .shutdown = tps65910_shutdown,
Graeme Gregory518fb722011-05-02 16:20:08 -05001236};
1237
1238static int __init tps65910_init(void)
1239{
1240 return platform_driver_register(&tps65910_driver);
1241}
1242subsys_initcall(tps65910_init);
1243
1244static void __exit tps65910_cleanup(void)
1245{
1246 platform_driver_unregister(&tps65910_driver);
1247}
1248module_exit(tps65910_cleanup);
1249
1250MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
Axel Linae0e6542012-02-21 10:14:55 +08001251MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver");
Graeme Gregory518fb722011-05-02 16:20:08 -05001252MODULE_LICENSE("GPL v2");
1253MODULE_ALIAS("platform:tps65910-pmic");