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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/init.h>
18
19#include <linux/mm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/delay.h>
21#include <linux/bootmem.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/interrupt.h>
23#include <linux/mc146818rtc.h>
24#include <linux/kernel_stat.h>
25#include <linux/sysdev.h>
Venkatesh Pallipadid25bf7e2006-01-11 22:44:24 +010026#include <linux/module.h>
Aaron Durbin39928722006-12-07 02:14:01 +010027#include <linux/ioport.h>
Thomas Gleixnerba7eda42007-10-12 23:04:07 +020028#include <linux/clockchips.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#include <asm/atomic.h>
31#include <asm/smp.h>
32#include <asm/mtrr.h>
33#include <asm/mpspec.h>
34#include <asm/pgalloc.h>
35#include <asm/mach_apic.h>
Andi Kleen75152112005-05-16 21:53:34 -070036#include <asm/nmi.h>
Andi Kleen95833c82006-01-11 22:44:36 +010037#include <asm/idle.h>
Andi Kleen73dea472006-02-03 21:50:50 +010038#include <asm/proto.h>
39#include <asm/timex.h>
john stultz2d0c87c2007-02-16 01:28:18 -080040#include <asm/hpet.h>
Andi Kleen2c8c0e62006-09-26 10:52:32 +020041#include <asm/apic.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042
43int apic_verbosity;
Thomas Gleixnerfb79d222007-10-12 23:04:07 +020044int disable_apic_timer __cpuinitdata;
Chris Wrightbc1d99c2007-10-12 23:04:23 +020045static int apic_calibrate_pmtmr __initdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -070046
Linus Torvalds2e7c2832007-03-23 11:32:31 -070047/* Local APIC timer works in C2? */
48int local_apic_timer_c2_ok;
49EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
50
Aaron Durbin39928722006-12-07 02:14:01 +010051static struct resource *ioapic_resources;
52static struct resource lapic_resource = {
53 .name = "Local APIC",
54 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
55};
56
Thomas Gleixnerd03030e2007-10-12 23:04:06 +020057static unsigned int calibration_result;
58
Thomas Gleixnerba7eda42007-10-12 23:04:07 +020059static int lapic_next_event(unsigned long delta,
60 struct clock_event_device *evt);
61static void lapic_timer_setup(enum clock_event_mode mode,
62 struct clock_event_device *evt);
63
64static void lapic_timer_broadcast(cpumask_t mask);
65
66static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen);
67
68static struct clock_event_device lapic_clockevent = {
69 .name = "lapic",
70 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
71 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
72 .shift = 32,
73 .set_mode = lapic_timer_setup,
74 .set_next_event = lapic_next_event,
75 .broadcast = lapic_timer_broadcast,
76 .rating = 100,
77 .irq = -1,
78};
79static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
80
81static int lapic_next_event(unsigned long delta,
82 struct clock_event_device *evt)
83{
84 apic_write(APIC_TMICT, delta);
85 return 0;
86}
87
88static void lapic_timer_setup(enum clock_event_mode mode,
89 struct clock_event_device *evt)
90{
91 unsigned long flags;
92 unsigned int v;
93
94 /* Lapic used as dummy for broadcast ? */
95 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
96 return;
97
98 local_irq_save(flags);
99
100 switch (mode) {
101 case CLOCK_EVT_MODE_PERIODIC:
102 case CLOCK_EVT_MODE_ONESHOT:
103 __setup_APIC_LVTT(calibration_result,
104 mode != CLOCK_EVT_MODE_PERIODIC, 1);
105 break;
106 case CLOCK_EVT_MODE_UNUSED:
107 case CLOCK_EVT_MODE_SHUTDOWN:
108 v = apic_read(APIC_LVTT);
109 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
110 apic_write(APIC_LVTT, v);
111 break;
112 case CLOCK_EVT_MODE_RESUME:
113 /* Nothing to do here */
114 break;
115 }
116
117 local_irq_restore(flags);
118}
119
120/*
121 * Local APIC timer broadcast function
122 */
123static void lapic_timer_broadcast(cpumask_t mask)
124{
125#ifdef CONFIG_SMP
126 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
127#endif
128}
129
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130static void apic_pm_activate(void);
131
Fernando Luis VazquezCao8339e9f2007-05-02 19:27:17 +0200132void apic_wait_icr_idle(void)
133{
134 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
135 cpu_relax();
136}
137
138unsigned int safe_apic_wait_icr_idle(void)
139{
140 unsigned int send_status;
141 int timeout;
142
143 timeout = 0;
144 do {
145 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
146 if (!send_status)
147 break;
148 udelay(100);
149 } while (timeout++ < 1000);
150
151 return send_status;
152}
153
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154void enable_NMI_through_LVT0 (void * dummy)
155{
Andi Kleen11a8e772006-01-11 22:46:51 +0100156 unsigned int v;
Thomas Gleixner6935d1f2007-07-21 17:10:17 +0200157
158 /* unmask and set to NMI */
159 v = APIC_DM_NMI;
Andi Kleen11a8e772006-01-11 22:46:51 +0100160 apic_write(APIC_LVT0, v);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161}
162
163int get_maxlvt(void)
164{
Andi Kleen11a8e772006-01-11 22:46:51 +0100165 unsigned int v, maxlvt;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166
167 v = apic_read(APIC_LVR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 maxlvt = GET_APIC_MAXLVT(v);
169 return maxlvt;
170}
171
Andi Kleen3777a952006-02-03 21:51:53 +0100172/*
173 * 'what should we do if we get a hw irq event on an illegal vector'.
174 * each architecture has to answer this themselves.
175 */
176void ack_bad_irq(unsigned int irq)
177{
178 printk("unexpected IRQ trap at vector %02x\n", irq);
179 /*
180 * Currently unexpected vectors happen only on SMP and APIC.
181 * We _must_ ack these because every local APIC has only N
182 * irq slots per priority level, and a 'hanging, unacked' IRQ
183 * holds up an irq slot - in excessive cases (when multiple
184 * unexpected vectors occur) that might lock up the APIC
185 * completely.
Thomas Gleixner6935d1f2007-07-21 17:10:17 +0200186 * But don't ack when the APIC is disabled. -AK
Andi Kleen3777a952006-02-03 21:51:53 +0100187 */
188 if (!disable_apic)
189 ack_APIC_irq();
190}
191
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192void clear_local_APIC(void)
193{
194 int maxlvt;
195 unsigned int v;
196
197 maxlvt = get_maxlvt();
198
199 /*
Siddha, Suresh B704fc592006-06-26 13:59:53 +0200200 * Masking an LVT entry can trigger a local APIC error
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 * if the vector is zero. Mask LVTERR first to prevent this.
202 */
203 if (maxlvt >= 3) {
204 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
Andi Kleen11a8e772006-01-11 22:46:51 +0100205 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206 }
207 /*
208 * Careful: we have to set masks only first to deassert
209 * any level-triggered sources.
210 */
211 v = apic_read(APIC_LVTT);
Andi Kleen11a8e772006-01-11 22:46:51 +0100212 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213 v = apic_read(APIC_LVT0);
Andi Kleen11a8e772006-01-11 22:46:51 +0100214 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 v = apic_read(APIC_LVT1);
Andi Kleen11a8e772006-01-11 22:46:51 +0100216 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217 if (maxlvt >= 4) {
218 v = apic_read(APIC_LVTPC);
Andi Kleen11a8e772006-01-11 22:46:51 +0100219 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 }
221
222 /*
223 * Clean APIC state for other OSs:
224 */
Andi Kleen11a8e772006-01-11 22:46:51 +0100225 apic_write(APIC_LVTT, APIC_LVT_MASKED);
226 apic_write(APIC_LVT0, APIC_LVT_MASKED);
227 apic_write(APIC_LVT1, APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228 if (maxlvt >= 3)
Andi Kleen11a8e772006-01-11 22:46:51 +0100229 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230 if (maxlvt >= 4)
Andi Kleen11a8e772006-01-11 22:46:51 +0100231 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
Andi Kleen5a40b7c2005-09-12 18:49:24 +0200232 apic_write(APIC_ESR, 0);
233 apic_read(APIC_ESR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234}
235
Eric W. Biederman208fb932005-06-25 14:57:45 -0700236void disconnect_bsp_APIC(int virt_wire_setup)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237{
Andi Kleena8fcf1a2006-09-26 10:52:30 +0200238 /* Go back to Virtual Wire compatibility mode */
239 unsigned long value;
240
241 /* For the spurious interrupt use vector F, and enable it */
242 value = apic_read(APIC_SPIV);
243 value &= ~APIC_VECTOR_MASK;
244 value |= APIC_SPIV_APIC_ENABLED;
245 value |= 0xf;
246 apic_write(APIC_SPIV, value);
247
248 if (!virt_wire_setup) {
Chris Wrightbc1d99c2007-10-12 23:04:23 +0200249 /*
250 * For LVT0 make it edge triggered, active high,
251 * external and enabled
252 */
Andi Kleena8fcf1a2006-09-26 10:52:30 +0200253 value = apic_read(APIC_LVT0);
254 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
255 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
256 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
257 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
258 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
259 apic_write(APIC_LVT0, value);
260 } else {
261 /* Disable LVT0 */
262 apic_write(APIC_LVT0, APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263 }
Eric W. Biederman208fb932005-06-25 14:57:45 -0700264
Andi Kleena8fcf1a2006-09-26 10:52:30 +0200265 /* For LVT1 make it edge triggered, active high, nmi and enabled */
266 value = apic_read(APIC_LVT1);
267 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
Eric W. Biederman208fb932005-06-25 14:57:45 -0700268 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
269 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
Andi Kleena8fcf1a2006-09-26 10:52:30 +0200270 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
271 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
272 apic_write(APIC_LVT1, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273}
274
275void disable_local_APIC(void)
276{
277 unsigned int value;
278
279 clear_local_APIC();
280
281 /*
282 * Disable APIC (implies clearing of registers
283 * for 82489DX!).
284 */
285 value = apic_read(APIC_SPIV);
286 value &= ~APIC_SPIV_APIC_ENABLED;
Andi Kleen11a8e772006-01-11 22:46:51 +0100287 apic_write(APIC_SPIV, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288}
289
Hiroshi Shimamoto9b7711f2007-10-19 18:21:11 -0700290void lapic_shutdown(void)
291{
292 unsigned long flags;
293
294 if (!cpu_has_apic)
295 return;
296
297 local_irq_save(flags);
298
299 disable_local_APIC();
300
301 local_irq_restore(flags);
302}
303
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304/*
305 * This is to verify that we're looking at a real local APIC.
306 * Check these against your board if the CPUs aren't getting
307 * started for no apparent reason.
308 */
309int __init verify_local_APIC(void)
310{
311 unsigned int reg0, reg1;
312
313 /*
314 * The version register is read-only in a real APIC.
315 */
316 reg0 = apic_read(APIC_LVR);
317 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
318 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
319 reg1 = apic_read(APIC_LVR);
320 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
321
322 /*
323 * The two version reads above should print the same
324 * numbers. If the second one is different, then we
325 * poke at a non-APIC.
326 */
327 if (reg1 != reg0)
328 return 0;
329
330 /*
331 * Check if the version looks reasonably.
332 */
333 reg1 = GET_APIC_VERSION(reg0);
334 if (reg1 == 0x00 || reg1 == 0xff)
335 return 0;
336 reg1 = get_maxlvt();
337 if (reg1 < 0x02 || reg1 == 0xff)
338 return 0;
339
340 /*
341 * The ID register is read/write in a real APIC.
342 */
343 reg0 = apic_read(APIC_ID);
344 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
345 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
346 reg1 = apic_read(APIC_ID);
347 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
348 apic_write(APIC_ID, reg0);
349 if (reg1 != (reg0 ^ APIC_ID_MASK))
350 return 0;
351
352 /*
353 * The next two are just to see if we have sane values.
354 * They're only really relevant if we're in Virtual Wire
355 * compatibility mode, but most boxes are anymore.
356 */
357 reg0 = apic_read(APIC_LVT0);
358 apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
359 reg1 = apic_read(APIC_LVT1);
360 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
361
362 return 1;
363}
364
365void __init sync_Arb_IDs(void)
366{
367 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
368 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
369 if (ver >= 0x14) /* P4 or higher */
370 return;
371
372 /*
373 * Wait for idle.
374 */
375 apic_wait_icr_idle();
376
377 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
Andi Kleen11a8e772006-01-11 22:46:51 +0100378 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 | APIC_DM_INIT);
380}
381
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382/*
383 * An initial setup of the virtual wire mode.
384 */
385void __init init_bsp_APIC(void)
386{
Andi Kleen11a8e772006-01-11 22:46:51 +0100387 unsigned int value;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388
389 /*
390 * Don't do the setup now if we have a SMP BIOS as the
391 * through-I/O-APIC virtual wire mode might be active.
392 */
393 if (smp_found_config || !cpu_has_apic)
394 return;
395
396 value = apic_read(APIC_LVR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397
398 /*
399 * Do not trust the local APIC being empty at bootup.
400 */
401 clear_local_APIC();
402
403 /*
404 * Enable APIC.
405 */
406 value = apic_read(APIC_SPIV);
407 value &= ~APIC_VECTOR_MASK;
408 value |= APIC_SPIV_APIC_ENABLED;
409 value |= APIC_SPIV_FOCUS_DISABLED;
410 value |= SPURIOUS_APIC_VECTOR;
Andi Kleen11a8e772006-01-11 22:46:51 +0100411 apic_write(APIC_SPIV, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412
413 /*
414 * Set up the virtual wire mode.
415 */
Andi Kleen11a8e772006-01-11 22:46:51 +0100416 apic_write(APIC_LVT0, APIC_DM_EXTINT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417 value = APIC_DM_NMI;
Andi Kleen11a8e772006-01-11 22:46:51 +0100418 apic_write(APIC_LVT1, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419}
420
Ashok Raje6982c62005-06-25 14:54:58 -0700421void __cpuinit setup_local_APIC (void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422{
Andi Kleen11a8e772006-01-11 22:46:51 +0100423 unsigned int value, maxlvt;
Vivek Goyalda7ed9f2006-03-25 16:31:16 +0100424 int i, j;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426 value = apic_read(APIC_LVR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427
Andi Kleenfe7414a2006-09-26 10:52:30 +0200428 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429
430 /*
431 * Double-check whether this APIC is really registered.
432 * This is meaningless in clustered apic mode, so we skip it.
433 */
434 if (!apic_id_registered())
435 BUG();
436
437 /*
438 * Intel recommends to set DFR, LDR and TPR before enabling
439 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
440 * document number 292116). So here it goes...
441 */
442 init_apic_ldr();
443
444 /*
445 * Set Task Priority to 'accept all'. We never change this
446 * later on.
447 */
448 value = apic_read(APIC_TASKPRI);
449 value &= ~APIC_TPRI_MASK;
Andi Kleen11a8e772006-01-11 22:46:51 +0100450 apic_write(APIC_TASKPRI, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451
452 /*
Vivek Goyalda7ed9f2006-03-25 16:31:16 +0100453 * After a crash, we no longer service the interrupts and a pending
454 * interrupt from previous kernel might still have ISR bit set.
455 *
456 * Most probably by now CPU has serviced that pending interrupt and
457 * it might not have done the ack_APIC_irq() because it thought,
458 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
459 * does not clear the ISR bit and cpu thinks it has already serivced
460 * the interrupt. Hence a vector might get locked. It was noticed
461 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
462 */
463 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
464 value = apic_read(APIC_ISR + i*0x10);
465 for (j = 31; j >= 0; j--) {
466 if (value & (1<<j))
467 ack_APIC_irq();
468 }
469 }
470
471 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472 * Now that we are all set up, enable the APIC
473 */
474 value = apic_read(APIC_SPIV);
475 value &= ~APIC_VECTOR_MASK;
476 /*
477 * Enable APIC
478 */
479 value |= APIC_SPIV_APIC_ENABLED;
480
Andi Kleen3f14c742006-09-26 10:52:29 +0200481 /* We always use processor focus */
482
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483 /*
484 * Set spurious IRQ vector
485 */
486 value |= SPURIOUS_APIC_VECTOR;
Andi Kleen11a8e772006-01-11 22:46:51 +0100487 apic_write(APIC_SPIV, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488
489 /*
490 * Set up LVT0, LVT1:
491 *
492 * set up through-local-APIC on the BP's LINT0. This is not
493 * strictly necessary in pure symmetric-IO mode, but sometimes
494 * we delegate interrupts to the 8259A.
495 */
496 /*
497 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
498 */
499 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
Andi Kleena8fcf1a2006-09-26 10:52:30 +0200500 if (!smp_processor_id() && !value) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501 value = APIC_DM_EXTINT;
Chris Wrightbc1d99c2007-10-12 23:04:23 +0200502 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
503 smp_processor_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504 } else {
505 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
Chris Wrightbc1d99c2007-10-12 23:04:23 +0200506 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
507 smp_processor_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508 }
Andi Kleen11a8e772006-01-11 22:46:51 +0100509 apic_write(APIC_LVT0, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510
511 /*
512 * only the BP should see the LINT1 NMI signal, obviously.
513 */
514 if (!smp_processor_id())
515 value = APIC_DM_NMI;
516 else
517 value = APIC_DM_NMI | APIC_LVT_MASKED;
Andi Kleen11a8e772006-01-11 22:46:51 +0100518 apic_write(APIC_LVT1, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519
Andi Kleen61c11342005-09-12 18:49:23 +0200520 {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521 unsigned oldvalue;
522 maxlvt = get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523 oldvalue = apic_read(APIC_ESR);
524 value = ERROR_APIC_VECTOR; // enables sending errors
Andi Kleen11a8e772006-01-11 22:46:51 +0100525 apic_write(APIC_LVTERR, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526 /*
527 * spec says clear errors after enabling vector.
528 */
529 if (maxlvt > 3)
530 apic_write(APIC_ESR, 0);
531 value = apic_read(APIC_ESR);
532 if (value != oldvalue)
533 apic_printk(APIC_VERBOSE,
534 "ESR value after enabling vector: %08x, after %08x\n",
535 oldvalue, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536 }
537
538 nmi_watchdog_default();
Don Zickusf2802e72006-09-26 10:52:26 +0200539 setup_apic_nmi_watchdog(NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540 apic_pm_activate();
541}
542
543#ifdef CONFIG_PM
544
545static struct {
546 /* 'active' is true if the local APIC was enabled by us and
547 not the BIOS; this signifies that we are also responsible
548 for disabling it before entering apm/acpi suspend */
549 int active;
550 /* r/w apic fields */
551 unsigned int apic_id;
552 unsigned int apic_taskpri;
553 unsigned int apic_ldr;
554 unsigned int apic_dfr;
555 unsigned int apic_spiv;
556 unsigned int apic_lvtt;
557 unsigned int apic_lvtpc;
558 unsigned int apic_lvt0;
559 unsigned int apic_lvt1;
560 unsigned int apic_lvterr;
561 unsigned int apic_tmict;
562 unsigned int apic_tdcr;
563 unsigned int apic_thmr;
564} apic_pm_state;
565
Pavel Machek0b9c33a72005-04-16 15:25:31 -0700566static int lapic_suspend(struct sys_device *dev, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567{
568 unsigned long flags;
Karsten Wiesef990fff2006-12-07 02:14:11 +0100569 int maxlvt;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700570
571 if (!apic_pm_state.active)
572 return 0;
573
Karsten Wiesef990fff2006-12-07 02:14:11 +0100574 maxlvt = get_maxlvt();
575
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576 apic_pm_state.apic_id = apic_read(APIC_ID);
577 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
578 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
579 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
580 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
581 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
Karsten Wiesef990fff2006-12-07 02:14:11 +0100582 if (maxlvt >= 4)
583 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
585 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
586 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
587 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
588 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
Karsten Wiesef990fff2006-12-07 02:14:11 +0100589#ifdef CONFIG_X86_MCE_INTEL
590 if (maxlvt >= 5)
591 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
592#endif
Fernando Luis Vázquez Cao2b94ab22006-09-26 10:52:33 +0200593 local_irq_save(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594 disable_local_APIC();
595 local_irq_restore(flags);
596 return 0;
597}
598
599static int lapic_resume(struct sys_device *dev)
600{
601 unsigned int l, h;
602 unsigned long flags;
Karsten Wiesef990fff2006-12-07 02:14:11 +0100603 int maxlvt;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604
605 if (!apic_pm_state.active)
606 return 0;
607
Karsten Wiesef990fff2006-12-07 02:14:11 +0100608 maxlvt = get_maxlvt();
609
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610 local_irq_save(flags);
611 rdmsr(MSR_IA32_APICBASE, l, h);
612 l &= ~MSR_IA32_APICBASE_BASE;
Shaohua Li5b743572006-01-16 01:56:45 +0100613 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 wrmsr(MSR_IA32_APICBASE, l, h);
615 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
616 apic_write(APIC_ID, apic_pm_state.apic_id);
617 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
618 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
619 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
620 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
621 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
622 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
Karsten Wiesef990fff2006-12-07 02:14:11 +0100623#ifdef CONFIG_X86_MCE_INTEL
624 if (maxlvt >= 5)
625 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
626#endif
627 if (maxlvt >= 4)
628 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
630 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
631 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
632 apic_write(APIC_ESR, 0);
633 apic_read(APIC_ESR);
634 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
635 apic_write(APIC_ESR, 0);
636 apic_read(APIC_ESR);
637 local_irq_restore(flags);
638 return 0;
639}
640
641static struct sysdev_class lapic_sysclass = {
Kay Sieversaf5ca3f42007-12-20 02:09:39 +0100642 .name = "lapic",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643 .resume = lapic_resume,
644 .suspend = lapic_suspend,
645};
646
647static struct sys_device device_lapic = {
648 .id = 0,
649 .cls = &lapic_sysclass,
650};
651
Ashok Raje6982c62005-06-25 14:54:58 -0700652static void __cpuinit apic_pm_activate(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653{
654 apic_pm_state.active = 1;
655}
656
657static int __init init_lapic_sysfs(void)
658{
659 int error;
660 if (!cpu_has_apic)
661 return 0;
662 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
663 error = sysdev_class_register(&lapic_sysclass);
664 if (!error)
665 error = sysdev_register(&device_lapic);
666 return error;
667}
668device_initcall(init_lapic_sysfs);
669
670#else /* CONFIG_PM */
671
672static void apic_pm_activate(void) { }
673
674#endif /* CONFIG_PM */
675
676static int __init apic_set_verbosity(char *str)
677{
Andi Kleen2c8c0e62006-09-26 10:52:32 +0200678 if (str == NULL) {
679 skip_ioapic_setup = 0;
680 ioapic_force = 1;
681 return 0;
682 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 if (strcmp("debug", str) == 0)
684 apic_verbosity = APIC_DEBUG;
685 else if (strcmp("verbose", str) == 0)
686 apic_verbosity = APIC_VERBOSE;
Andi Kleen2c8c0e62006-09-26 10:52:32 +0200687 else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
Andi Kleen2c8c0e62006-09-26 10:52:32 +0200689 " use apic=verbose or apic=debug\n", str);
690 return -EINVAL;
691 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692
Andi Kleen2c8c0e62006-09-26 10:52:32 +0200693 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694}
Andi Kleen2c8c0e62006-09-26 10:52:32 +0200695early_param("apic", apic_set_verbosity);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696
697/*
698 * Detect and enable local APICs on non-SMP boards.
699 * Original code written by Keir Fraser.
700 * On AMD64 we trust the BIOS - if it says no APIC it is likely
Thomas Gleixner6935d1f2007-07-21 17:10:17 +0200701 * not correctly set up (usually the APIC timer won't work etc.)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702 */
703
704static int __init detect_init_APIC (void)
705{
706 if (!cpu_has_apic) {
707 printk(KERN_INFO "No local APIC present\n");
708 return -1;
709 }
710
711 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
712 boot_cpu_id = 0;
713 return 0;
714}
715
Aaron Durbin39928722006-12-07 02:14:01 +0100716#ifdef CONFIG_X86_IO_APIC
717static struct resource * __init ioapic_setup_resources(void)
718{
719#define IOAPIC_RESOURCE_NAME_SIZE 11
720 unsigned long n;
721 struct resource *res;
722 char *mem;
723 int i;
724
725 if (nr_ioapics <= 0)
726 return NULL;
727
728 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
729 n *= nr_ioapics;
730
731 mem = alloc_bootmem(n);
732 res = (void *)mem;
733
734 if (mem != NULL) {
735 memset(mem, 0, n);
736 mem += sizeof(struct resource) * nr_ioapics;
737
738 for (i = 0; i < nr_ioapics; i++) {
739 res[i].name = mem;
740 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
741 sprintf(mem, "IOAPIC %u", i);
742 mem += IOAPIC_RESOURCE_NAME_SIZE;
743 }
744 }
745
746 ioapic_resources = res;
747
748 return res;
749}
750
751static int __init ioapic_insert_resources(void)
752{
753 int i;
754 struct resource *r = ioapic_resources;
755
756 if (!r) {
757 printk("IO APIC resources could be not be allocated.\n");
758 return -1;
759 }
760
761 for (i = 0; i < nr_ioapics; i++) {
762 insert_resource(&iomem_resource, r);
763 r++;
764 }
765
766 return 0;
767}
768
769/* Insert the IO APIC resources after PCI initialization has occured to handle
770 * IO APICS that are mapped in on a BAR in PCI space. */
771late_initcall(ioapic_insert_resources);
772#endif
773
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774void __init init_apic_mappings(void)
775{
776 unsigned long apic_phys;
777
778 /*
779 * If no local APIC can be found then set up a fake all
780 * zeroes page to simulate the local APIC and another
781 * one for the IO-APIC.
782 */
783 if (!smp_found_config && detect_init_APIC()) {
784 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
785 apic_phys = __pa(apic_phys);
786 } else
787 apic_phys = mp_lapic_addr;
788
789 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
Yinghai Lu7ffeeb12007-10-12 23:04:06 +0200790 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
791 APIC_BASE, apic_phys);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792
Aaron Durbin39928722006-12-07 02:14:01 +0100793 /* Put local APIC into the resource map. */
794 lapic_resource.start = apic_phys;
795 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
796 insert_resource(&iomem_resource, &lapic_resource);
797
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798 /*
799 * Fetch the APIC ID of the BSP in case we have a
800 * default configuration (or the MP table is broken).
801 */
Andi Kleen1d3fbbf2005-09-12 18:49:24 +0200802 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700803
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804 {
805 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
806 int i;
Aaron Durbin39928722006-12-07 02:14:01 +0100807 struct resource *ioapic_res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808
Aaron Durbin39928722006-12-07 02:14:01 +0100809 ioapic_res = ioapic_setup_resources();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 for (i = 0; i < nr_ioapics; i++) {
811 if (smp_found_config) {
812 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
813 } else {
Chris Wrightbc1d99c2007-10-12 23:04:23 +0200814 ioapic_phys = (unsigned long)
815 alloc_bootmem_pages(PAGE_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816 ioapic_phys = __pa(ioapic_phys);
817 }
818 set_fixmap_nocache(idx, ioapic_phys);
Chris Wrightbc1d99c2007-10-12 23:04:23 +0200819 apic_printk(APIC_VERBOSE,
820 "mapped IOAPIC to %016lx (%016lx)\n",
821 __fix_to_virt(idx), ioapic_phys);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822 idx++;
Aaron Durbin39928722006-12-07 02:14:01 +0100823
824 if (ioapic_res != NULL) {
825 ioapic_res->start = ioapic_phys;
826 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
827 ioapic_res++;
828 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829 }
830 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831}
832
833/*
834 * This function sets up the local APIC timer, with a timeout of
835 * 'clocks' APIC bus clock. During calibration we actually call
836 * this function twice on the boot CPU, once with a bogus timeout
837 * value, second time for real. The other (noncalibrating) CPUs
838 * call this function only once, with the real, calibrated value.
839 *
840 * We do reads before writes even if unnecessary, to get around the
841 * P5 APIC double write bug.
842 */
843
Thomas Gleixner80174092007-10-12 23:04:06 +0200844static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845{
David Rientjes86bd58b2006-12-07 02:14:11 +0100846 unsigned int lvtt_value, tmp_value;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847
Thomas Gleixner80174092007-10-12 23:04:06 +0200848 lvtt_value = LOCAL_TIMER_VECTOR;
849 if (!oneshot)
850 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
851 if (!irqen)
Venkatesh Pallipadid25bf7e2006-01-11 22:44:24 +0100852 lvtt_value |= APIC_LVT_MASKED;
853
Andi Kleen11a8e772006-01-11 22:46:51 +0100854 apic_write(APIC_LVTT, lvtt_value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700855
856 /*
857 * Divide PICLK by 16
858 */
859 tmp_value = apic_read(APIC_TDCR);
Andi Kleen11a8e772006-01-11 22:46:51 +0100860 apic_write(APIC_TDCR, (tmp_value
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
862 | APIC_TDR_DIV_16);
863
Thomas Gleixner80174092007-10-12 23:04:06 +0200864 if (!oneshot)
Thomas Gleixnerb58eb002007-10-12 23:04:06 +0200865 apic_write(APIC_TMICT, clocks);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866}
867
Thomas Gleixnerabc63fc2007-10-12 23:04:07 +0200868static void setup_APIC_timer(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869{
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200870 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200872 memcpy(levt, &lapic_clockevent, sizeof(*levt));
873 levt->cpumask = cpumask_of_cpu(smp_processor_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200875 clockevents_register_device(levt);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876}
877
878/*
879 * In this function we calibrate APIC bus clocks to the external
880 * timer. Unfortunately we cannot use jiffies and the timer irq
881 * to calibrate, since some later bootup code depends on getting
882 * the first irq? Ugh.
883 *
884 * We want to do the calibration only once since we
885 * want to have local timer irqs syncron. CPUs connected
886 * by the same APIC bus have the very same bus frequency.
887 * And we want to have irqs off anyways, no accidental
888 * APIC irq that way.
889 */
890
891#define TICK_COUNT 100000000
892
Thomas Gleixnerd03030e2007-10-12 23:04:06 +0200893static void __init calibrate_APIC_clock(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894{
David P. Reed4637a742007-05-02 19:27:20 +0200895 unsigned apic, apic_start;
896 unsigned long tsc, tsc_start;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897 int result;
Thomas Gleixnerc4d58cb2007-10-12 23:04:07 +0200898
899 local_irq_disable();
900
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901 /*
902 * Put whatever arbitrary (but long enough) timeout
903 * value into the APIC clock, we just want to get the
904 * counter running for calibration.
Thomas Gleixner80174092007-10-12 23:04:06 +0200905 *
906 * No interrupt enable !
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907 */
Thomas Gleixnerb58eb002007-10-12 23:04:06 +0200908 __setup_APIC_LVTT(250000000, 0, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909
910 apic_start = apic_read(APIC_TMCCT);
Andi Kleen0c3749c2006-02-03 21:51:41 +0100911#ifdef CONFIG_X86_PM_TIMER
912 if (apic_calibrate_pmtmr && pmtmr_ioport) {
913 pmtimer_wait(5000); /* 5ms wait */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914 apic = apic_read(APIC_TMCCT);
Andi Kleen0c3749c2006-02-03 21:51:41 +0100915 result = (apic_start - apic) * 1000L / 5;
916 } else
917#endif
918 {
David P. Reed4637a742007-05-02 19:27:20 +0200919 rdtscll(tsc_start);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920
Andi Kleen0c3749c2006-02-03 21:51:41 +0100921 do {
922 apic = apic_read(APIC_TMCCT);
David P. Reed4637a742007-05-02 19:27:20 +0200923 rdtscll(tsc);
Andi Kleen0c3749c2006-02-03 21:51:41 +0100924 } while ((tsc - tsc_start) < TICK_COUNT &&
David P. Reed4637a742007-05-02 19:27:20 +0200925 (apic_start - apic) < TICK_COUNT);
Andi Kleen0c3749c2006-02-03 21:51:41 +0100926
Joerg Roedel6b37f5a2007-05-02 19:27:06 +0200927 result = (apic_start - apic) * 1000L * tsc_khz /
Andi Kleen0c3749c2006-02-03 21:51:41 +0100928 (tsc - tsc_start);
929 }
Thomas Gleixnerc4d58cb2007-10-12 23:04:07 +0200930
931 local_irq_enable();
932
Thomas Gleixnerd03030e2007-10-12 23:04:06 +0200933 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934
935 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
936 result / 1000 / 1000, result / 1000 % 1000);
937
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200938 /* Calculate the scaled math multiplication factor */
939 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, 32);
940 lapic_clockevent.max_delta_ns =
941 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
942 lapic_clockevent.min_delta_ns =
943 clockevent_delta2ns(0xF, &lapic_clockevent);
944
Thomas Gleixnerb58eb002007-10-12 23:04:06 +0200945 calibration_result = result / HZ;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946}
947
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948void __init setup_boot_APIC_clock (void)
949{
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200950 /*
951 * The local apic timer can be disabled via the kernel commandline.
952 * Register the lapic timer as a dummy clock event source on SMP
953 * systems, so the broadcast mechanism is used. On UP systems simply
954 * ignore it.
955 */
Thomas Gleixner6935d1f2007-07-21 17:10:17 +0200956 if (disable_apic_timer) {
957 printk(KERN_INFO "Disabling APIC timer\n");
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200958 /* No broadcast on UP ! */
959 if (num_possible_cpus() > 1)
960 setup_APIC_timer();
Thomas Gleixner6935d1f2007-07-21 17:10:17 +0200961 return;
962 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700963
964 printk(KERN_INFO "Using local APIC timer interrupts.\n");
Thomas Gleixnerd03030e2007-10-12 23:04:06 +0200965 calibrate_APIC_clock();
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200966
Linus Torvalds1da177e2005-04-16 15:20:36 -0700967 /*
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200968 * If nmi_watchdog is set to IO_APIC, we need the
969 * PIT/HPET going. Otherwise register lapic as a dummy
970 * device.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971 */
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +0200972 if (nmi_watchdog != NMI_IO_APIC)
973 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
974 else
975 printk(KERN_WARNING "APIC timer registered as dummy,"
976 " due to nmi_watchdog=1!\n");
977
Thomas Gleixnerabc63fc2007-10-12 23:04:07 +0200978 setup_APIC_timer();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700979}
980
Thomas Gleixner89039b32007-10-14 22:57:45 +0200981/*
982 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
983 * C1E flag only in the secondary CPU, so when we detect the wreckage
984 * we already have enabled the boot CPU local apic timer. Check, if
985 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
986 * set the DUMMY flag again and force the broadcast mode in the
987 * clockevents layer.
988 */
989void __cpuinit check_boot_apic_timer_broadcast(void)
990{
Thomas Gleixner89039b32007-10-14 22:57:45 +0200991 if (!disable_apic_timer ||
992 (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY))
993 return;
994
995 printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n");
996 lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY;
Thomas Gleixner89039b32007-10-14 22:57:45 +0200997
998 local_irq_enable();
999 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, &boot_cpu_id);
1000 local_irq_disable();
1001}
1002
Ashok Raje6982c62005-06-25 14:54:58 -07001003void __cpuinit setup_secondary_APIC_clock(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004{
Thomas Gleixner89039b32007-10-14 22:57:45 +02001005 check_boot_apic_timer_broadcast();
Thomas Gleixnerabc63fc2007-10-12 23:04:07 +02001006 setup_APIC_timer();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007}
1008
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009int setup_profiling_timer(unsigned int multiplier)
1010{
Venkatesh Pallipadi5a07a302006-01-11 22:44:18 +01001011 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001012}
1013
Thomas Gleixnerf40f31b2007-07-21 17:10:14 +02001014void setup_APIC_extended_lvt(unsigned char lvt_off, unsigned char vector,
1015 unsigned char msg_type, unsigned char mask)
Jacob Shin89b831e2005-11-05 17:25:53 +01001016{
Jacob Shin17fc14f2006-06-26 13:58:47 +02001017 unsigned long reg = (lvt_off << 4) + K8_APIC_EXT_LVT_BASE;
1018 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
Jacob Shin89b831e2005-11-05 17:25:53 +01001019 apic_write(reg, v);
1020}
Jacob Shin89b831e2005-11-05 17:25:53 +01001021
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022/*
1023 * Local timer interrupt handler. It does both profiling and
1024 * process statistics/rescheduling.
1025 *
1026 * We do profiling in every local tick, statistics/rescheduling
1027 * happen only every 'profiling multiplier' ticks. The default
1028 * multiplier is 1 and it can be changed by writing the new multiplier
1029 * value into /proc/profile.
1030 */
1031
David Howells7d12e782006-10-05 14:55:46 +01001032void smp_local_timer_interrupt(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001033{
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +02001034 int cpu = smp_processor_id();
1035 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
1036
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037 /*
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +02001038 * Normally we should not be here till LAPIC has been initialized but
1039 * in some cases like kdump, its possible that there is a pending LAPIC
1040 * timer interrupt from previous kernel's context and is delivered in
1041 * new kernel the moment interrupts are enabled.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001042 *
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +02001043 * Interrupts are enabled early and LAPIC is setup much later, hence
1044 * its possible that when we get here evt->event_handler is NULL.
1045 * Check for event_handler being NULL and discard the interrupt as
1046 * spurious.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001047 */
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +02001048 if (!evt->event_handler) {
1049 printk(KERN_WARNING
1050 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
1051 /* Switch it off */
1052 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
1053 return;
1054 }
1055
1056 /*
1057 * the NMI deadlock-detector uses this.
1058 */
1059 add_pda(apic_timer_irqs, 1);
1060
1061 evt->event_handler(evt);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001062}
1063
1064/*
1065 * Local APIC timer interrupt. This is the most natural way for doing
1066 * local interrupts, but local timer interrupts can be emulated by
1067 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1068 *
1069 * [ if a single-CPU system runs an SMP kernel then we call the local
1070 * interrupt as well. Thus we cannot inline the local irq ... ]
1071 */
Andrew Mortond150ad72006-10-06 13:28:09 -07001072void smp_apic_timer_interrupt(struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001073{
Andrew Mortond150ad72006-10-06 13:28:09 -07001074 struct pt_regs *old_regs = set_irq_regs(regs);
1075
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077 * NOTE! We'd better ACK the irq immediately,
1078 * because timer handling can be slow.
1079 */
1080 ack_APIC_irq();
1081 /*
1082 * update_process_times() expects us to have done irq_enter().
1083 * Besides, if we don't timer interrupts ignore the global
1084 * interrupt lock, which is the WrongThing (tm) to do.
1085 */
Andi Kleen95833c82006-01-11 22:44:36 +01001086 exit_idle();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087 irq_enter();
David Howells7d12e782006-10-05 14:55:46 +01001088 smp_local_timer_interrupt();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089 irq_exit();
Andrew Mortond150ad72006-10-06 13:28:09 -07001090 set_irq_regs(old_regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001091}
1092
1093/*
Vojtech Pavlikf8bf3c62006-06-26 13:58:23 +02001094 * apic_is_clustered_box() -- Check if we can expect good TSC
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095 *
1096 * Thus far, the major user of this is IBM's Summit2 series:
1097 *
Linus Torvalds637029c2006-02-27 20:41:56 -08001098 * Clustered boxes may have unsynced TSC problems if they are
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099 * multi-chassis. Use available data to take a good guess.
1100 * If in doubt, go HPET.
1101 */
Vojtech Pavlikf8bf3c62006-06-26 13:58:23 +02001102__cpuinit int apic_is_clustered_box(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103{
1104 int i, clusters, zeros;
1105 unsigned id;
1106 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1107
Suresh Siddha376ec33f2005-05-16 21:53:32 -07001108 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109
1110 for (i = 0; i < NR_CPUS; i++) {
1111 id = bios_cpu_apicid[i];
1112 if (id != BAD_APICID)
1113 __set_bit(APIC_CLUSTERID(id), clustermap);
1114 }
1115
1116 /* Problem: Partially populated chassis may not have CPUs in some of
1117 * the APIC clusters they have been allocated. Only present CPUs have
1118 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1119 * clusters are allocated sequentially, count zeros only if they are
1120 * bounded by ones.
1121 */
1122 clusters = 0;
1123 zeros = 0;
1124 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1125 if (test_bit(i, clustermap)) {
1126 clusters += 1 + zeros;
1127 zeros = 0;
1128 } else
1129 ++zeros;
1130 }
1131
1132 /*
Vojtech Pavlikf8bf3c62006-06-26 13:58:23 +02001133 * If clusters > 2, then should be multi-chassis.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001134 * May have to revisit this when multi-core + hyperthreaded CPUs come
1135 * out, but AFAIK this will work even for them.
1136 */
1137 return (clusters > 2);
1138}
1139
1140/*
1141 * This interrupt should _never_ happen with our APIC/SMP architecture
1142 */
1143asmlinkage void smp_spurious_interrupt(void)
1144{
1145 unsigned int v;
Andi Kleen95833c82006-01-11 22:44:36 +01001146 exit_idle();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147 irq_enter();
1148 /*
1149 * Check if this really is a spurious interrupt and ACK it
1150 * if it is a vectored one. Just in case...
1151 * Spurious interrupts should not be ACKed.
1152 */
1153 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1154 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1155 ack_APIC_irq();
1156
Joe Korty38e760a2007-10-17 18:04:40 +02001157 add_pda(irq_spurious_count, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158 irq_exit();
1159}
1160
1161/*
1162 * This interrupt should never happen with our APIC/SMP architecture
1163 */
1164
1165asmlinkage void smp_error_interrupt(void)
1166{
1167 unsigned int v, v1;
1168
Andi Kleen95833c82006-01-11 22:44:36 +01001169 exit_idle();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001170 irq_enter();
1171 /* First tickle the hardware, only then report what went on. -- REW */
1172 v = apic_read(APIC_ESR);
1173 apic_write(APIC_ESR, 0);
1174 v1 = apic_read(APIC_ESR);
1175 ack_APIC_irq();
1176 atomic_inc(&irq_err_count);
1177
1178 /* Here is what the APIC error bits mean:
1179 0: Send CS error
1180 1: Receive CS error
1181 2: Send accept error
1182 3: Receive accept error
1183 4: Reserved
1184 5: Send illegal vector
1185 6: Received illegal vector
1186 7: Illegal register address
1187 */
1188 printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02001189 smp_processor_id(), v , v1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001190 irq_exit();
1191}
1192
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02001193int disable_apic;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001194
1195/*
1196 * This initializes the IO-APIC and APIC hardware if this is
1197 * a UP kernel.
1198 */
1199int __init APIC_init_uniprocessor (void)
1200{
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02001201 if (disable_apic) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001202 printk(KERN_INFO "Apic disabled\n");
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02001203 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001204 }
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02001205 if (!cpu_has_apic) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001206 disable_apic = 1;
1207 printk(KERN_INFO "Apic disabled by BIOS\n");
1208 return -1;
1209 }
1210
1211 verify_local_APIC();
1212
Andi Kleen357e11d2005-09-12 18:49:24 +02001213 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
Andi Kleen11a8e772006-01-11 22:46:51 +01001214 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215
1216 setup_local_APIC();
1217
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
Andi Kleen7f11d8a2006-09-26 10:52:29 +02001219 setup_IO_APIC();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220 else
1221 nr_ioapics = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222 setup_boot_APIC_clock();
Andi Kleen75152112005-05-16 21:53:34 -07001223 check_nmi_watchdog();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001224 return 0;
1225}
1226
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02001227static __init int setup_disableapic(char *str)
1228{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001229 disable_apic = 1;
Andi Kleen2c8c0e62006-09-26 10:52:32 +02001230 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1231 return 0;
1232}
1233early_param("disableapic", setup_disableapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001234
Andi Kleen2c8c0e62006-09-26 10:52:32 +02001235/* same as disableapic, for compatibility */
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02001236static __init int setup_nolapic(char *str)
1237{
Andi Kleen2c8c0e62006-09-26 10:52:32 +02001238 return setup_disableapic(str);
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02001239}
Andi Kleen2c8c0e62006-09-26 10:52:32 +02001240early_param("nolapic", setup_nolapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001241
Linus Torvalds2e7c2832007-03-23 11:32:31 -07001242static int __init parse_lapic_timer_c2_ok(char *arg)
1243{
1244 local_apic_timer_c2_ok = 1;
1245 return 0;
1246}
1247early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1248
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02001249static __init int setup_noapictimer(char *str)
1250{
Andi Kleen73dea472006-02-03 21:50:50 +01001251 if (str[0] != ' ' && str[0] != 0)
OGAWA Hirofumi9b410462006-03-31 02:30:33 -08001252 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001253 disable_apic_timer = 1;
OGAWA Hirofumi9b410462006-03-31 02:30:33 -08001254 return 1;
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02001255}
Thomas Gleixner9f75e9b2007-10-12 23:04:23 +02001256__setup("noapictimer", setup_noapictimer);
Andi Kleen73dea472006-02-03 21:50:50 +01001257
Andi Kleen0c3749c2006-02-03 21:51:41 +01001258static __init int setup_apicpmtimer(char *s)
1259{
1260 apic_calibrate_pmtmr = 1;
Andi Kleen7fd67842006-02-16 23:42:07 +01001261 notsc_setup(NULL);
Thomas Gleixnerb8ce3352007-10-12 23:04:07 +02001262 return 0;
Andi Kleen0c3749c2006-02-03 21:51:41 +01001263}
1264__setup("apicpmtimer", setup_apicpmtimer);
1265