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Joerg Roedelb6c02712008-06-26 21:27:53 +02001/*
Joerg Roedel5d0d7152010-10-13 11:13:21 +02002 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
Joerg Roedel63ce3ae2015-02-04 16:12:55 +01003 * Author: Joerg Roedel <jroedel@suse.de>
Joerg Roedelb6c02712008-06-26 21:27:53 +02004 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010020#include <linux/ratelimit.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020021#include <linux/pci.h>
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -040022#include <linux/acpi.h>
Wan Zongshun9a4d3bf52016-04-01 09:06:05 -040023#include <linux/amba/bus.h>
Wan Zongshun0076cd32016-05-10 09:21:01 -040024#include <linux/platform_device.h>
Joerg Roedelcb41ed82011-04-05 11:00:53 +020025#include <linux/pci-ats.h>
Akinobu Mitaa66022c2009-12-15 16:48:28 -080026#include <linux/bitmap.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090027#include <linux/slab.h>
Joerg Roedel7f265082008-12-12 13:50:21 +010028#include <linux/debugfs.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020029#include <linux/scatterlist.h>
FUJITA Tomonori51491362009-01-05 23:47:25 +090030#include <linux/dma-mapping.h>
Christoph Hellwigfec777c2018-03-19 11:38:15 +010031#include <linux/dma-direct.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020032#include <linux/iommu-helper.h>
Joerg Roedelc156e342008-12-02 18:13:27 +010033#include <linux/iommu.h>
Joerg Roedel815b33f2011-04-06 17:26:49 +020034#include <linux/delay.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020035#include <linux/amd-iommu.h>
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010036#include <linux/notifier.h>
37#include <linux/export.h>
Joerg Roedel2b324502012-06-21 16:29:10 +020038#include <linux/irq.h>
39#include <linux/msi.h>
Joerg Roedel3b839a52015-04-01 14:58:47 +020040#include <linux/dma-contiguous.h>
Jiang Liu7c71d302015-04-13 14:11:33 +080041#include <linux/irqdomain.h>
Joerg Roedel5f6bed52015-12-22 13:34:22 +010042#include <linux/percpu.h>
Joerg Roedel307d5852016-07-05 11:54:04 +020043#include <linux/iova.h>
Joerg Roedel2b324502012-06-21 16:29:10 +020044#include <asm/irq_remapping.h>
45#include <asm/io_apic.h>
46#include <asm/apic.h>
47#include <asm/hw_irq.h>
Joerg Roedel17f5b562011-07-06 17:14:44 +020048#include <asm/msidef.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020049#include <asm/proto.h>
FUJITA Tomonori46a7fa22008-07-11 10:23:42 +090050#include <asm/iommu.h>
Joerg Roedel1d9b16d2008-11-27 18:39:15 +010051#include <asm/gart.h>
Joerg Roedel27c2127a2011-05-30 15:56:24 +020052#include <asm/dma.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020053
54#include "amd_iommu_proto.h"
55#include "amd_iommu_types.h"
Joerg Roedel6b474b82012-06-26 16:46:04 +020056#include "irq_remapping.h"
Joerg Roedelb6c02712008-06-26 21:27:53 +020057
Christoph Hellwiga8695722017-05-21 13:26:45 +020058#define AMD_IOMMU_MAPPING_ERROR 0
59
Joerg Roedelb6c02712008-06-26 21:27:53 +020060#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
61
Joerg Roedel815b33f2011-04-06 17:26:49 +020062#define LOOP_TIMEOUT 100000
Joerg Roedel136f78a2008-07-11 17:14:27 +020063
Joerg Roedel307d5852016-07-05 11:54:04 +020064/* IO virtual address start page frame number */
65#define IOVA_START_PFN (1)
66#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
Joerg Roedel307d5852016-07-05 11:54:04 +020067
Joerg Roedel81cd07b2016-07-07 18:01:10 +020068/* Reserved IOVA ranges */
69#define MSI_RANGE_START (0xfee00000)
70#define MSI_RANGE_END (0xfeefffff)
71#define HT_RANGE_START (0xfd00000000ULL)
72#define HT_RANGE_END (0xffffffffffULL)
73
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020074/*
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
78 * that we support.
79 *
Joerg Roedel954e3dd2012-12-02 15:35:37 +010080 * 512GB Pages are not supported due to a hardware bug
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020081 */
Joerg Roedel954e3dd2012-12-02 15:35:37 +010082#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020083
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +010084static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
Sebastian Andrzej Siewior2bc00182018-03-22 16:22:35 +010085static DEFINE_SPINLOCK(pd_bitmap_lock);
Joerg Roedelb6c02712008-06-26 21:27:53 +020086
Joerg Roedel8fa5f802011-06-09 12:24:45 +020087/* List of all available dev_data structures */
Sebastian Andrzej Siewior779da732018-03-22 16:22:34 +010088static LLIST_HEAD(dev_data_list);
Joerg Roedel8fa5f802011-06-09 12:24:45 +020089
Joerg Roedel6efed632012-06-14 15:52:58 +020090LIST_HEAD(ioapic_map);
91LIST_HEAD(hpet_map);
Wan Zongshun2a0cb4e2016-04-01 09:06:00 -040092LIST_HEAD(acpihid_map);
Joerg Roedel6efed632012-06-14 15:52:58 +020093
Joerg Roedel0feae532009-08-26 15:26:30 +020094/*
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
97 */
Joerg Roedelb0119e82017-02-01 13:23:08 +010098const struct iommu_ops amd_iommu_ops;
Joerg Roedel26961ef2008-12-03 17:00:17 +010099
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100100static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
Joerg Roedel52815b72011-11-17 17:24:28 +0100101int amd_iommu_max_glx_val = -1;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100102
Bart Van Assche52997092017-01-20 13:04:01 -0800103static const struct dma_map_ops amd_iommu_dma_ops;
Joerg Roedelac1534a2012-06-21 14:52:40 +0200104
Joerg Roedel431b2a22008-07-11 17:14:22 +0200105/*
106 * general struct to manage commands send to an IOMMU
107 */
Joerg Roedeld6449532008-07-11 17:14:28 +0200108struct iommu_cmd {
Joerg Roedelb6c02712008-06-26 21:27:53 +0200109 u32 data[4];
110};
111
Joerg Roedel05152a02012-06-15 16:53:51 +0200112struct kmem_cache *amd_iommu_irq_cache;
113
Joerg Roedel04bfdd82009-09-02 16:00:23 +0200114static void update_domain(struct protection_domain *domain);
Joerg Roedel7a5a5662015-06-30 08:56:11 +0200115static int protection_domain_init(struct protection_domain *domain);
Joerg Roedelb6809ee52016-02-26 16:48:59 +0100116static void detach_device(struct device *dev);
Joerg Roedel9003d612017-08-10 17:19:13 +0200117static void iova_domain_flush_tlb(struct iova_domain *iovad);
Joerg Roedeld4241a22017-06-02 14:55:56 +0200118
Joerg Roedel007b74b2015-12-21 12:53:54 +0100119/*
Joerg Roedel007b74b2015-12-21 12:53:54 +0100120 * Data container for a dma_ops specific protection domain
121 */
122struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
125
Joerg Roedel307d5852016-07-05 11:54:04 +0200126 /* IOVA RB-Tree */
127 struct iova_domain iovad;
Joerg Roedel007b74b2015-12-21 12:53:54 +0100128};
129
Joerg Roedel81cd07b2016-07-07 18:01:10 +0200130static struct iova_domain reserved_iova_ranges;
131static struct lock_class_key reserved_rbtree_key;
132
Joerg Roedel15898bb2009-11-24 15:39:42 +0100133/****************************************************************************
134 *
135 * Helper functions
136 *
137 ****************************************************************************/
138
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400139static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
Joerg Roedel3f4b87b2015-03-26 13:43:07 +0100141{
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400142 const char *hid, *uid;
143
144 hid = acpi_device_hid(ACPI_COMPANION(dev));
145 uid = acpi_device_uid(ACPI_COMPANION(dev));
146
147 if (!hid || !(*hid))
148 return -ENODEV;
149
150 if (!uid || !(*uid))
151 return strcmp(hid, entry->hid);
152
153 if (!(*entry->uid))
154 return strcmp(hid, entry->hid);
155
156 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
Joerg Roedel3f4b87b2015-03-26 13:43:07 +0100157}
158
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400159static inline u16 get_pci_device_id(struct device *dev)
Joerg Roedele3156042016-04-08 15:12:24 +0200160{
161 struct pci_dev *pdev = to_pci_dev(dev);
162
163 return PCI_DEVID(pdev->bus->number, pdev->devfn);
164}
165
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400166static inline int get_acpihid_device_id(struct device *dev,
167 struct acpihid_map_entry **entry)
168{
169 struct acpihid_map_entry *p;
170
171 list_for_each_entry(p, &acpihid_map, list) {
172 if (!match_hid_uid(dev, p)) {
173 if (entry)
174 *entry = p;
175 return p->devid;
176 }
177 }
178 return -EINVAL;
179}
180
181static inline int get_device_id(struct device *dev)
182{
183 int devid;
184
185 if (dev_is_pci(dev))
186 devid = get_pci_device_id(dev);
187 else
188 devid = get_acpihid_device_id(dev, NULL);
189
190 return devid;
191}
192
Joerg Roedel15898bb2009-11-24 15:39:42 +0100193static struct protection_domain *to_pdomain(struct iommu_domain *dom)
194{
195 return container_of(dom, struct protection_domain, domain);
196}
197
Joerg Roedelb3311b02016-07-08 13:31:31 +0200198static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
199{
200 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
201 return container_of(domain, struct dma_ops_domain, domain);
202}
203
Joerg Roedelf62dda62011-06-09 12:55:35 +0200204static struct iommu_dev_data *alloc_dev_data(u16 devid)
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200205{
206 struct iommu_dev_data *dev_data;
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200207
208 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
209 if (!dev_data)
210 return NULL;
211
Joerg Roedelf62dda62011-06-09 12:55:35 +0200212 dev_data->devid = devid;
Joerg Roedel30bf2df2017-05-15 16:25:03 +0200213 ratelimit_default_init(&dev_data->rs);
214
Sebastian Andrzej Siewior779da732018-03-22 16:22:34 +0100215 llist_add(&dev_data->dev_data_list, &dev_data_list);
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200216 return dev_data;
217}
218
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200219static struct iommu_dev_data *search_dev_data(u16 devid)
220{
221 struct iommu_dev_data *dev_data;
Sebastian Andrzej Siewior779da732018-03-22 16:22:34 +0100222 struct llist_node *node;
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200223
Sebastian Andrzej Siewior779da732018-03-22 16:22:34 +0100224 if (llist_empty(&dev_data_list))
225 return NULL;
226
227 node = dev_data_list.first;
228 llist_for_each_entry(dev_data, node, dev_data_list) {
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200229 if (dev_data->devid == devid)
Sebastian Andrzej Siewior779da732018-03-22 16:22:34 +0100230 return dev_data;
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200231 }
232
Sebastian Andrzej Siewior779da732018-03-22 16:22:34 +0100233 return NULL;
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200234}
235
Joerg Roedele3156042016-04-08 15:12:24 +0200236static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
237{
238 *(u16 *)data = alias;
239 return 0;
240}
241
242static u16 get_alias(struct device *dev)
243{
244 struct pci_dev *pdev = to_pci_dev(dev);
245 u16 devid, ivrs_alias, pci_alias;
246
Joerg Roedel6c0b43d2016-05-09 19:39:17 +0200247 /* The callers make sure that get_device_id() does not fail here */
Joerg Roedele3156042016-04-08 15:12:24 +0200248 devid = get_device_id(dev);
Arindam Nath5ebb1bc2018-09-18 15:40:58 +0530249
250 /* For ACPI HID devices, we simply return the devid as such */
251 if (!dev_is_pci(dev))
252 return devid;
253
Joerg Roedele3156042016-04-08 15:12:24 +0200254 ivrs_alias = amd_iommu_alias_table[devid];
Arindam Nath5ebb1bc2018-09-18 15:40:58 +0530255
Joerg Roedele3156042016-04-08 15:12:24 +0200256 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
257
258 if (ivrs_alias == pci_alias)
259 return ivrs_alias;
260
261 /*
262 * DMA alias showdown
263 *
264 * The IVRS is fairly reliable in telling us about aliases, but it
265 * can't know about every screwy device. If we don't have an IVRS
266 * reported alias, use the PCI reported alias. In that case we may
267 * still need to initialize the rlookup and dev_table entries if the
268 * alias is to a non-existent device.
269 */
270 if (ivrs_alias == devid) {
271 if (!amd_iommu_rlookup_table[pci_alias]) {
272 amd_iommu_rlookup_table[pci_alias] =
273 amd_iommu_rlookup_table[devid];
274 memcpy(amd_iommu_dev_table[pci_alias].data,
275 amd_iommu_dev_table[devid].data,
276 sizeof(amd_iommu_dev_table[pci_alias].data));
277 }
278
279 return pci_alias;
280 }
281
282 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
283 "for device %s[%04x:%04x], kernel reported alias "
284 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
285 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
286 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
287 PCI_FUNC(pci_alias));
288
289 /*
290 * If we don't have a PCI DMA alias and the IVRS alias is on the same
291 * bus, then the IVRS table may know about a quirk that we don't.
292 */
293 if (pci_alias == devid &&
294 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
Linus Torvalds7afd16f2016-05-19 13:10:54 -0700295 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
Joerg Roedele3156042016-04-08 15:12:24 +0200296 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
297 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
298 dev_name(dev));
299 }
300
301 return ivrs_alias;
302}
303
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200304static struct iommu_dev_data *find_dev_data(u16 devid)
305{
306 struct iommu_dev_data *dev_data;
Baoquan Hedf3f7a62017-08-09 16:33:41 +0800307 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200308
309 dev_data = search_dev_data(devid);
310
Baoquan Hedf3f7a62017-08-09 16:33:41 +0800311 if (dev_data == NULL) {
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200312 dev_data = alloc_dev_data(devid);
Sebastian Andrzej Siewior39ffe392018-03-22 16:22:33 +0100313 if (!dev_data)
314 return NULL;
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200315
Baoquan Hedf3f7a62017-08-09 16:33:41 +0800316 if (translation_pre_enabled(iommu))
317 dev_data->defer_attach = true;
318 }
319
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200320 return dev_data;
321}
322
Baoquan Hedaae2d22017-08-09 16:33:43 +0800323struct iommu_dev_data *get_dev_data(struct device *dev)
Joerg Roedel657cbb62009-11-23 15:26:46 +0100324{
325 return dev->archdata.iommu;
326}
Baoquan Hedaae2d22017-08-09 16:33:43 +0800327EXPORT_SYMBOL(get_dev_data);
Joerg Roedel657cbb62009-11-23 15:26:46 +0100328
Wan Zongshunb097d112016-04-01 09:06:04 -0400329/*
330* Find or create an IOMMU group for a acpihid device.
331*/
332static struct iommu_group *acpihid_device_group(struct device *dev)
333{
334 struct acpihid_map_entry *p, *entry = NULL;
Dan Carpenter2d8e1f02016-04-11 10:14:46 +0300335 int devid;
Wan Zongshunb097d112016-04-01 09:06:04 -0400336
337 devid = get_acpihid_device_id(dev, &entry);
338 if (devid < 0)
339 return ERR_PTR(devid);
340
341 list_for_each_entry(p, &acpihid_map, list) {
342 if ((devid == p->devid) && p->group)
343 entry->group = p->group;
344 }
345
346 if (!entry->group)
347 entry->group = generic_device_group(dev);
Robin Murphyf2f101f2016-11-11 17:59:23 +0000348 else
349 iommu_group_ref_get(entry->group);
Wan Zongshunb097d112016-04-01 09:06:04 -0400350
351 return entry->group;
352}
353
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100354static bool pci_iommuv2_capable(struct pci_dev *pdev)
355{
356 static const int caps[] = {
357 PCI_EXT_CAP_ID_ATS,
Joerg Roedel46277b72011-12-07 14:34:02 +0100358 PCI_EXT_CAP_ID_PRI,
359 PCI_EXT_CAP_ID_PASID,
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100360 };
361 int i, pos;
362
Gil Kupfercef74402018-05-10 17:56:02 -0500363 if (pci_ats_disabled())
364 return false;
365
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100366 for (i = 0; i < 3; ++i) {
367 pos = pci_find_ext_capability(pdev, caps[i]);
368 if (pos == 0)
369 return false;
370 }
371
372 return true;
373}
374
Joerg Roedel6a113dd2011-12-01 12:04:58 +0100375static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
376{
377 struct iommu_dev_data *dev_data;
378
379 dev_data = get_dev_data(&pdev->dev);
380
381 return dev_data->errata & (1 << erratum) ? true : false;
382}
383
Joerg Roedel71c70982009-11-24 16:43:06 +0100384/*
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100385 * This function checks if the driver got a valid device from the caller to
386 * avoid dereferencing invalid pointers.
387 */
388static bool check_device(struct device *dev)
389{
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400390 int devid;
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100391
392 if (!dev || !dev->dma_mask)
393 return false;
394
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100395 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200396 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400397 return false;
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100398
399 /* Out of our scope? */
400 if (devid > amd_iommu_last_bdf)
401 return false;
402
403 if (amd_iommu_rlookup_table[devid] == NULL)
404 return false;
405
406 return true;
407}
408
Alex Williamson25b11ce2014-09-19 10:03:13 -0600409static void init_iommu_group(struct device *dev)
Alex Williamson2851db22012-10-08 22:49:41 -0600410{
Alex Williamson2851db22012-10-08 22:49:41 -0600411 struct iommu_group *group;
Alex Williamson2851db22012-10-08 22:49:41 -0600412
Alex Williamson65d53522014-07-03 09:51:30 -0600413 group = iommu_group_get_for_dev(dev);
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200414 if (IS_ERR(group))
415 return;
416
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200417 iommu_group_put(group);
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600418}
419
420static int iommu_init_device(struct device *dev)
421{
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600422 struct iommu_dev_data *dev_data;
Joerg Roedel39ab9552017-02-01 16:56:46 +0100423 struct amd_iommu *iommu;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400424 int devid;
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600425
426 if (dev->archdata.iommu)
427 return 0;
428
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400429 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200430 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400431 return devid;
432
Joerg Roedel39ab9552017-02-01 16:56:46 +0100433 iommu = amd_iommu_rlookup_table[devid];
434
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400435 dev_data = find_dev_data(devid);
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600436 if (!dev_data)
437 return -ENOMEM;
438
Joerg Roedele3156042016-04-08 15:12:24 +0200439 dev_data->alias = get_alias(dev);
440
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400441 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100442 struct amd_iommu *iommu;
443
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400444 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100445 dev_data->iommu_v2 = iommu->is_iommu_v2;
446 }
447
Joerg Roedel657cbb62009-11-23 15:26:46 +0100448 dev->archdata.iommu = dev_data;
449
Joerg Roedele3d10af2017-02-01 17:23:22 +0100450 iommu_device_link(&iommu->iommu, dev);
Alex Williamson066f2e92014-06-12 16:12:37 -0600451
Joerg Roedel657cbb62009-11-23 15:26:46 +0100452 return 0;
453}
454
Joerg Roedel26018872011-06-06 16:50:14 +0200455static void iommu_ignore_device(struct device *dev)
456{
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400457 u16 alias;
458 int devid;
Joerg Roedel26018872011-06-06 16:50:14 +0200459
460 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200461 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400462 return;
463
Joerg Roedele3156042016-04-08 15:12:24 +0200464 alias = get_alias(dev);
Joerg Roedel26018872011-06-06 16:50:14 +0200465
466 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
467 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
468
469 amd_iommu_rlookup_table[devid] = NULL;
470 amd_iommu_rlookup_table[alias] = NULL;
471}
472
Joerg Roedel657cbb62009-11-23 15:26:46 +0100473static void iommu_uninit_device(struct device *dev)
474{
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400475 struct iommu_dev_data *dev_data;
Joerg Roedel39ab9552017-02-01 16:56:46 +0100476 struct amd_iommu *iommu;
477 int devid;
Alex Williamsonc1931092014-07-03 09:51:24 -0600478
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400479 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200480 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400481 return;
482
Joerg Roedel39ab9552017-02-01 16:56:46 +0100483 iommu = amd_iommu_rlookup_table[devid];
484
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400485 dev_data = search_dev_data(devid);
Alex Williamsonc1931092014-07-03 09:51:24 -0600486 if (!dev_data)
487 return;
488
Joerg Roedelb6809ee52016-02-26 16:48:59 +0100489 if (dev_data->domain)
490 detach_device(dev);
491
Joerg Roedele3d10af2017-02-01 17:23:22 +0100492 iommu_device_unlink(&iommu->iommu, dev);
Alex Williamson066f2e92014-06-12 16:12:37 -0600493
Alex Williamson9dcd6132012-05-30 14:19:07 -0600494 iommu_group_remove_device(dev);
495
Joerg Roedelaafd8ba2015-05-28 18:41:39 +0200496 /* Remove dma-ops */
Bart Van Assche56579332017-01-20 13:04:02 -0800497 dev->dma_ops = NULL;
Joerg Roedelaafd8ba2015-05-28 18:41:39 +0200498
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200499 /*
Alex Williamsonc1931092014-07-03 09:51:24 -0600500 * We keep dev_data around for unplugged devices and reuse it when the
501 * device is re-plugged - not doing so would introduce a ton of races.
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200502 */
Joerg Roedel657cbb62009-11-23 15:26:46 +0100503}
Joerg Roedelb7cc9552009-12-10 11:03:39 +0100504
Joerg Roedel431b2a22008-07-11 17:14:22 +0200505/****************************************************************************
506 *
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200507 * Interrupt handling functions
508 *
509 ****************************************************************************/
510
Joerg Roedele3e59872009-09-03 14:02:10 +0200511static void dump_dte_entry(u16 devid)
512{
513 int i;
514
Joerg Roedelee6c2862011-11-09 12:06:03 +0100515 for (i = 0; i < 4; ++i)
516 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
Joerg Roedele3e59872009-09-03 14:02:10 +0200517 amd_iommu_dev_table[devid].data[i]);
518}
519
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200520static void dump_command(unsigned long phys_addr)
521{
Tom Lendacky2543a782017-07-17 16:10:24 -0500522 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200523 int i;
524
525 for (i = 0; i < 4; ++i)
526 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
527}
528
Joerg Roedel30bf2df2017-05-15 16:25:03 +0200529static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
530 u64 address, int flags)
531{
532 struct iommu_dev_data *dev_data = NULL;
533 struct pci_dev *pdev;
534
Sinan Kayad5bf0f42017-12-19 00:37:47 -0500535 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
536 devid & 0xff);
Joerg Roedel30bf2df2017-05-15 16:25:03 +0200537 if (pdev)
538 dev_data = get_dev_data(&pdev->dev);
539
540 if (dev_data && __ratelimit(&dev_data->rs)) {
541 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
542 domain_id, address, flags);
543 } else if (printk_ratelimit()) {
544 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
545 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
546 domain_id, address, flags);
547 }
548
549 if (pdev)
550 pci_dev_put(pdev);
551}
552
Joerg Roedela345b232009-09-03 15:01:43 +0200553static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
Joerg Roedel90008ee2008-09-09 16:41:05 +0200554{
Gary R Hook90ca3852018-03-08 18:34:41 -0600555 struct device *dev = iommu->iommu.dev;
Gary R Hooke7f63ff2018-05-01 14:53:00 -0500556 int type, devid, pasid, flags, tag;
Joerg Roedel3d06fca2012-04-12 14:12:00 +0200557 volatile u32 *event = __evt;
558 int count = 0;
559 u64 address;
560
561retry:
562 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
563 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
Gary R Hookd64c0482018-05-01 14:52:52 -0500564 pasid = PPR_PASID(*(u64 *)&event[0]);
Joerg Roedel3d06fca2012-04-12 14:12:00 +0200565 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
566 address = (u64)(((u64)event[3]) << 32) | event[2];
567
568 if (type == 0) {
569 /* Did we hit the erratum? */
570 if (++count == LOOP_TIMEOUT) {
571 pr_err("AMD-Vi: No event written to event log\n");
572 return;
573 }
574 udelay(1);
575 goto retry;
576 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200577
Joerg Roedel30bf2df2017-05-15 16:25:03 +0200578 if (type == EVENT_TYPE_IO_FAULT) {
Gary R Hookd64c0482018-05-01 14:52:52 -0500579 amd_iommu_report_page_fault(devid, pasid, address, flags);
Joerg Roedel30bf2df2017-05-15 16:25:03 +0200580 return;
581 } else {
Gary R Hook90ca3852018-03-08 18:34:41 -0600582 dev_err(dev, "AMD-Vi: Event logged [");
Joerg Roedel30bf2df2017-05-15 16:25:03 +0200583 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200584
585 switch (type) {
586 case EVENT_TYPE_ILL_DEV:
Gary R Hookd64c0482018-05-01 14:52:52 -0500587 dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
Gary R Hook90ca3852018-03-08 18:34:41 -0600588 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Gary R Hookd64c0482018-05-01 14:52:52 -0500589 pasid, address, flags);
Joerg Roedele3e59872009-09-03 14:02:10 +0200590 dump_dte_entry(devid);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200591 break;
Joerg Roedel90008ee2008-09-09 16:41:05 +0200592 case EVENT_TYPE_DEV_TAB_ERR:
Gary R Hook90ca3852018-03-08 18:34:41 -0600593 dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
594 "address=0x%016llx flags=0x%04x]\n",
595 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
596 address, flags);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200597 break;
598 case EVENT_TYPE_PAGE_TAB_ERR:
Gary R Hookd64c0482018-05-01 14:52:52 -0500599 dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
Gary R Hook90ca3852018-03-08 18:34:41 -0600600 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Gary R Hookd64c0482018-05-01 14:52:52 -0500601 pasid, address, flags);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200602 break;
603 case EVENT_TYPE_ILL_CMD:
Gary R Hook90ca3852018-03-08 18:34:41 -0600604 dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200605 dump_command(address);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200606 break;
607 case EVENT_TYPE_CMD_HARD_ERR:
Gary R Hookd64c0482018-05-01 14:52:52 -0500608 dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n",
609 address, flags);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200610 break;
611 case EVENT_TYPE_IOTLB_INV_TO:
Gary R Hookd64c0482018-05-01 14:52:52 -0500612 dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n",
Gary R Hook90ca3852018-03-08 18:34:41 -0600613 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
614 address);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200615 break;
616 case EVENT_TYPE_INV_DEV_REQ:
Gary R Hookd64c0482018-05-01 14:52:52 -0500617 dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
Gary R Hook90ca3852018-03-08 18:34:41 -0600618 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Gary R Hookd64c0482018-05-01 14:52:52 -0500619 pasid, address, flags);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200620 break;
Gary R Hooke7f63ff2018-05-01 14:53:00 -0500621 case EVENT_TYPE_INV_PPR_REQ:
622 pasid = ((event[0] >> 16) & 0xFFFF)
623 | ((event[1] << 6) & 0xF0000);
624 tag = event[1] & 0x03FF;
625 dev_err(dev, "INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
626 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
627 pasid, address, flags);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200628 break;
629 default:
Gary R Hookd64c0482018-05-01 14:52:52 -0500630 dev_err(dev, "UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
Gary R Hook90ca3852018-03-08 18:34:41 -0600631 event[0], event[1], event[2], event[3]);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200632 }
Joerg Roedel3d06fca2012-04-12 14:12:00 +0200633
634 memset(__evt, 0, 4 * sizeof(u32));
Joerg Roedel90008ee2008-09-09 16:41:05 +0200635}
636
637static void iommu_poll_events(struct amd_iommu *iommu)
638{
639 u32 head, tail;
Joerg Roedel90008ee2008-09-09 16:41:05 +0200640
641 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
642 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
643
644 while (head != tail) {
Joerg Roedela345b232009-09-03 15:01:43 +0200645 iommu_print_event(iommu, iommu->evt_buf + head);
Joerg Roedeldeba4bc2015-10-20 17:33:41 +0200646 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
Joerg Roedel90008ee2008-09-09 16:41:05 +0200647 }
648
649 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200650}
651
Joerg Roedeleee53532012-06-01 15:20:23 +0200652static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100653{
654 struct amd_iommu_fault fault;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100655
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100656 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
657 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
658 return;
659 }
660
661 fault.address = raw[1];
662 fault.pasid = PPR_PASID(raw[0]);
663 fault.device_id = PPR_DEVID(raw[0]);
664 fault.tag = PPR_TAG(raw[0]);
665 fault.flags = PPR_FLAGS(raw[0]);
666
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100667 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
668}
669
670static void iommu_poll_ppr_log(struct amd_iommu *iommu)
671{
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100672 u32 head, tail;
673
674 if (iommu->ppr_log == NULL)
675 return;
676
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100677 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
678 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
679
680 while (head != tail) {
Joerg Roedeleee53532012-06-01 15:20:23 +0200681 volatile u64 *raw;
682 u64 entry[2];
683 int i;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100684
Joerg Roedeleee53532012-06-01 15:20:23 +0200685 raw = (u64 *)(iommu->ppr_log + head);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100686
Joerg Roedeleee53532012-06-01 15:20:23 +0200687 /*
688 * Hardware bug: Interrupt may arrive before the entry is
689 * written to memory. If this happens we need to wait for the
690 * entry to arrive.
691 */
692 for (i = 0; i < LOOP_TIMEOUT; ++i) {
693 if (PPR_REQ_TYPE(raw[0]) != 0)
694 break;
695 udelay(1);
696 }
697
698 /* Avoid memcpy function-call overhead */
699 entry[0] = raw[0];
700 entry[1] = raw[1];
701
702 /*
703 * To detect the hardware bug we need to clear the entry
704 * back to zero.
705 */
706 raw[0] = raw[1] = 0UL;
707
708 /* Update head pointer of hardware ring-buffer */
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100709 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
710 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
Joerg Roedeleee53532012-06-01 15:20:23 +0200711
Joerg Roedeleee53532012-06-01 15:20:23 +0200712 /* Handle PPR entry */
713 iommu_handle_ppr_entry(iommu, entry);
714
Joerg Roedeleee53532012-06-01 15:20:23 +0200715 /* Refresh ring-buffer information */
716 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100717 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
718 }
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100719}
720
Suravee Suthikulpanitbd6fcef2016-08-23 13:52:37 -0500721#ifdef CONFIG_IRQ_REMAP
722static int (*iommu_ga_log_notifier)(u32);
723
724int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
725{
726 iommu_ga_log_notifier = notifier;
727
728 return 0;
729}
730EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
731
732static void iommu_poll_ga_log(struct amd_iommu *iommu)
733{
734 u32 head, tail, cnt = 0;
735
736 if (iommu->ga_log == NULL)
737 return;
738
739 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
740 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
741
742 while (head != tail) {
743 volatile u64 *raw;
744 u64 log_entry;
745
746 raw = (u64 *)(iommu->ga_log + head);
747 cnt++;
748
749 /* Avoid memcpy function-call overhead */
750 log_entry = *raw;
751
752 /* Update head pointer of hardware ring-buffer */
753 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
754 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
755
756 /* Handle GA entry */
757 switch (GA_REQ_TYPE(log_entry)) {
758 case GA_GUEST_NR:
759 if (!iommu_ga_log_notifier)
760 break;
761
762 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
763 __func__, GA_DEVID(log_entry),
764 GA_TAG(log_entry));
765
766 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
767 pr_err("AMD-Vi: GA log notifier failed.\n");
768 break;
769 default:
770 break;
771 }
772 }
773}
774#endif /* CONFIG_IRQ_REMAP */
775
776#define AMD_IOMMU_INT_MASK \
777 (MMIO_STATUS_EVT_INT_MASK | \
778 MMIO_STATUS_PPR_INT_MASK | \
779 MMIO_STATUS_GALOG_INT_MASK)
780
Joerg Roedel72fe00f2011-05-10 10:50:42 +0200781irqreturn_t amd_iommu_int_thread(int irq, void *data)
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200782{
Suravee Suthikulpanit3f398bc2013-04-22 16:32:34 -0500783 struct amd_iommu *iommu = (struct amd_iommu *) data;
784 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200785
Suravee Suthikulpanitbd6fcef2016-08-23 13:52:37 -0500786 while (status & AMD_IOMMU_INT_MASK) {
787 /* Enable EVT and PPR and GA interrupts again */
788 writel(AMD_IOMMU_INT_MASK,
Suravee Suthikulpanit3f398bc2013-04-22 16:32:34 -0500789 iommu->mmio_base + MMIO_STATUS_OFFSET);
790
791 if (status & MMIO_STATUS_EVT_INT_MASK) {
792 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
793 iommu_poll_events(iommu);
794 }
795
796 if (status & MMIO_STATUS_PPR_INT_MASK) {
797 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
798 iommu_poll_ppr_log(iommu);
799 }
800
Suravee Suthikulpanitbd6fcef2016-08-23 13:52:37 -0500801#ifdef CONFIG_IRQ_REMAP
802 if (status & MMIO_STATUS_GALOG_INT_MASK) {
803 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
804 iommu_poll_ga_log(iommu);
805 }
806#endif
807
Suravee Suthikulpanit3f398bc2013-04-22 16:32:34 -0500808 /*
809 * Hardware bug: ERBT1312
810 * When re-enabling interrupt (by writing 1
811 * to clear the bit), the hardware might also try to set
812 * the interrupt bit in the event status register.
813 * In this scenario, the bit will be set, and disable
814 * subsequent interrupts.
815 *
816 * Workaround: The IOMMU driver should read back the
817 * status register and check if the interrupt bits are cleared.
818 * If not, driver will need to go through the interrupt handler
819 * again and re-clear the bits
820 */
821 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100822 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200823 return IRQ_HANDLED;
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200824}
825
Joerg Roedel72fe00f2011-05-10 10:50:42 +0200826irqreturn_t amd_iommu_int_handler(int irq, void *data)
827{
828 return IRQ_WAKE_THREAD;
829}
830
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200831/****************************************************************************
832 *
Joerg Roedel431b2a22008-07-11 17:14:22 +0200833 * IOMMU command queuing functions
834 *
835 ****************************************************************************/
836
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200837static int wait_on_sem(volatile u64 *sem)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200838{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200839 int i = 0;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200840
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200841 while (*sem == 0 && i < LOOP_TIMEOUT) {
842 udelay(1);
843 i += 1;
844 }
845
846 if (i == LOOP_TIMEOUT) {
847 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
848 return -EIO;
849 }
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200850
851 return 0;
852}
853
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200854static void copy_cmd_to_buffer(struct amd_iommu *iommu,
Tom Lendackyd334a562017-06-05 14:52:12 -0500855 struct iommu_cmd *cmd)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200856{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200857 u8 *target;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200858
Tom Lendackyd334a562017-06-05 14:52:12 -0500859 target = iommu->cmd_buf + iommu->cmd_buf_tail;
860
861 iommu->cmd_buf_tail += sizeof(*cmd);
862 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200863
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200864 /* Copy command to buffer */
865 memcpy(target, cmd, sizeof(*cmd));
866
867 /* Tell the IOMMU about it */
Tom Lendackyd334a562017-06-05 14:52:12 -0500868 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200869}
870
Joerg Roedel815b33f2011-04-06 17:26:49 +0200871static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
Joerg Roedelded46732011-04-06 10:53:48 +0200872{
Tom Lendacky2543a782017-07-17 16:10:24 -0500873 u64 paddr = iommu_virt_to_phys((void *)address);
874
Joerg Roedel815b33f2011-04-06 17:26:49 +0200875 WARN_ON(address & 0x7ULL);
876
Joerg Roedelded46732011-04-06 10:53:48 +0200877 memset(cmd, 0, sizeof(*cmd));
Tom Lendacky2543a782017-07-17 16:10:24 -0500878 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
879 cmd->data[1] = upper_32_bits(paddr);
Joerg Roedel815b33f2011-04-06 17:26:49 +0200880 cmd->data[2] = 1;
Joerg Roedelded46732011-04-06 10:53:48 +0200881 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
882}
883
Joerg Roedel94fe79e2011-04-06 11:07:21 +0200884static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
885{
886 memset(cmd, 0, sizeof(*cmd));
887 cmd->data[0] = devid;
888 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
889}
890
Joerg Roedel11b64022011-04-06 11:49:28 +0200891static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
892 size_t size, u16 domid, int pde)
893{
894 u64 pages;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100895 bool s;
Joerg Roedel11b64022011-04-06 11:49:28 +0200896
897 pages = iommu_num_pages(address, size, PAGE_SIZE);
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100898 s = false;
Joerg Roedel11b64022011-04-06 11:49:28 +0200899
900 if (pages > 1) {
901 /*
902 * If we have to flush more than one page, flush all
903 * TLB entries for this domain
904 */
905 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100906 s = true;
Joerg Roedel11b64022011-04-06 11:49:28 +0200907 }
908
909 address &= PAGE_MASK;
910
911 memset(cmd, 0, sizeof(*cmd));
912 cmd->data[1] |= domid;
913 cmd->data[2] = lower_32_bits(address);
914 cmd->data[3] = upper_32_bits(address);
915 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
916 if (s) /* size bit - we flush more than one 4kb page */
917 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
Frank Arnolddf805ab2012-08-27 19:21:04 +0200918 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
Joerg Roedel11b64022011-04-06 11:49:28 +0200919 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
920}
921
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200922static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
923 u64 address, size_t size)
924{
925 u64 pages;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100926 bool s;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200927
928 pages = iommu_num_pages(address, size, PAGE_SIZE);
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100929 s = false;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200930
931 if (pages > 1) {
932 /*
933 * If we have to flush more than one page, flush all
934 * TLB entries for this domain
935 */
936 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100937 s = true;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200938 }
939
940 address &= PAGE_MASK;
941
942 memset(cmd, 0, sizeof(*cmd));
943 cmd->data[0] = devid;
944 cmd->data[0] |= (qdep & 0xff) << 24;
945 cmd->data[1] = devid;
946 cmd->data[2] = lower_32_bits(address);
947 cmd->data[3] = upper_32_bits(address);
948 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
949 if (s)
950 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
951}
952
Joerg Roedel22e266c2011-11-21 15:59:08 +0100953static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
954 u64 address, bool size)
955{
956 memset(cmd, 0, sizeof(*cmd));
957
958 address &= ~(0xfffULL);
959
Suravee Suthikulpanita919a012014-03-05 18:54:18 -0600960 cmd->data[0] = pasid;
Joerg Roedel22e266c2011-11-21 15:59:08 +0100961 cmd->data[1] = domid;
962 cmd->data[2] = lower_32_bits(address);
963 cmd->data[3] = upper_32_bits(address);
964 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
965 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
966 if (size)
967 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
968 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
969}
970
971static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
972 int qdep, u64 address, bool size)
973{
974 memset(cmd, 0, sizeof(*cmd));
975
976 address &= ~(0xfffULL);
977
978 cmd->data[0] = devid;
Jay Cornwalle8d2d822014-02-26 15:49:31 -0600979 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
Joerg Roedel22e266c2011-11-21 15:59:08 +0100980 cmd->data[0] |= (qdep & 0xff) << 24;
981 cmd->data[1] = devid;
Jay Cornwalle8d2d822014-02-26 15:49:31 -0600982 cmd->data[1] |= (pasid & 0xff) << 16;
Joerg Roedel22e266c2011-11-21 15:59:08 +0100983 cmd->data[2] = lower_32_bits(address);
984 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
985 cmd->data[3] = upper_32_bits(address);
986 if (size)
987 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
988 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
989}
990
Joerg Roedelc99afa22011-11-21 18:19:25 +0100991static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
992 int status, int tag, bool gn)
993{
994 memset(cmd, 0, sizeof(*cmd));
995
996 cmd->data[0] = devid;
997 if (gn) {
Suravee Suthikulpanita919a012014-03-05 18:54:18 -0600998 cmd->data[1] = pasid;
Joerg Roedelc99afa22011-11-21 18:19:25 +0100999 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1000 }
1001 cmd->data[3] = tag & 0x1ff;
1002 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1003
1004 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1005}
1006
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001007static void build_inv_all(struct iommu_cmd *cmd)
1008{
1009 memset(cmd, 0, sizeof(*cmd));
1010 CMD_SET_TYPE(cmd, CMD_INV_ALL);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001011}
1012
Joerg Roedel7ef27982012-06-21 16:46:04 +02001013static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1014{
1015 memset(cmd, 0, sizeof(*cmd));
1016 cmd->data[0] = devid;
1017 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1018}
1019
Joerg Roedel431b2a22008-07-11 17:14:22 +02001020/*
Joerg Roedelb6c02712008-06-26 21:27:53 +02001021 * Writes the command to the IOMMUs command buffer and informs the
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001022 * hardware about the new command.
Joerg Roedel431b2a22008-07-11 17:14:22 +02001023 */
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001024static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1025 struct iommu_cmd *cmd,
1026 bool sync)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001027{
Tom Lendacky23e967e2017-06-05 14:52:26 -05001028 unsigned int count = 0;
Tom Lendackyd334a562017-06-05 14:52:12 -05001029 u32 left, next_tail;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001030
Tom Lendackyd334a562017-06-05 14:52:12 -05001031 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001032again:
Tom Lendackyd334a562017-06-05 14:52:12 -05001033 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001034
Huang Rui432abf62016-12-12 07:28:26 -05001035 if (left <= 0x20) {
Tom Lendacky23e967e2017-06-05 14:52:26 -05001036 /* Skip udelay() the first time around */
1037 if (count++) {
1038 if (count == LOOP_TIMEOUT) {
1039 pr_err("AMD-Vi: Command buffer timeout\n");
1040 return -EIO;
1041 }
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001042
Tom Lendacky23e967e2017-06-05 14:52:26 -05001043 udelay(1);
Tom Lendackyd334a562017-06-05 14:52:12 -05001044 }
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001045
Tom Lendacky23e967e2017-06-05 14:52:26 -05001046 /* Update head and recheck remaining space */
1047 iommu->cmd_buf_head = readl(iommu->mmio_base +
1048 MMIO_CMD_HEAD_OFFSET);
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001049
1050 goto again;
Joerg Roedel136f78a2008-07-11 17:14:27 +02001051 }
1052
Tom Lendackyd334a562017-06-05 14:52:12 -05001053 copy_cmd_to_buffer(iommu, cmd);
Joerg Roedel519c31b2008-08-14 19:55:15 +02001054
Tom Lendacky23e967e2017-06-05 14:52:26 -05001055 /* Do we need to make sure all commands are processed? */
Joerg Roedelf1ca1512011-09-02 14:10:32 +02001056 iommu->need_sync = sync;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001057
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001058 return 0;
1059}
1060
1061static int iommu_queue_command_sync(struct amd_iommu *iommu,
1062 struct iommu_cmd *cmd,
1063 bool sync)
1064{
1065 unsigned long flags;
1066 int ret;
1067
Scott Wood27790392018-01-21 03:28:54 -06001068 raw_spin_lock_irqsave(&iommu->lock, flags);
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001069 ret = __iommu_queue_command_sync(iommu, cmd, sync);
Scott Wood27790392018-01-21 03:28:54 -06001070 raw_spin_unlock_irqrestore(&iommu->lock, flags);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001071
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001072 return ret;
Joerg Roedel8d201962008-12-02 20:34:41 +01001073}
1074
Joerg Roedelf1ca1512011-09-02 14:10:32 +02001075static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1076{
1077 return iommu_queue_command_sync(iommu, cmd, true);
1078}
1079
Joerg Roedel8d201962008-12-02 20:34:41 +01001080/*
1081 * This function queues a completion wait command into the command
1082 * buffer of an IOMMU
1083 */
Joerg Roedel8d201962008-12-02 20:34:41 +01001084static int iommu_completion_wait(struct amd_iommu *iommu)
1085{
Joerg Roedel815b33f2011-04-06 17:26:49 +02001086 struct iommu_cmd cmd;
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001087 unsigned long flags;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001088 int ret;
Joerg Roedel8d201962008-12-02 20:34:41 +01001089
1090 if (!iommu->need_sync)
Joerg Roedel815b33f2011-04-06 17:26:49 +02001091 return 0;
Joerg Roedel8d201962008-12-02 20:34:41 +01001092
Joerg Roedel8d201962008-12-02 20:34:41 +01001093
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001094 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1095
Scott Wood27790392018-01-21 03:28:54 -06001096 raw_spin_lock_irqsave(&iommu->lock, flags);
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001097
1098 iommu->cmd_sem = 0;
1099
1100 ret = __iommu_queue_command_sync(iommu, &cmd, false);
Joerg Roedel8d201962008-12-02 20:34:41 +01001101 if (ret)
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001102 goto out_unlock;
Joerg Roedel8d201962008-12-02 20:34:41 +01001103
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001104 ret = wait_on_sem(&iommu->cmd_sem);
1105
1106out_unlock:
Scott Wood27790392018-01-21 03:28:54 -06001107 raw_spin_unlock_irqrestore(&iommu->lock, flags);
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001108
1109 return ret;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001110}
1111
Joerg Roedeld8c13082011-04-06 18:51:26 +02001112static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001113{
1114 struct iommu_cmd cmd;
1115
Joerg Roedeld8c13082011-04-06 18:51:26 +02001116 build_inv_dte(&cmd, devid);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001117
Joerg Roedeld8c13082011-04-06 18:51:26 +02001118 return iommu_queue_command(iommu, &cmd);
1119}
1120
Joerg Roedel0688a092017-08-23 15:50:03 +02001121static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001122{
1123 u32 devid;
1124
1125 for (devid = 0; devid <= 0xffff; ++devid)
1126 iommu_flush_dte(iommu, devid);
1127
1128 iommu_completion_wait(iommu);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001129}
1130
1131/*
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001132 * This function uses heavy locking and may disable irqs for some time. But
1133 * this is no issue because it is only called during resume.
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001134 */
Joerg Roedel0688a092017-08-23 15:50:03 +02001135static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001136{
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001137 u32 dom_id;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001138
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001139 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1140 struct iommu_cmd cmd;
1141 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1142 dom_id, 1);
1143 iommu_queue_command(iommu, &cmd);
1144 }
Joerg Roedel431b2a22008-07-11 17:14:22 +02001145
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001146 iommu_completion_wait(iommu);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001147}
1148
Joerg Roedel0688a092017-08-23 15:50:03 +02001149static void amd_iommu_flush_all(struct amd_iommu *iommu)
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001150{
1151 struct iommu_cmd cmd;
1152
1153 build_inv_all(&cmd);
1154
1155 iommu_queue_command(iommu, &cmd);
1156 iommu_completion_wait(iommu);
1157}
1158
Joerg Roedel7ef27982012-06-21 16:46:04 +02001159static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1160{
1161 struct iommu_cmd cmd;
1162
1163 build_inv_irt(&cmd, devid);
1164
1165 iommu_queue_command(iommu, &cmd);
1166}
1167
Joerg Roedel0688a092017-08-23 15:50:03 +02001168static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
Joerg Roedel7ef27982012-06-21 16:46:04 +02001169{
1170 u32 devid;
1171
1172 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1173 iommu_flush_irt(iommu, devid);
1174
1175 iommu_completion_wait(iommu);
1176}
1177
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001178void iommu_flush_all_caches(struct amd_iommu *iommu)
1179{
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001180 if (iommu_feature(iommu, FEATURE_IA)) {
Joerg Roedel0688a092017-08-23 15:50:03 +02001181 amd_iommu_flush_all(iommu);
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001182 } else {
Joerg Roedel0688a092017-08-23 15:50:03 +02001183 amd_iommu_flush_dte_all(iommu);
1184 amd_iommu_flush_irt_all(iommu);
1185 amd_iommu_flush_tlb_all(iommu);
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001186 }
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001187}
1188
Joerg Roedel431b2a22008-07-11 17:14:22 +02001189/*
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001190 * Command send function for flushing on-device TLB
1191 */
Joerg Roedel6c542042011-06-09 17:07:31 +02001192static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1193 u64 address, size_t size)
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001194{
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001195 struct amd_iommu *iommu;
1196 struct iommu_cmd cmd;
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001197 int qdep;
1198
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001199 qdep = dev_data->ats.qdep;
1200 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001201
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001202 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001203
1204 return iommu_queue_command(iommu, &cmd);
1205}
1206
1207/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001208 * Command send function for invalidating a device table entry
1209 */
Joerg Roedel6c542042011-06-09 17:07:31 +02001210static int device_flush_dte(struct iommu_dev_data *dev_data)
Joerg Roedel3fa43652009-11-26 15:04:38 +01001211{
1212 struct amd_iommu *iommu;
Joerg Roedele25bfb52015-10-20 17:33:38 +02001213 u16 alias;
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001214 int ret;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001215
Joerg Roedel6c542042011-06-09 17:07:31 +02001216 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedele3156042016-04-08 15:12:24 +02001217 alias = dev_data->alias;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001218
Joerg Roedelf62dda62011-06-09 12:55:35 +02001219 ret = iommu_flush_dte(iommu, dev_data->devid);
Joerg Roedele25bfb52015-10-20 17:33:38 +02001220 if (!ret && alias != dev_data->devid)
1221 ret = iommu_flush_dte(iommu, alias);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001222 if (ret)
1223 return ret;
1224
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001225 if (dev_data->ats.enabled)
Joerg Roedel6c542042011-06-09 17:07:31 +02001226 ret = device_flush_iotlb(dev_data, 0, ~0UL);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001227
1228 return ret;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001229}
1230
Joerg Roedel431b2a22008-07-11 17:14:22 +02001231/*
1232 * TLB invalidation function which is called from the mapping functions.
1233 * It invalidates a single PTE if the range to flush is within a single
1234 * page. Otherwise it flushes the whole TLB of the IOMMU.
1235 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001236static void __domain_flush_pages(struct protection_domain *domain,
1237 u64 address, size_t size, int pde)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001238{
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001239 struct iommu_dev_data *dev_data;
Joerg Roedel11b64022011-04-06 11:49:28 +02001240 struct iommu_cmd cmd;
1241 int ret = 0, i;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001242
Joerg Roedel11b64022011-04-06 11:49:28 +02001243 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
Joerg Roedel999ba412008-07-03 19:35:08 +02001244
Suravee Suthikulpanit6b9376e2017-02-24 02:48:17 -06001245 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001246 if (!domain->dev_iommu[i])
1247 continue;
1248
1249 /*
1250 * Devices of this domain are behind this IOMMU
1251 * We need a TLB flush
1252 */
Joerg Roedel11b64022011-04-06 11:49:28 +02001253 ret |= iommu_queue_command(amd_iommus[i], &cmd);
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001254 }
1255
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001256 list_for_each_entry(dev_data, &domain->dev_list, list) {
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001257
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001258 if (!dev_data->ats.enabled)
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001259 continue;
1260
Joerg Roedel6c542042011-06-09 17:07:31 +02001261 ret |= device_flush_iotlb(dev_data, address, size);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001262 }
1263
Joerg Roedel11b64022011-04-06 11:49:28 +02001264 WARN_ON(ret);
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001265}
1266
Joerg Roedel17b124b2011-04-06 18:01:35 +02001267static void domain_flush_pages(struct protection_domain *domain,
1268 u64 address, size_t size)
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001269{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001270 __domain_flush_pages(domain, address, size, 0);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001271}
Joerg Roedelb6c02712008-06-26 21:27:53 +02001272
Joerg Roedel1c655772008-09-04 18:40:05 +02001273/* Flush the whole IO/TLB for a given protection domain */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001274static void domain_flush_tlb(struct protection_domain *domain)
Joerg Roedel1c655772008-09-04 18:40:05 +02001275{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001276 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
Joerg Roedel1c655772008-09-04 18:40:05 +02001277}
1278
Chris Wright42a49f92009-06-15 15:42:00 +02001279/* Flush the whole IO/TLB for a given protection domain - including PDE */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001280static void domain_flush_tlb_pde(struct protection_domain *domain)
Chris Wright42a49f92009-06-15 15:42:00 +02001281{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001282 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1283}
1284
1285static void domain_flush_complete(struct protection_domain *domain)
Joerg Roedelb6c02712008-06-26 21:27:53 +02001286{
1287 int i;
1288
Suravee Suthikulpanit6b9376e2017-02-24 02:48:17 -06001289 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
Joerg Roedelf1eae7c2016-07-06 12:50:35 +02001290 if (domain && !domain->dev_iommu[i])
Joerg Roedelb6c02712008-06-26 21:27:53 +02001291 continue;
1292
1293 /*
1294 * Devices of this domain are behind this IOMMU
1295 * We need to wait for completion of all commands.
1296 */
1297 iommu_completion_wait(amd_iommus[i]);
1298 }
1299}
1300
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001301
Joerg Roedel43f49602008-12-02 21:01:12 +01001302/*
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001303 * This function flushes the DTEs for all devices in domain
Joerg Roedel43f49602008-12-02 21:01:12 +01001304 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001305static void domain_flush_devices(struct protection_domain *domain)
Joerg Roedelbfd1be12009-05-05 15:33:57 +02001306{
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001307 struct iommu_dev_data *dev_data;
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001308
1309 list_for_each_entry(dev_data, &domain->dev_list, list)
Joerg Roedel6c542042011-06-09 17:07:31 +02001310 device_flush_dte(dev_data);
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001311}
1312
Joerg Roedel431b2a22008-07-11 17:14:22 +02001313/****************************************************************************
1314 *
1315 * The functions below are used the create the page table mappings for
1316 * unity mapped regions.
1317 *
1318 ****************************************************************************/
1319
1320/*
Joerg Roedel308973d2009-11-24 17:43:32 +01001321 * This function is used to add another level to an IO page table. Adding
1322 * another level increases the size of the address space by 9 bits to a size up
1323 * to 64 bits.
1324 */
1325static bool increase_address_space(struct protection_domain *domain,
1326 gfp_t gfp)
1327{
1328 u64 *pte;
1329
1330 if (domain->mode == PAGE_MODE_6_LEVEL)
1331 /* address space already 64 bit large */
1332 return false;
1333
1334 pte = (void *)get_zeroed_page(gfp);
1335 if (!pte)
1336 return false;
1337
1338 *pte = PM_LEVEL_PDE(domain->mode,
Tom Lendacky2543a782017-07-17 16:10:24 -05001339 iommu_virt_to_phys(domain->pt_root));
Joerg Roedel308973d2009-11-24 17:43:32 +01001340 domain->pt_root = pte;
1341 domain->mode += 1;
1342 domain->updated = true;
1343
1344 return true;
1345}
1346
1347static u64 *alloc_pte(struct protection_domain *domain,
1348 unsigned long address,
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001349 unsigned long page_size,
Joerg Roedel308973d2009-11-24 17:43:32 +01001350 u64 **pte_page,
1351 gfp_t gfp)
1352{
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001353 int level, end_lvl;
Joerg Roedel308973d2009-11-24 17:43:32 +01001354 u64 *pte, *page;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001355
1356 BUG_ON(!is_power_of_2(page_size));
Joerg Roedel308973d2009-11-24 17:43:32 +01001357
1358 while (address > PM_LEVEL_SIZE(domain->mode))
1359 increase_address_space(domain, gfp);
1360
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001361 level = domain->mode - 1;
1362 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1363 address = PAGE_SIZE_ALIGN(address, page_size);
1364 end_lvl = PAGE_SIZE_LEVEL(page_size);
Joerg Roedel308973d2009-11-24 17:43:32 +01001365
1366 while (level > end_lvl) {
Joerg Roedel7bfa5bd2015-12-21 19:07:50 +01001367 u64 __pte, __npte;
1368
1369 __pte = *pte;
1370
1371 if (!IOMMU_PTE_PRESENT(__pte)) {
Joerg Roedel308973d2009-11-24 17:43:32 +01001372 page = (u64 *)get_zeroed_page(gfp);
1373 if (!page)
1374 return NULL;
Joerg Roedel7bfa5bd2015-12-21 19:07:50 +01001375
Tom Lendacky2543a782017-07-17 16:10:24 -05001376 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
Joerg Roedel7bfa5bd2015-12-21 19:07:50 +01001377
Baoquan He134414f2016-09-15 16:50:50 +08001378 /* pte could have been changed somewhere. */
1379 if (cmpxchg64(pte, __pte, __npte) != __pte) {
Joerg Roedel7bfa5bd2015-12-21 19:07:50 +01001380 free_page((unsigned long)page);
1381 continue;
1382 }
Joerg Roedel308973d2009-11-24 17:43:32 +01001383 }
1384
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001385 /* No level skipping support yet */
1386 if (PM_PTE_LEVEL(*pte) != level)
1387 return NULL;
1388
Joerg Roedel308973d2009-11-24 17:43:32 +01001389 level -= 1;
1390
1391 pte = IOMMU_PTE_PAGE(*pte);
1392
1393 if (pte_page && level == end_lvl)
1394 *pte_page = pte;
1395
1396 pte = &pte[PM_LEVEL_INDEX(level, address)];
1397 }
1398
1399 return pte;
1400}
1401
1402/*
1403 * This function checks if there is a PTE for a given dma address. If
1404 * there is one, it returns the pointer to it.
1405 */
Joerg Roedel3039ca12015-04-01 14:58:48 +02001406static u64 *fetch_pte(struct protection_domain *domain,
1407 unsigned long address,
1408 unsigned long *page_size)
Joerg Roedel308973d2009-11-24 17:43:32 +01001409{
1410 int level;
1411 u64 *pte;
1412
yzhai003@ucr.edu46746862018-06-01 11:30:14 -07001413 *page_size = 0;
1414
Joerg Roedel24cd7722010-01-19 17:27:39 +01001415 if (address > PM_LEVEL_SIZE(domain->mode))
1416 return NULL;
Joerg Roedel308973d2009-11-24 17:43:32 +01001417
Joerg Roedel3039ca12015-04-01 14:58:48 +02001418 level = domain->mode - 1;
1419 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1420 *page_size = PTE_LEVEL_PAGE_SIZE(level);
Joerg Roedel24cd7722010-01-19 17:27:39 +01001421
1422 while (level > 0) {
1423
1424 /* Not Present */
Joerg Roedel308973d2009-11-24 17:43:32 +01001425 if (!IOMMU_PTE_PRESENT(*pte))
1426 return NULL;
1427
Joerg Roedel24cd7722010-01-19 17:27:39 +01001428 /* Large PTE */
Joerg Roedel3039ca12015-04-01 14:58:48 +02001429 if (PM_PTE_LEVEL(*pte) == 7 ||
1430 PM_PTE_LEVEL(*pte) == 0)
1431 break;
Joerg Roedel24cd7722010-01-19 17:27:39 +01001432
1433 /* No level skipping support yet */
1434 if (PM_PTE_LEVEL(*pte) != level)
1435 return NULL;
1436
Joerg Roedel308973d2009-11-24 17:43:32 +01001437 level -= 1;
1438
Joerg Roedel24cd7722010-01-19 17:27:39 +01001439 /* Walk to the next level */
Joerg Roedel3039ca12015-04-01 14:58:48 +02001440 pte = IOMMU_PTE_PAGE(*pte);
1441 pte = &pte[PM_LEVEL_INDEX(level, address)];
1442 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1443 }
1444
1445 if (PM_PTE_LEVEL(*pte) == 0x07) {
1446 unsigned long pte_mask;
1447
1448 /*
1449 * If we have a series of large PTEs, make
1450 * sure to return a pointer to the first one.
1451 */
1452 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1453 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1454 pte = (u64 *)(((unsigned long)pte) & pte_mask);
Joerg Roedel308973d2009-11-24 17:43:32 +01001455 }
1456
1457 return pte;
1458}
1459
1460/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001461 * Generic mapping functions. It maps a physical address into a DMA
1462 * address space. It allocates the page table pages if necessary.
1463 * In the future it can be extended to a generic mapping function
1464 * supporting all features of AMD IOMMU page tables like level skipping
1465 * and full 64 bit address spaces.
1466 */
Joerg Roedel38e817f2008-12-02 17:27:52 +01001467static int iommu_map_page(struct protection_domain *dom,
1468 unsigned long bus_addr,
1469 unsigned long phys_addr,
Joerg Roedelb911b892016-07-05 14:29:11 +02001470 unsigned long page_size,
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001471 int prot,
Joerg Roedelb911b892016-07-05 14:29:11 +02001472 gfp_t gfp)
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001473{
Joerg Roedel8bda3092009-05-12 12:02:46 +02001474 u64 __pte, *pte;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001475 int i, count;
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001476
Joerg Roedeld4b03662015-04-01 14:58:52 +02001477 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1478 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1479
Joerg Roedelbad1cac2009-09-02 16:52:23 +02001480 if (!(prot & IOMMU_PROT_MASK))
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001481 return -EINVAL;
1482
Joerg Roedeld4b03662015-04-01 14:58:52 +02001483 count = PAGE_SIZE_PTE_COUNT(page_size);
Joerg Roedelb911b892016-07-05 14:29:11 +02001484 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001485
Maurizio Lombardi63eaa752014-09-11 12:28:03 +02001486 if (!pte)
1487 return -ENOMEM;
1488
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001489 for (i = 0; i < count; ++i)
1490 if (IOMMU_PTE_PRESENT(pte[i]))
1491 return -EBUSY;
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001492
Joerg Roedeld4b03662015-04-01 14:58:52 +02001493 if (count > 1) {
Tom Lendacky2543a782017-07-17 16:10:24 -05001494 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
Baoquan He07a80a62017-08-09 16:33:36 +08001495 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001496 } else
Linus Torvalds4dfc2782017-09-09 15:03:24 -07001497 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001498
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001499 if (prot & IOMMU_PROT_IR)
1500 __pte |= IOMMU_PTE_IR;
1501 if (prot & IOMMU_PROT_IW)
1502 __pte |= IOMMU_PTE_IW;
1503
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001504 for (i = 0; i < count; ++i)
1505 pte[i] = __pte;
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001506
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001507 update_domain(dom);
1508
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001509 return 0;
1510}
1511
Joerg Roedel24cd7722010-01-19 17:27:39 +01001512static unsigned long iommu_unmap_page(struct protection_domain *dom,
1513 unsigned long bus_addr,
1514 unsigned long page_size)
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001515{
Joerg Roedel71b390e2015-04-01 14:58:49 +02001516 unsigned long long unmapped;
1517 unsigned long unmap_size;
Joerg Roedel24cd7722010-01-19 17:27:39 +01001518 u64 *pte;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001519
Joerg Roedel24cd7722010-01-19 17:27:39 +01001520 BUG_ON(!is_power_of_2(page_size));
1521
1522 unmapped = 0;
1523
1524 while (unmapped < page_size) {
1525
Joerg Roedel71b390e2015-04-01 14:58:49 +02001526 pte = fetch_pte(dom, bus_addr, &unmap_size);
Joerg Roedel24cd7722010-01-19 17:27:39 +01001527
Joerg Roedel71b390e2015-04-01 14:58:49 +02001528 if (pte) {
1529 int i, count;
Joerg Roedel24cd7722010-01-19 17:27:39 +01001530
Joerg Roedel71b390e2015-04-01 14:58:49 +02001531 count = PAGE_SIZE_PTE_COUNT(unmap_size);
Joerg Roedel24cd7722010-01-19 17:27:39 +01001532 for (i = 0; i < count; i++)
1533 pte[i] = 0ULL;
1534 }
1535
1536 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1537 unmapped += unmap_size;
1538 }
1539
Alex Williamson60d0ca32013-06-21 14:33:19 -06001540 BUG_ON(unmapped && !is_power_of_2(unmapped));
Joerg Roedel24cd7722010-01-19 17:27:39 +01001541
1542 return unmapped;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001543}
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001544
Joerg Roedel431b2a22008-07-11 17:14:22 +02001545/****************************************************************************
1546 *
1547 * The next functions belong to the address allocator for the dma_ops
Joerg Roedel2d4c5152016-07-05 16:21:32 +02001548 * interface functions.
Joerg Roedel431b2a22008-07-11 17:14:22 +02001549 *
1550 ****************************************************************************/
Joerg Roedeld3086442008-06-26 21:27:57 +02001551
Joerg Roedel9cabe892009-05-18 16:38:55 +02001552
Joerg Roedel256e4622016-07-05 14:23:01 +02001553static unsigned long dma_ops_alloc_iova(struct device *dev,
1554 struct dma_ops_domain *dma_dom,
1555 unsigned int pages, u64 dma_mask)
Joerg Roedela0f51442015-12-21 16:20:09 +01001556{
Joerg Roedel256e4622016-07-05 14:23:01 +02001557 unsigned long pfn = 0;
Joerg Roedela0f51442015-12-21 16:20:09 +01001558
Joerg Roedel256e4622016-07-05 14:23:01 +02001559 pages = __roundup_pow_of_two(pages);
Joerg Roedela0f51442015-12-21 16:20:09 +01001560
Joerg Roedel256e4622016-07-05 14:23:01 +02001561 if (dma_mask > DMA_BIT_MASK(32))
1562 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
Tomasz Nowicki538d5b32017-09-20 10:52:02 +02001563 IOVA_PFN(DMA_BIT_MASK(32)), false);
Joerg Roedel7b5e25b842015-12-22 13:38:12 +01001564
Joerg Roedel256e4622016-07-05 14:23:01 +02001565 if (!pfn)
Tomasz Nowicki538d5b32017-09-20 10:52:02 +02001566 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1567 IOVA_PFN(dma_mask), true);
Joerg Roedel60e6a7c2015-12-21 16:53:17 +01001568
Joerg Roedel256e4622016-07-05 14:23:01 +02001569 return (pfn << PAGE_SHIFT);
Joerg Roedela0f51442015-12-21 16:20:09 +01001570}
1571
Joerg Roedel256e4622016-07-05 14:23:01 +02001572static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1573 unsigned long address,
1574 unsigned int pages)
Joerg Roedel384de722009-05-15 12:30:05 +02001575{
Joerg Roedel256e4622016-07-05 14:23:01 +02001576 pages = __roundup_pow_of_two(pages);
1577 address >>= PAGE_SHIFT;
Joerg Roedel5f6bed52015-12-22 13:34:22 +01001578
Joerg Roedel256e4622016-07-05 14:23:01 +02001579 free_iova_fast(&dma_dom->iovad, address, pages);
Joerg Roedeld3086442008-06-26 21:27:57 +02001580}
1581
Joerg Roedel431b2a22008-07-11 17:14:22 +02001582/****************************************************************************
1583 *
1584 * The next functions belong to the domain allocation. A domain is
1585 * allocated for every IOMMU as the default domain. If device isolation
1586 * is enabled, every device get its own domain. The most important thing
1587 * about domains is the page table mapping the DMA address space they
1588 * contain.
1589 *
1590 ****************************************************************************/
1591
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001592/*
1593 * This function adds a protection domain to the global protection domain list
1594 */
1595static void add_domain_to_list(struct protection_domain *domain)
1596{
1597 unsigned long flags;
1598
1599 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1600 list_add(&domain->list, &amd_iommu_pd_list);
1601 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1602}
1603
1604/*
1605 * This function removes a protection domain to the global
1606 * protection domain list
1607 */
1608static void del_domain_from_list(struct protection_domain *domain)
1609{
1610 unsigned long flags;
1611
1612 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1613 list_del(&domain->list);
1614 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1615}
1616
Joerg Roedelec487d12008-06-26 21:27:58 +02001617static u16 domain_id_alloc(void)
1618{
Joerg Roedelec487d12008-06-26 21:27:58 +02001619 int id;
1620
Sebastian Andrzej Siewior2bc00182018-03-22 16:22:35 +01001621 spin_lock(&pd_bitmap_lock);
Joerg Roedelec487d12008-06-26 21:27:58 +02001622 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1623 BUG_ON(id == 0);
1624 if (id > 0 && id < MAX_DOMAIN_ID)
1625 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1626 else
1627 id = 0;
Sebastian Andrzej Siewior2bc00182018-03-22 16:22:35 +01001628 spin_unlock(&pd_bitmap_lock);
Joerg Roedelec487d12008-06-26 21:27:58 +02001629
1630 return id;
1631}
1632
Joerg Roedela2acfb72008-12-02 18:28:53 +01001633static void domain_id_free(int id)
1634{
Sebastian Andrzej Siewior2bc00182018-03-22 16:22:35 +01001635 spin_lock(&pd_bitmap_lock);
Joerg Roedela2acfb72008-12-02 18:28:53 +01001636 if (id > 0 && id < MAX_DOMAIN_ID)
1637 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
Sebastian Andrzej Siewior2bc00182018-03-22 16:22:35 +01001638 spin_unlock(&pd_bitmap_lock);
Joerg Roedela2acfb72008-12-02 18:28:53 +01001639}
Joerg Roedela2acfb72008-12-02 18:28:53 +01001640
Joerg Roedel5c34c402013-06-20 20:22:58 +02001641#define DEFINE_FREE_PT_FN(LVL, FN) \
1642static void free_pt_##LVL (unsigned long __pt) \
1643{ \
1644 unsigned long p; \
1645 u64 *pt; \
1646 int i; \
1647 \
1648 pt = (u64 *)__pt; \
1649 \
1650 for (i = 0; i < 512; ++i) { \
Joerg Roedel0b3fff542015-06-18 10:48:34 +02001651 /* PTE present? */ \
Joerg Roedel5c34c402013-06-20 20:22:58 +02001652 if (!IOMMU_PTE_PRESENT(pt[i])) \
1653 continue; \
1654 \
Joerg Roedel0b3fff542015-06-18 10:48:34 +02001655 /* Large PTE? */ \
1656 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1657 PM_PTE_LEVEL(pt[i]) == 7) \
1658 continue; \
1659 \
Joerg Roedel5c34c402013-06-20 20:22:58 +02001660 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1661 FN(p); \
1662 } \
1663 free_page((unsigned long)pt); \
1664}
1665
1666DEFINE_FREE_PT_FN(l2, free_page)
1667DEFINE_FREE_PT_FN(l3, free_pt_l2)
1668DEFINE_FREE_PT_FN(l4, free_pt_l3)
1669DEFINE_FREE_PT_FN(l5, free_pt_l4)
1670DEFINE_FREE_PT_FN(l6, free_pt_l5)
1671
Joerg Roedel86db2e52008-12-02 18:20:21 +01001672static void free_pagetable(struct protection_domain *domain)
Joerg Roedelec487d12008-06-26 21:27:58 +02001673{
Joerg Roedel5c34c402013-06-20 20:22:58 +02001674 unsigned long root = (unsigned long)domain->pt_root;
Joerg Roedelec487d12008-06-26 21:27:58 +02001675
Joerg Roedel5c34c402013-06-20 20:22:58 +02001676 switch (domain->mode) {
1677 case PAGE_MODE_NONE:
1678 break;
1679 case PAGE_MODE_1_LEVEL:
1680 free_page(root);
1681 break;
1682 case PAGE_MODE_2_LEVEL:
1683 free_pt_l2(root);
1684 break;
1685 case PAGE_MODE_3_LEVEL:
1686 free_pt_l3(root);
1687 break;
1688 case PAGE_MODE_4_LEVEL:
1689 free_pt_l4(root);
1690 break;
1691 case PAGE_MODE_5_LEVEL:
1692 free_pt_l5(root);
1693 break;
1694 case PAGE_MODE_6_LEVEL:
1695 free_pt_l6(root);
1696 break;
1697 default:
1698 BUG();
Joerg Roedelec487d12008-06-26 21:27:58 +02001699 }
Joerg Roedelec487d12008-06-26 21:27:58 +02001700}
1701
Joerg Roedelb16137b2011-11-21 16:50:23 +01001702static void free_gcr3_tbl_level1(u64 *tbl)
1703{
1704 u64 *ptr;
1705 int i;
1706
1707 for (i = 0; i < 512; ++i) {
1708 if (!(tbl[i] & GCR3_VALID))
1709 continue;
1710
Tom Lendacky2543a782017-07-17 16:10:24 -05001711 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
Joerg Roedelb16137b2011-11-21 16:50:23 +01001712
1713 free_page((unsigned long)ptr);
1714 }
1715}
1716
1717static void free_gcr3_tbl_level2(u64 *tbl)
1718{
1719 u64 *ptr;
1720 int i;
1721
1722 for (i = 0; i < 512; ++i) {
1723 if (!(tbl[i] & GCR3_VALID))
1724 continue;
1725
Tom Lendacky2543a782017-07-17 16:10:24 -05001726 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
Joerg Roedelb16137b2011-11-21 16:50:23 +01001727
1728 free_gcr3_tbl_level1(ptr);
1729 }
1730}
1731
Joerg Roedel52815b72011-11-17 17:24:28 +01001732static void free_gcr3_table(struct protection_domain *domain)
1733{
Joerg Roedelb16137b2011-11-21 16:50:23 +01001734 if (domain->glx == 2)
1735 free_gcr3_tbl_level2(domain->gcr3_tbl);
1736 else if (domain->glx == 1)
1737 free_gcr3_tbl_level1(domain->gcr3_tbl);
Joerg Roedel23d3a982015-08-13 11:15:13 +02001738 else
1739 BUG_ON(domain->glx != 0);
Joerg Roedelb16137b2011-11-21 16:50:23 +01001740
Joerg Roedel52815b72011-11-17 17:24:28 +01001741 free_page((unsigned long)domain->gcr3_tbl);
1742}
1743
Joerg Roedelfca6af62017-06-02 18:13:37 +02001744static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1745{
Joerg Roedelfca6af62017-06-02 18:13:37 +02001746 domain_flush_tlb(&dom->domain);
1747 domain_flush_complete(&dom->domain);
Joerg Roedelfca6af62017-06-02 18:13:37 +02001748}
1749
Joerg Roedel9003d612017-08-10 17:19:13 +02001750static void iova_domain_flush_tlb(struct iova_domain *iovad)
Joerg Roedelfd621902017-06-02 15:37:26 +02001751{
Joerg Roedel9003d612017-08-10 17:19:13 +02001752 struct dma_ops_domain *dom;
Joerg Roedele241f8e762017-06-02 15:44:57 +02001753
Joerg Roedel9003d612017-08-10 17:19:13 +02001754 dom = container_of(iovad, struct dma_ops_domain, iovad);
Joerg Roedelfca6af62017-06-02 18:13:37 +02001755
1756 dma_ops_domain_flush_tlb(dom);
Joerg Roedelfca6af62017-06-02 18:13:37 +02001757}
1758
Joerg Roedel431b2a22008-07-11 17:14:22 +02001759/*
1760 * Free a domain, only used if something went wrong in the
1761 * allocation path and we need to free an already allocated page table
1762 */
Joerg Roedelec487d12008-06-26 21:27:58 +02001763static void dma_ops_domain_free(struct dma_ops_domain *dom)
1764{
1765 if (!dom)
1766 return;
1767
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001768 del_domain_from_list(&dom->domain);
1769
Joerg Roedel2d4c5152016-07-05 16:21:32 +02001770 put_iova_domain(&dom->iovad);
1771
Joerg Roedel86db2e52008-12-02 18:20:21 +01001772 free_pagetable(&dom->domain);
Joerg Roedelec487d12008-06-26 21:27:58 +02001773
Baoquan Hec3db9012016-09-15 16:50:52 +08001774 if (dom->domain.id)
1775 domain_id_free(dom->domain.id);
1776
Joerg Roedelec487d12008-06-26 21:27:58 +02001777 kfree(dom);
1778}
1779
Joerg Roedel431b2a22008-07-11 17:14:22 +02001780/*
1781 * Allocates a new protection domain usable for the dma_ops functions.
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001782 * It also initializes the page table and the address allocator data
Joerg Roedel431b2a22008-07-11 17:14:22 +02001783 * structures required for the dma_ops interface
1784 */
Joerg Roedel87a64d52009-11-24 17:26:43 +01001785static struct dma_ops_domain *dma_ops_domain_alloc(void)
Joerg Roedelec487d12008-06-26 21:27:58 +02001786{
1787 struct dma_ops_domain *dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001788
1789 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1790 if (!dma_dom)
1791 return NULL;
1792
Joerg Roedel7a5a5662015-06-30 08:56:11 +02001793 if (protection_domain_init(&dma_dom->domain))
Joerg Roedelec487d12008-06-26 21:27:58 +02001794 goto free_dma_dom;
Joerg Roedel7a5a5662015-06-30 08:56:11 +02001795
Joerg Roedelffec2192016-07-26 15:31:23 +02001796 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
Joerg Roedelec487d12008-06-26 21:27:58 +02001797 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
Joerg Roedel9fdb19d2008-12-02 17:46:25 +01001798 dma_dom->domain.flags = PD_DMA_OPS_MASK;
Joerg Roedelec487d12008-06-26 21:27:58 +02001799 if (!dma_dom->domain.pt_root)
1800 goto free_dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001801
Zhen Leiaa3ac942017-09-21 16:52:45 +01001802 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
Joerg Roedel307d5852016-07-05 11:54:04 +02001803
Joerg Roedel9003d612017-08-10 17:19:13 +02001804 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
Joerg Roedeld4241a22017-06-02 14:55:56 +02001805 goto free_dma_dom;
1806
Joerg Roedel9003d612017-08-10 17:19:13 +02001807 /* Initialize reserved ranges */
1808 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
Joerg Roedelfca6af62017-06-02 18:13:37 +02001809
Joerg Roedel2d4c5152016-07-05 16:21:32 +02001810 add_domain_to_list(&dma_dom->domain);
1811
Joerg Roedelec487d12008-06-26 21:27:58 +02001812 return dma_dom;
1813
1814free_dma_dom:
1815 dma_ops_domain_free(dma_dom);
1816
1817 return NULL;
1818}
1819
Joerg Roedel431b2a22008-07-11 17:14:22 +02001820/*
Joerg Roedel5b28df62008-12-02 17:49:42 +01001821 * little helper function to check whether a given protection domain is a
1822 * dma_ops domain
1823 */
1824static bool dma_ops_domain(struct protection_domain *domain)
1825{
1826 return domain->flags & PD_DMA_OPS_MASK;
1827}
1828
Gary R Hookff18c4e2017-12-20 09:47:08 -07001829static void set_dte_entry(u16 devid, struct protection_domain *domain,
1830 bool ats, bool ppr)
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02001831{
Joerg Roedel132bd682011-11-17 14:18:46 +01001832 u64 pte_root = 0;
Joerg Roedelee6c2862011-11-09 12:06:03 +01001833 u64 flags = 0;
Joerg Roedel863c74e2008-12-02 17:56:36 +01001834
Joerg Roedel132bd682011-11-17 14:18:46 +01001835 if (domain->mode != PAGE_MODE_NONE)
Tom Lendacky2543a782017-07-17 16:10:24 -05001836 pte_root = iommu_virt_to_phys(domain->pt_root);
Joerg Roedel132bd682011-11-17 14:18:46 +01001837
Joerg Roedel38ddf412008-09-11 10:38:32 +02001838 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1839 << DEV_ENTRY_MODE_SHIFT;
Baoquan He07a80a62017-08-09 16:33:36 +08001840 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02001841
Joerg Roedelee6c2862011-11-09 12:06:03 +01001842 flags = amd_iommu_dev_table[devid].data[1];
1843
Joerg Roedelfd7b5532011-04-05 15:31:08 +02001844 if (ats)
1845 flags |= DTE_FLAG_IOTLB;
1846
Gary R Hookff18c4e2017-12-20 09:47:08 -07001847 if (ppr) {
1848 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1849
1850 if (iommu_feature(iommu, FEATURE_EPHSUP))
1851 pte_root |= 1ULL << DEV_ENTRY_PPR;
1852 }
1853
Joerg Roedel52815b72011-11-17 17:24:28 +01001854 if (domain->flags & PD_IOMMUV2_MASK) {
Tom Lendacky2543a782017-07-17 16:10:24 -05001855 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
Joerg Roedel52815b72011-11-17 17:24:28 +01001856 u64 glx = domain->glx;
1857 u64 tmp;
1858
1859 pte_root |= DTE_FLAG_GV;
1860 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1861
1862 /* First mask out possible old values for GCR3 table */
1863 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1864 flags &= ~tmp;
1865
1866 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1867 flags &= ~tmp;
1868
1869 /* Encode GCR3 table into DTE */
1870 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1871 pte_root |= tmp;
1872
1873 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1874 flags |= tmp;
1875
1876 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1877 flags |= tmp;
1878 }
1879
Baoquan He45a01c42017-08-09 16:33:37 +08001880 flags &= ~DEV_DOMID_MASK;
Joerg Roedelee6c2862011-11-09 12:06:03 +01001881 flags |= domain->id;
1882
1883 amd_iommu_dev_table[devid].data[1] = flags;
1884 amd_iommu_dev_table[devid].data[0] = pte_root;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02001885}
1886
Joerg Roedel15898bb2009-11-24 15:39:42 +01001887static void clear_dte_entry(u16 devid)
Joerg Roedel355bf552008-12-08 12:02:41 +01001888{
Joerg Roedel355bf552008-12-08 12:02:41 +01001889 /* remove entry from the device table seen by the hardware */
Baoquan He07a80a62017-08-09 16:33:36 +08001890 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
Joerg Roedelcbf3ccd2015-10-20 14:59:36 +02001891 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
Joerg Roedel355bf552008-12-08 12:02:41 +01001892
Joerg Roedelc5cca142009-10-09 18:31:20 +02001893 amd_iommu_apply_erratum_63(devid);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001894}
1895
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001896static void do_attach(struct iommu_dev_data *dev_data,
1897 struct protection_domain *domain)
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001898{
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001899 struct amd_iommu *iommu;
Joerg Roedele25bfb52015-10-20 17:33:38 +02001900 u16 alias;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001901 bool ats;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001902
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001903 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedele3156042016-04-08 15:12:24 +02001904 alias = dev_data->alias;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001905 ats = dev_data->ats.enabled;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001906
1907 /* Update data structures */
1908 dev_data->domain = domain;
1909 list_add(&dev_data->list, &domain->dev_list);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001910
1911 /* Do reference counting */
1912 domain->dev_iommu[iommu->index] += 1;
1913 domain->dev_cnt += 1;
1914
Joerg Roedele25bfb52015-10-20 17:33:38 +02001915 /* Update device table */
Gary R Hookff18c4e2017-12-20 09:47:08 -07001916 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
Joerg Roedele25bfb52015-10-20 17:33:38 +02001917 if (alias != dev_data->devid)
Gary R Hookff18c4e2017-12-20 09:47:08 -07001918 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
Joerg Roedele25bfb52015-10-20 17:33:38 +02001919
Joerg Roedel6c542042011-06-09 17:07:31 +02001920 device_flush_dte(dev_data);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001921}
1922
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001923static void do_detach(struct iommu_dev_data *dev_data)
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001924{
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001925 struct amd_iommu *iommu;
Joerg Roedele25bfb52015-10-20 17:33:38 +02001926 u16 alias;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001927
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001928 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedele3156042016-04-08 15:12:24 +02001929 alias = dev_data->alias;
Joerg Roedelc5cca142009-10-09 18:31:20 +02001930
Joerg Roedelc4596112009-11-20 14:57:32 +01001931 /* decrease reference counters */
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001932 dev_data->domain->dev_iommu[iommu->index] -= 1;
1933 dev_data->domain->dev_cnt -= 1;
Joerg Roedel355bf552008-12-08 12:02:41 +01001934
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001935 /* Update data structures */
1936 dev_data->domain = NULL;
1937 list_del(&dev_data->list);
Joerg Roedelf62dda62011-06-09 12:55:35 +02001938 clear_dte_entry(dev_data->devid);
Joerg Roedele25bfb52015-10-20 17:33:38 +02001939 if (alias != dev_data->devid)
1940 clear_dte_entry(alias);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001941
1942 /* Flush the DTE entry */
Joerg Roedel6c542042011-06-09 17:07:31 +02001943 device_flush_dte(dev_data);
Joerg Roedel15898bb2009-11-24 15:39:42 +01001944}
1945
1946/*
Anna-Maria Gleixner29a0c412018-05-07 14:53:26 +02001947 * If a device is not yet associated with a domain, this function makes the
1948 * device visible in the domain
Joerg Roedel15898bb2009-11-24 15:39:42 +01001949 */
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001950static int __attach_device(struct iommu_dev_data *dev_data,
Joerg Roedel15898bb2009-11-24 15:39:42 +01001951 struct protection_domain *domain)
1952{
Julia Lawall84fe6c12010-05-27 12:31:51 +02001953 int ret;
Joerg Roedel657cbb62009-11-23 15:26:46 +01001954
Joerg Roedel15898bb2009-11-24 15:39:42 +01001955 /* lock domain */
1956 spin_lock(&domain->lock);
1957
Joerg Roedel397111a2014-08-05 17:31:51 +02001958 ret = -EBUSY;
Joerg Roedel150952f2015-10-20 17:33:35 +02001959 if (dev_data->domain != NULL)
Joerg Roedel397111a2014-08-05 17:31:51 +02001960 goto out_unlock;
Joerg Roedel24100052009-11-25 15:59:57 +01001961
Joerg Roedel397111a2014-08-05 17:31:51 +02001962 /* Attach alias group root */
Joerg Roedel150952f2015-10-20 17:33:35 +02001963 do_attach(dev_data, domain);
Joerg Roedel24100052009-11-25 15:59:57 +01001964
Julia Lawall84fe6c12010-05-27 12:31:51 +02001965 ret = 0;
1966
1967out_unlock:
1968
Joerg Roedel355bf552008-12-08 12:02:41 +01001969 /* ready */
1970 spin_unlock(&domain->lock);
Joerg Roedel21129f72009-09-01 11:59:42 +02001971
Julia Lawall84fe6c12010-05-27 12:31:51 +02001972 return ret;
Joerg Roedel15898bb2009-11-24 15:39:42 +01001973}
1974
Joerg Roedel52815b72011-11-17 17:24:28 +01001975
1976static void pdev_iommuv2_disable(struct pci_dev *pdev)
1977{
1978 pci_disable_ats(pdev);
1979 pci_disable_pri(pdev);
1980 pci_disable_pasid(pdev);
1981}
1982
Joerg Roedel6a113dd2011-12-01 12:04:58 +01001983/* FIXME: Change generic reset-function to do the same */
1984static int pri_reset_while_enabled(struct pci_dev *pdev)
1985{
1986 u16 control;
1987 int pos;
1988
Joerg Roedel46277b72011-12-07 14:34:02 +01001989 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01001990 if (!pos)
1991 return -EINVAL;
1992
Joerg Roedel46277b72011-12-07 14:34:02 +01001993 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1994 control |= PCI_PRI_CTRL_RESET;
1995 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01001996
1997 return 0;
1998}
1999
Joerg Roedel52815b72011-11-17 17:24:28 +01002000static int pdev_iommuv2_enable(struct pci_dev *pdev)
2001{
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002002 bool reset_enable;
2003 int reqs, ret;
2004
2005 /* FIXME: Hardcode number of outstanding requests for now */
2006 reqs = 32;
2007 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2008 reqs = 1;
2009 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
Joerg Roedel52815b72011-11-17 17:24:28 +01002010
2011 /* Only allow access to user-accessible pages */
2012 ret = pci_enable_pasid(pdev, 0);
2013 if (ret)
2014 goto out_err;
2015
2016 /* First reset the PRI state of the device */
2017 ret = pci_reset_pri(pdev);
2018 if (ret)
2019 goto out_err;
2020
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002021 /* Enable PRI */
2022 ret = pci_enable_pri(pdev, reqs);
Joerg Roedel52815b72011-11-17 17:24:28 +01002023 if (ret)
2024 goto out_err;
2025
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002026 if (reset_enable) {
2027 ret = pri_reset_while_enabled(pdev);
2028 if (ret)
2029 goto out_err;
2030 }
2031
Joerg Roedel52815b72011-11-17 17:24:28 +01002032 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2033 if (ret)
2034 goto out_err;
2035
2036 return 0;
2037
2038out_err:
2039 pci_disable_pri(pdev);
2040 pci_disable_pasid(pdev);
2041
2042 return ret;
2043}
2044
Joerg Roedelc99afa22011-11-21 18:19:25 +01002045/* FIXME: Move this to PCI code */
Joerg Roedela3b93122012-04-12 12:49:26 +02002046#define PCI_PRI_TLP_OFF (1 << 15)
Joerg Roedelc99afa22011-11-21 18:19:25 +01002047
Joerg Roedel98f1ad22012-07-06 13:28:37 +02002048static bool pci_pri_tlp_required(struct pci_dev *pdev)
Joerg Roedelc99afa22011-11-21 18:19:25 +01002049{
Joerg Roedela3b93122012-04-12 12:49:26 +02002050 u16 status;
Joerg Roedelc99afa22011-11-21 18:19:25 +01002051 int pos;
2052
Joerg Roedel46277b72011-12-07 14:34:02 +01002053 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002054 if (!pos)
2055 return false;
2056
Joerg Roedela3b93122012-04-12 12:49:26 +02002057 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002058
Joerg Roedela3b93122012-04-12 12:49:26 +02002059 return (status & PCI_PRI_TLP_OFF) ? true : false;
Joerg Roedelc99afa22011-11-21 18:19:25 +01002060}
2061
Joerg Roedel15898bb2009-11-24 15:39:42 +01002062/*
Anna-Maria Gleixner29a0c412018-05-07 14:53:26 +02002063 * If a device is not yet associated with a domain, this function makes the
2064 * device visible in the domain
Joerg Roedel15898bb2009-11-24 15:39:42 +01002065 */
2066static int attach_device(struct device *dev,
2067 struct protection_domain *domain)
2068{
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -04002069 struct pci_dev *pdev;
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002070 struct iommu_dev_data *dev_data;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002071 unsigned long flags;
2072 int ret;
2073
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002074 dev_data = get_dev_data(dev);
2075
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -04002076 if (!dev_is_pci(dev))
2077 goto skip_ats_check;
2078
2079 pdev = to_pci_dev(dev);
Joerg Roedel52815b72011-11-17 17:24:28 +01002080 if (domain->flags & PD_IOMMUV2_MASK) {
Joerg Roedel02ca2022015-07-28 16:58:49 +02002081 if (!dev_data->passthrough)
Joerg Roedel52815b72011-11-17 17:24:28 +01002082 return -EINVAL;
2083
Joerg Roedel02ca2022015-07-28 16:58:49 +02002084 if (dev_data->iommu_v2) {
2085 if (pdev_iommuv2_enable(pdev) != 0)
2086 return -EINVAL;
Joerg Roedel52815b72011-11-17 17:24:28 +01002087
Joerg Roedel02ca2022015-07-28 16:58:49 +02002088 dev_data->ats.enabled = true;
2089 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2090 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2091 }
Joerg Roedel52815b72011-11-17 17:24:28 +01002092 } else if (amd_iommu_iotlb_sup &&
2093 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002094 dev_data->ats.enabled = true;
2095 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2096 }
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002097
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -04002098skip_ats_check:
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +01002099 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002100 ret = __attach_device(dev_data, domain);
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +01002101 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002102
2103 /*
2104 * We might boot into a crash-kernel here. The crashed kernel
2105 * left the caches in the IOMMU dirty. So we have to flush
2106 * here to evict all dirty stuff.
2107 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02002108 domain_flush_tlb_pde(domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002109
2110 return ret;
2111}
2112
2113/*
2114 * Removes a device from a protection domain (unlocked)
2115 */
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002116static void __detach_device(struct iommu_dev_data *dev_data)
Joerg Roedel15898bb2009-11-24 15:39:42 +01002117{
Joerg Roedel2ca76272010-01-22 16:45:31 +01002118 struct protection_domain *domain;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002119
Joerg Roedel2ca76272010-01-22 16:45:31 +01002120 domain = dev_data->domain;
2121
Joerg Roedelf1dd0a82015-10-20 17:33:36 +02002122 spin_lock(&domain->lock);
Joerg Roedel24100052009-11-25 15:59:57 +01002123
Joerg Roedel150952f2015-10-20 17:33:35 +02002124 do_detach(dev_data);
Joerg Roedel71f77582011-06-09 19:03:15 +02002125
Joerg Roedelf1dd0a82015-10-20 17:33:36 +02002126 spin_unlock(&domain->lock);
Joerg Roedel355bf552008-12-08 12:02:41 +01002127}
2128
2129/*
2130 * Removes a device from a protection domain (with devtable_lock held)
2131 */
Joerg Roedel15898bb2009-11-24 15:39:42 +01002132static void detach_device(struct device *dev)
Joerg Roedel355bf552008-12-08 12:02:41 +01002133{
Joerg Roedel52815b72011-11-17 17:24:28 +01002134 struct protection_domain *domain;
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002135 struct iommu_dev_data *dev_data;
Joerg Roedel355bf552008-12-08 12:02:41 +01002136 unsigned long flags;
2137
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002138 dev_data = get_dev_data(dev);
Joerg Roedel52815b72011-11-17 17:24:28 +01002139 domain = dev_data->domain;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002140
Anna-Maria Gleixnerea3fd042018-05-07 14:53:27 +02002141 /*
2142 * First check if the device is still attached. It might already
2143 * be detached from its domain because the generic
2144 * iommu_detach_group code detached it and we try again here in
2145 * our alias handling.
2146 */
2147 if (WARN_ON(!dev_data->domain))
2148 return;
2149
Joerg Roedel355bf552008-12-08 12:02:41 +01002150 /* lock device table */
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +01002151 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002152 __detach_device(dev_data);
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +01002153 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002154
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -04002155 if (!dev_is_pci(dev))
2156 return;
2157
Joerg Roedel02ca2022015-07-28 16:58:49 +02002158 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
Joerg Roedel52815b72011-11-17 17:24:28 +01002159 pdev_iommuv2_disable(to_pci_dev(dev));
2160 else if (dev_data->ats.enabled)
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002161 pci_disable_ats(to_pci_dev(dev));
Joerg Roedel52815b72011-11-17 17:24:28 +01002162
2163 dev_data->ats.enabled = false;
Joerg Roedel355bf552008-12-08 12:02:41 +01002164}
Joerg Roedele275a2a2008-12-10 18:27:25 +01002165
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002166static int amd_iommu_add_device(struct device *dev)
Joerg Roedel15898bb2009-11-24 15:39:42 +01002167{
Joerg Roedel71f77582011-06-09 19:03:15 +02002168 struct iommu_dev_data *dev_data;
Joerg Roedel07ee8692015-05-28 18:41:42 +02002169 struct iommu_domain *domain;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002170 struct amd_iommu *iommu;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002171 int ret, devid;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002172
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002173 if (!check_device(dev) || get_dev_data(dev))
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002174 return 0;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002175
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002176 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02002177 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002178 return devid;
2179
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002180 iommu = amd_iommu_rlookup_table[devid];
Joerg Roedele275a2a2008-12-10 18:27:25 +01002181
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002182 ret = iommu_init_device(dev);
Joerg Roedel4d58b8a2015-06-11 09:21:39 +02002183 if (ret) {
2184 if (ret != -ENOTSUPP)
2185 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2186 dev_name(dev));
Joerg Roedel657cbb62009-11-23 15:26:46 +01002187
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002188 iommu_ignore_device(dev);
Christoph Hellwigfec777c2018-03-19 11:38:15 +01002189 dev->dma_ops = &dma_direct_ops;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002190 goto out;
2191 }
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002192 init_iommu_group(dev);
Joerg Roedele275a2a2008-12-10 18:27:25 +01002193
Joerg Roedel07ee8692015-05-28 18:41:42 +02002194 dev_data = get_dev_data(dev);
Joerg Roedel4d58b8a2015-06-11 09:21:39 +02002195
2196 BUG_ON(!dev_data);
2197
Joerg Roedel1e6a7b02015-07-28 16:58:48 +02002198 if (iommu_pass_through || dev_data->iommu_v2)
Joerg Roedel07ee8692015-05-28 18:41:42 +02002199 iommu_request_dm_for_dev(dev);
2200
2201 /* Domains are initialized for this device - have a look what we ended up with */
2202 domain = iommu_get_domain_for_dev(dev);
Joerg Roedel32302322015-07-28 16:58:50 +02002203 if (domain->type == IOMMU_DOMAIN_IDENTITY)
Joerg Roedel07ee8692015-05-28 18:41:42 +02002204 dev_data->passthrough = true;
Joerg Roedel32302322015-07-28 16:58:50 +02002205 else
Bart Van Assche56579332017-01-20 13:04:02 -08002206 dev->dma_ops = &amd_iommu_dma_ops;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002207
2208out:
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002209 iommu_completion_wait(iommu);
2210
Joerg Roedele275a2a2008-12-10 18:27:25 +01002211 return 0;
2212}
2213
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002214static void amd_iommu_remove_device(struct device *dev)
Joerg Roedel8638c492009-12-10 11:12:25 +01002215{
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002216 struct amd_iommu *iommu;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002217 int devid;
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002218
2219 if (!check_device(dev))
2220 return;
2221
2222 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02002223 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002224 return;
2225
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002226 iommu = amd_iommu_rlookup_table[devid];
2227
2228 iommu_uninit_device(dev);
2229 iommu_completion_wait(iommu);
Joerg Roedel8638c492009-12-10 11:12:25 +01002230}
2231
Wan Zongshunb097d112016-04-01 09:06:04 -04002232static struct iommu_group *amd_iommu_device_group(struct device *dev)
2233{
2234 if (dev_is_pci(dev))
2235 return pci_device_group(dev);
2236
2237 return acpihid_device_group(dev);
2238}
2239
Joerg Roedel431b2a22008-07-11 17:14:22 +02002240/*****************************************************************************
2241 *
2242 * The next functions belong to the dma_ops mapping/unmapping code.
2243 *
2244 *****************************************************************************/
2245
2246/*
2247 * In the dma_ops path we only have the struct device. This function
2248 * finds the corresponding IOMMU, the protection domain and the
2249 * requestor id for a given device.
2250 * If the device is not yet associated with a domain this is also done
2251 * in this function.
2252 */
Joerg Roedel94f6d192009-11-24 16:40:02 +01002253static struct protection_domain *get_domain(struct device *dev)
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002254{
Joerg Roedel94f6d192009-11-24 16:40:02 +01002255 struct protection_domain *domain;
Baoquan Hedf3f7a62017-08-09 16:33:41 +08002256 struct iommu_domain *io_domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002257
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002258 if (!check_device(dev))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002259 return ERR_PTR(-EINVAL);
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002260
Joerg Roedeld26592a2016-07-07 15:31:13 +02002261 domain = get_dev_data(dev)->domain;
Baoquan Hedf3f7a62017-08-09 16:33:41 +08002262 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2263 get_dev_data(dev)->defer_attach = false;
2264 io_domain = iommu_get_domain_for_dev(dev);
2265 domain = to_pdomain(io_domain);
2266 attach_device(dev, domain);
2267 }
Baoquan Heec62b1a2017-08-24 21:13:57 +08002268 if (domain == NULL)
2269 return ERR_PTR(-EBUSY);
2270
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002271 if (!dma_ops_domain(domain))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002272 return ERR_PTR(-EBUSY);
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002273
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002274 return domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002275}
2276
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002277static void update_device_table(struct protection_domain *domain)
2278{
Joerg Roedel492667d2009-11-27 13:25:47 +01002279 struct iommu_dev_data *dev_data;
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002280
Joerg Roedel3254de62016-07-26 15:18:54 +02002281 list_for_each_entry(dev_data, &domain->dev_list, list) {
Gary R Hookff18c4e2017-12-20 09:47:08 -07002282 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2283 dev_data->iommu_v2);
Joerg Roedel3254de62016-07-26 15:18:54 +02002284
2285 if (dev_data->devid == dev_data->alias)
2286 continue;
2287
2288 /* There is an alias, update device table entry for it */
Gary R Hookff18c4e2017-12-20 09:47:08 -07002289 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2290 dev_data->iommu_v2);
Joerg Roedel3254de62016-07-26 15:18:54 +02002291 }
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002292}
2293
2294static void update_domain(struct protection_domain *domain)
2295{
2296 if (!domain->updated)
2297 return;
2298
2299 update_device_table(domain);
Joerg Roedel17b124b2011-04-06 18:01:35 +02002300
2301 domain_flush_devices(domain);
2302 domain_flush_tlb_pde(domain);
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002303
2304 domain->updated = false;
2305}
2306
Joerg Roedelf37f7f32016-07-08 11:47:22 +02002307static int dir2prot(enum dma_data_direction direction)
2308{
2309 if (direction == DMA_TO_DEVICE)
2310 return IOMMU_PROT_IR;
2311 else if (direction == DMA_FROM_DEVICE)
2312 return IOMMU_PROT_IW;
2313 else if (direction == DMA_BIDIRECTIONAL)
2314 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2315 else
2316 return 0;
2317}
Baoquan Hedaae2d22017-08-09 16:33:43 +08002318
Joerg Roedel431b2a22008-07-11 17:14:22 +02002319/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02002320 * This function contains common code for mapping of a physically
Joerg Roedel24f81162008-12-08 14:25:39 +01002321 * contiguous memory region into DMA address space. It is used by all
2322 * mapping functions provided with this IOMMU driver.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002323 * Must be called with the domain lock held.
2324 */
Joerg Roedelcb76c322008-06-26 21:28:00 +02002325static dma_addr_t __map_single(struct device *dev,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002326 struct dma_ops_domain *dma_dom,
2327 phys_addr_t paddr,
2328 size_t size,
Joerg Roedelf37f7f32016-07-08 11:47:22 +02002329 enum dma_data_direction direction,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002330 u64 dma_mask)
Joerg Roedelcb76c322008-06-26 21:28:00 +02002331{
2332 dma_addr_t offset = paddr & ~PAGE_MASK;
Joerg Roedel53812c12009-05-12 12:17:38 +02002333 dma_addr_t address, start, ret;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002334 unsigned int pages;
Joerg Roedel518d9b42016-07-05 14:39:47 +02002335 int prot = 0;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002336 int i;
2337
Joerg Roedele3c449f2008-10-15 22:02:11 -07002338 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002339 paddr &= PAGE_MASK;
2340
Joerg Roedel256e4622016-07-05 14:23:01 +02002341 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
Christoph Hellwiga8695722017-05-21 13:26:45 +02002342 if (address == AMD_IOMMU_MAPPING_ERROR)
Joerg Roedel266a3bd2015-12-21 18:54:24 +01002343 goto out;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002344
Joerg Roedelf37f7f32016-07-08 11:47:22 +02002345 prot = dir2prot(direction);
Joerg Roedel518d9b42016-07-05 14:39:47 +02002346
Joerg Roedelcb76c322008-06-26 21:28:00 +02002347 start = address;
2348 for (i = 0; i < pages; ++i) {
Joerg Roedel518d9b42016-07-05 14:39:47 +02002349 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2350 PAGE_SIZE, prot, GFP_ATOMIC);
2351 if (ret)
Joerg Roedel53812c12009-05-12 12:17:38 +02002352 goto out_unmap;
2353
Joerg Roedelcb76c322008-06-26 21:28:00 +02002354 paddr += PAGE_SIZE;
2355 start += PAGE_SIZE;
2356 }
2357 address += offset;
2358
Joerg Roedelab7032b2015-12-21 18:47:11 +01002359 if (unlikely(amd_iommu_np_cache)) {
Joerg Roedel17b124b2011-04-06 18:01:35 +02002360 domain_flush_pages(&dma_dom->domain, address, size);
Joerg Roedelab7032b2015-12-21 18:47:11 +01002361 domain_flush_complete(&dma_dom->domain);
2362 }
Joerg Roedel270cab242008-09-04 15:49:46 +02002363
Joerg Roedelcb76c322008-06-26 21:28:00 +02002364out:
2365 return address;
Joerg Roedel53812c12009-05-12 12:17:38 +02002366
2367out_unmap:
2368
2369 for (--i; i >= 0; --i) {
2370 start -= PAGE_SIZE;
Joerg Roedel518d9b42016-07-05 14:39:47 +02002371 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
Joerg Roedel53812c12009-05-12 12:17:38 +02002372 }
2373
Joerg Roedel256e4622016-07-05 14:23:01 +02002374 domain_flush_tlb(&dma_dom->domain);
2375 domain_flush_complete(&dma_dom->domain);
2376
2377 dma_ops_free_iova(dma_dom, address, pages);
Joerg Roedel53812c12009-05-12 12:17:38 +02002378
Christoph Hellwiga8695722017-05-21 13:26:45 +02002379 return AMD_IOMMU_MAPPING_ERROR;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002380}
2381
Joerg Roedel431b2a22008-07-11 17:14:22 +02002382/*
2383 * Does the reverse of the __map_single function. Must be called with
2384 * the domain lock held too
2385 */
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002386static void __unmap_single(struct dma_ops_domain *dma_dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002387 dma_addr_t dma_addr,
2388 size_t size,
2389 int dir)
2390{
2391 dma_addr_t i, start;
2392 unsigned int pages;
2393
Joerg Roedele3c449f2008-10-15 22:02:11 -07002394 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002395 dma_addr &= PAGE_MASK;
2396 start = dma_addr;
2397
2398 for (i = 0; i < pages; ++i) {
Joerg Roedel518d9b42016-07-05 14:39:47 +02002399 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002400 start += PAGE_SIZE;
2401 }
2402
Joerg Roedelb1516a12016-07-06 13:07:22 +02002403 if (amd_iommu_unmap_flush) {
Joerg Roedelb1516a12016-07-06 13:07:22 +02002404 domain_flush_tlb(&dma_dom->domain);
2405 domain_flush_complete(&dma_dom->domain);
Zhen Lei3c120142018-06-06 10:18:46 +08002406 dma_ops_free_iova(dma_dom, dma_addr, pages);
Joerg Roedelb1516a12016-07-06 13:07:22 +02002407 } else {
Joerg Roedel9003d612017-08-10 17:19:13 +02002408 pages = __roundup_pow_of_two(pages);
2409 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
Joerg Roedelb1516a12016-07-06 13:07:22 +02002410 }
Joerg Roedelcb76c322008-06-26 21:28:00 +02002411}
2412
Joerg Roedel431b2a22008-07-11 17:14:22 +02002413/*
2414 * The exported map_single function for dma_ops.
2415 */
FUJITA Tomonori51491362009-01-05 23:47:25 +09002416static dma_addr_t map_page(struct device *dev, struct page *page,
2417 unsigned long offset, size_t size,
2418 enum dma_data_direction dir,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -07002419 unsigned long attrs)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002420{
FUJITA Tomonori51491362009-01-05 23:47:25 +09002421 phys_addr_t paddr = page_to_phys(page) + offset;
Joerg Roedel92d420e2015-12-21 19:31:33 +01002422 struct protection_domain *domain;
Joerg Roedelb3311b02016-07-08 13:31:31 +02002423 struct dma_ops_domain *dma_dom;
Joerg Roedel92d420e2015-12-21 19:31:33 +01002424 u64 dma_mask;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002425
Joerg Roedel94f6d192009-11-24 16:40:02 +01002426 domain = get_domain(dev);
2427 if (PTR_ERR(domain) == -EINVAL)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002428 return (dma_addr_t)paddr;
Joerg Roedel94f6d192009-11-24 16:40:02 +01002429 else if (IS_ERR(domain))
Christoph Hellwiga8695722017-05-21 13:26:45 +02002430 return AMD_IOMMU_MAPPING_ERROR;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002431
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002432 dma_mask = *dev->dma_mask;
Joerg Roedelb3311b02016-07-08 13:31:31 +02002433 dma_dom = to_dma_ops_domain(domain);
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002434
Joerg Roedelb3311b02016-07-08 13:31:31 +02002435 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002436}
2437
Joerg Roedel431b2a22008-07-11 17:14:22 +02002438/*
2439 * The exported unmap_single function for dma_ops.
2440 */
FUJITA Tomonori51491362009-01-05 23:47:25 +09002441static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -07002442 enum dma_data_direction dir, unsigned long attrs)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002443{
Joerg Roedel4da70b92008-06-26 21:28:01 +02002444 struct protection_domain *domain;
Joerg Roedelb3311b02016-07-08 13:31:31 +02002445 struct dma_ops_domain *dma_dom;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002446
Joerg Roedel94f6d192009-11-24 16:40:02 +01002447 domain = get_domain(dev);
2448 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002449 return;
2450
Joerg Roedelb3311b02016-07-08 13:31:31 +02002451 dma_dom = to_dma_ops_domain(domain);
2452
2453 __unmap_single(dma_dom, dma_addr, size, dir);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002454}
2455
Joerg Roedel80187fd2016-07-06 17:20:54 +02002456static int sg_num_pages(struct device *dev,
2457 struct scatterlist *sglist,
2458 int nelems)
2459{
2460 unsigned long mask, boundary_size;
2461 struct scatterlist *s;
2462 int i, npages = 0;
2463
2464 mask = dma_get_seg_boundary(dev);
2465 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2466 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2467
2468 for_each_sg(sglist, s, nelems, i) {
2469 int p, n;
2470
2471 s->dma_address = npages << PAGE_SHIFT;
2472 p = npages % boundary_size;
2473 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2474 if (p + n > boundary_size)
2475 npages += boundary_size - p;
2476 npages += n;
2477 }
2478
2479 return npages;
2480}
2481
Joerg Roedel431b2a22008-07-11 17:14:22 +02002482/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02002483 * The exported map_sg function for dma_ops (handles scatter-gather
2484 * lists).
2485 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002486static int map_sg(struct device *dev, struct scatterlist *sglist,
Joerg Roedel80187fd2016-07-06 17:20:54 +02002487 int nelems, enum dma_data_direction direction,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -07002488 unsigned long attrs)
Joerg Roedel65b050a2008-06-26 21:28:02 +02002489{
Joerg Roedel80187fd2016-07-06 17:20:54 +02002490 int mapped_pages = 0, npages = 0, prot = 0, i;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002491 struct protection_domain *domain;
Joerg Roedel80187fd2016-07-06 17:20:54 +02002492 struct dma_ops_domain *dma_dom;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002493 struct scatterlist *s;
Joerg Roedel80187fd2016-07-06 17:20:54 +02002494 unsigned long address;
Joerg Roedel832a90c2008-09-18 15:54:23 +02002495 u64 dma_mask;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002496
Joerg Roedel94f6d192009-11-24 16:40:02 +01002497 domain = get_domain(dev);
Joerg Roedela0e191b2013-04-09 15:04:36 +02002498 if (IS_ERR(domain))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002499 return 0;
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002500
Joerg Roedelb3311b02016-07-08 13:31:31 +02002501 dma_dom = to_dma_ops_domain(domain);
Joerg Roedel832a90c2008-09-18 15:54:23 +02002502 dma_mask = *dev->dma_mask;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002503
Joerg Roedel80187fd2016-07-06 17:20:54 +02002504 npages = sg_num_pages(dev, sglist, nelems);
2505
2506 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
Christoph Hellwiga8695722017-05-21 13:26:45 +02002507 if (address == AMD_IOMMU_MAPPING_ERROR)
Joerg Roedel80187fd2016-07-06 17:20:54 +02002508 goto out_err;
2509
2510 prot = dir2prot(direction);
2511
2512 /* Map all sg entries */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002513 for_each_sg(sglist, s, nelems, i) {
Joerg Roedel80187fd2016-07-06 17:20:54 +02002514 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002515
Joerg Roedel80187fd2016-07-06 17:20:54 +02002516 for (j = 0; j < pages; ++j) {
2517 unsigned long bus_addr, phys_addr;
2518 int ret;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002519
Joerg Roedel80187fd2016-07-06 17:20:54 +02002520 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2521 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2522 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2523 if (ret)
2524 goto out_unmap;
2525
2526 mapped_pages += 1;
2527 }
Joerg Roedel65b050a2008-06-26 21:28:02 +02002528 }
2529
Joerg Roedel80187fd2016-07-06 17:20:54 +02002530 /* Everything is mapped - write the right values into s->dma_address */
2531 for_each_sg(sglist, s, nelems, i) {
2532 s->dma_address += address + s->offset;
2533 s->dma_length = s->length;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002534 }
2535
Joerg Roedel80187fd2016-07-06 17:20:54 +02002536 return nelems;
2537
2538out_unmap:
2539 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2540 dev_name(dev), npages);
2541
2542 for_each_sg(sglist, s, nelems, i) {
2543 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2544
2545 for (j = 0; j < pages; ++j) {
2546 unsigned long bus_addr;
2547
2548 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2549 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2550
2551 if (--mapped_pages)
2552 goto out_free_iova;
2553 }
2554 }
2555
2556out_free_iova:
2557 free_iova_fast(&dma_dom->iovad, address, npages);
2558
2559out_err:
Joerg Roedel92d420e2015-12-21 19:31:33 +01002560 return 0;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002561}
2562
Joerg Roedel431b2a22008-07-11 17:14:22 +02002563/*
2564 * The exported map_sg function for dma_ops (handles scatter-gather
2565 * lists).
2566 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002567static void unmap_sg(struct device *dev, struct scatterlist *sglist,
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002568 int nelems, enum dma_data_direction dir,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -07002569 unsigned long attrs)
Joerg Roedel65b050a2008-06-26 21:28:02 +02002570{
Joerg Roedel65b050a2008-06-26 21:28:02 +02002571 struct protection_domain *domain;
Joerg Roedelb3311b02016-07-08 13:31:31 +02002572 struct dma_ops_domain *dma_dom;
Joerg Roedel80187fd2016-07-06 17:20:54 +02002573 unsigned long startaddr;
2574 int npages = 2;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002575
Joerg Roedel94f6d192009-11-24 16:40:02 +01002576 domain = get_domain(dev);
2577 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002578 return;
2579
Joerg Roedel80187fd2016-07-06 17:20:54 +02002580 startaddr = sg_dma_address(sglist) & PAGE_MASK;
Joerg Roedelb3311b02016-07-08 13:31:31 +02002581 dma_dom = to_dma_ops_domain(domain);
Joerg Roedel80187fd2016-07-06 17:20:54 +02002582 npages = sg_num_pages(dev, sglist, nelems);
2583
Joerg Roedelb3311b02016-07-08 13:31:31 +02002584 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002585}
2586
Joerg Roedel431b2a22008-07-11 17:14:22 +02002587/*
2588 * The exported alloc_coherent function for dma_ops.
2589 */
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002590static void *alloc_coherent(struct device *dev, size_t size,
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002591 dma_addr_t *dma_addr, gfp_t flag,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -07002592 unsigned long attrs)
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002593{
Joerg Roedel832a90c2008-09-18 15:54:23 +02002594 u64 dma_mask = dev->coherent_dma_mask;
Linus Torvaldse16c4792018-06-11 12:22:12 -07002595 struct protection_domain *domain;
2596 struct dma_ops_domain *dma_dom;
2597 struct page *page;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002598
Linus Torvaldse16c4792018-06-11 12:22:12 -07002599 domain = get_domain(dev);
2600 if (PTR_ERR(domain) == -EINVAL) {
2601 page = alloc_pages(flag, get_order(size));
2602 *dma_addr = page_to_phys(page);
2603 return page_address(page);
2604 } else if (IS_ERR(domain))
2605 return NULL;
2606
2607 dma_dom = to_dma_ops_domain(domain);
2608 size = PAGE_ALIGN(size);
2609 dma_mask = dev->coherent_dma_mask;
2610 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2611 flag |= __GFP_ZERO;
2612
2613 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2614 if (!page) {
2615 if (!gfpflags_allow_blocking(flag))
Joerg Roedel3b839a52015-04-01 14:58:47 +02002616 return NULL;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002617
Linus Torvaldse16c4792018-06-11 12:22:12 -07002618 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
Marek Szyprowskid834c5a2018-08-17 15:49:00 -07002619 get_order(size), flag & __GFP_NOWARN);
Linus Torvaldse16c4792018-06-11 12:22:12 -07002620 if (!page)
2621 return NULL;
2622 }
Christoph Hellwigb4686202018-03-19 11:38:19 +01002623
Joerg Roedel832a90c2008-09-18 15:54:23 +02002624 if (!dma_mask)
2625 dma_mask = *dev->dma_mask;
2626
Linus Torvaldse16c4792018-06-11 12:22:12 -07002627 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2628 size, DMA_BIDIRECTIONAL, dma_mask);
2629
Christoph Hellwiga8695722017-05-21 13:26:45 +02002630 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
Joerg Roedel5b28df62008-12-02 17:49:42 +01002631 goto out_free;
Linus Torvaldse16c4792018-06-11 12:22:12 -07002632
2633 return page_address(page);
Joerg Roedel5b28df62008-12-02 17:49:42 +01002634
2635out_free:
Linus Torvaldse16c4792018-06-11 12:22:12 -07002636
2637 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2638 __free_pages(page, get_order(size));
2639
Joerg Roedel5b28df62008-12-02 17:49:42 +01002640 return NULL;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002641}
2642
Joerg Roedel431b2a22008-07-11 17:14:22 +02002643/*
2644 * The exported free_coherent function for dma_ops.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002645 */
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002646static void free_coherent(struct device *dev, size_t size,
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002647 void *virt_addr, dma_addr_t dma_addr,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -07002648 unsigned long attrs)
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002649{
Linus Torvaldse16c4792018-06-11 12:22:12 -07002650 struct protection_domain *domain;
2651 struct dma_ops_domain *dma_dom;
2652 struct page *page;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002653
Linus Torvaldse16c4792018-06-11 12:22:12 -07002654 page = virt_to_page(virt_addr);
Joerg Roedel3b839a52015-04-01 14:58:47 +02002655 size = PAGE_ALIGN(size);
2656
Linus Torvaldse16c4792018-06-11 12:22:12 -07002657 domain = get_domain(dev);
2658 if (IS_ERR(domain))
2659 goto free_mem;
Joerg Roedel5b28df62008-12-02 17:49:42 +01002660
Linus Torvaldse16c4792018-06-11 12:22:12 -07002661 dma_dom = to_dma_ops_domain(domain);
Joerg Roedelb3311b02016-07-08 13:31:31 +02002662
Linus Torvaldse16c4792018-06-11 12:22:12 -07002663 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2664
2665free_mem:
2666 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2667 __free_pages(page, get_order(size));
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002668}
2669
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002670/*
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002671 * This function is called by the DMA layer to find out if we can handle a
2672 * particular device. It is part of the dma_ops.
2673 */
2674static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2675{
Christoph Hellwigfec777c2018-03-19 11:38:15 +01002676 if (!dma_direct_supported(dev, mask))
Christoph Hellwig5860acc2017-05-22 11:38:27 +02002677 return 0;
Joerg Roedel420aef82009-11-23 16:14:57 +01002678 return check_device(dev);
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002679}
2680
Christoph Hellwiga8695722017-05-21 13:26:45 +02002681static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2682{
2683 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2684}
2685
Bart Van Assche52997092017-01-20 13:04:01 -08002686static const struct dma_map_ops amd_iommu_dma_ops = {
Joerg Roedela639a8e2015-12-22 16:06:49 +01002687 .alloc = alloc_coherent,
2688 .free = free_coherent,
2689 .map_page = map_page,
2690 .unmap_page = unmap_page,
2691 .map_sg = map_sg,
2692 .unmap_sg = unmap_sg,
2693 .dma_supported = amd_iommu_dma_supported,
Christoph Hellwiga8695722017-05-21 13:26:45 +02002694 .mapping_error = amd_iommu_mapping_error,
Joerg Roedel6631ee92008-06-26 21:28:05 +02002695};
2696
Joerg Roedel81cd07b2016-07-07 18:01:10 +02002697static int init_reserved_iova_ranges(void)
2698{
2699 struct pci_dev *pdev = NULL;
2700 struct iova *val;
2701
Zhen Leiaa3ac942017-09-21 16:52:45 +01002702 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
Joerg Roedel81cd07b2016-07-07 18:01:10 +02002703
2704 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2705 &reserved_rbtree_key);
2706
2707 /* MSI memory range */
2708 val = reserve_iova(&reserved_iova_ranges,
2709 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2710 if (!val) {
2711 pr_err("Reserving MSI range failed\n");
2712 return -ENOMEM;
2713 }
2714
2715 /* HT memory range */
2716 val = reserve_iova(&reserved_iova_ranges,
2717 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2718 if (!val) {
2719 pr_err("Reserving HT range failed\n");
2720 return -ENOMEM;
2721 }
2722
2723 /*
2724 * Memory used for PCI resources
2725 * FIXME: Check whether we can reserve the PCI-hole completly
2726 */
2727 for_each_pci_dev(pdev) {
2728 int i;
2729
2730 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2731 struct resource *r = &pdev->resource[i];
2732
2733 if (!(r->flags & IORESOURCE_MEM))
2734 continue;
2735
2736 val = reserve_iova(&reserved_iova_ranges,
2737 IOVA_PFN(r->start),
2738 IOVA_PFN(r->end));
2739 if (!val) {
2740 pr_err("Reserve pci-resource range failed\n");
2741 return -ENOMEM;
2742 }
2743 }
2744 }
2745
2746 return 0;
2747}
2748
Joerg Roedel3a18404c2015-05-28 18:41:45 +02002749int __init amd_iommu_init_api(void)
Joerg Roedel27c2127a2011-05-30 15:56:24 +02002750{
Joerg Roedel460c26d2017-06-02 14:28:01 +02002751 int ret, err = 0;
Joerg Roedel307d5852016-07-05 11:54:04 +02002752
2753 ret = iova_cache_get();
2754 if (ret)
2755 return ret;
Wan Zongshun9a4d3bf52016-04-01 09:06:05 -04002756
Joerg Roedel81cd07b2016-07-07 18:01:10 +02002757 ret = init_reserved_iova_ranges();
2758 if (ret)
2759 return ret;
2760
Wan Zongshun9a4d3bf52016-04-01 09:06:05 -04002761 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2762 if (err)
2763 return err;
2764#ifdef CONFIG_ARM_AMBA
2765 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2766 if (err)
2767 return err;
2768#endif
Wan Zongshun0076cd32016-05-10 09:21:01 -04002769 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2770 if (err)
2771 return err;
Joerg Roedel460c26d2017-06-02 14:28:01 +02002772
Wan Zongshun9a4d3bf52016-04-01 09:06:05 -04002773 return 0;
Joerg Roedelf5325092010-01-22 17:44:35 +01002774}
2775
Joerg Roedel6631ee92008-06-26 21:28:05 +02002776int __init amd_iommu_init_dma_ops(void)
2777{
Tom Lendackyaba2d9a2017-10-06 16:35:40 -05002778 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
Joerg Roedel6631ee92008-06-26 21:28:05 +02002779 iommu_detected = 1;
Joerg Roedel6631ee92008-06-26 21:28:05 +02002780
Joerg Roedel52717822015-07-28 16:58:51 +02002781 /*
2782 * In case we don't initialize SWIOTLB (actually the common case
Tom Lendackyaba2d9a2017-10-06 16:35:40 -05002783 * when AMD IOMMU is enabled and SME is not active), make sure there
2784 * are global dma_ops set as a fall-back for devices not handled by
2785 * this driver (for example non-PCI devices). When SME is active,
2786 * make sure that swiotlb variable remains set so the global dma_ops
2787 * continue to be SWIOTLB.
Joerg Roedel52717822015-07-28 16:58:51 +02002788 */
2789 if (!swiotlb)
Christoph Hellwigfec777c2018-03-19 11:38:15 +01002790 dma_ops = &dma_direct_ops;
Joerg Roedel52717822015-07-28 16:58:51 +02002791
Joerg Roedel62410ee2012-06-12 16:42:43 +02002792 if (amd_iommu_unmap_flush)
2793 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2794 else
2795 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2796
Joerg Roedel6631ee92008-06-26 21:28:05 +02002797 return 0;
Joerg Roedelc5b5da92016-07-06 11:55:37 +02002798
Joerg Roedel6631ee92008-06-26 21:28:05 +02002799}
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002800
2801/*****************************************************************************
2802 *
2803 * The following functions belong to the exported interface of AMD IOMMU
2804 *
2805 * This interface allows access to lower level functions of the IOMMU
2806 * like protection domain handling and assignement of devices to domains
2807 * which is not possible with the dma_ops interface.
2808 *
2809 *****************************************************************************/
2810
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002811static void cleanup_domain(struct protection_domain *domain)
2812{
Joerg Roedel9b29d3c2014-08-05 17:50:15 +02002813 struct iommu_dev_data *entry;
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002814 unsigned long flags;
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002815
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +01002816 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002817
Joerg Roedel9b29d3c2014-08-05 17:50:15 +02002818 while (!list_empty(&domain->dev_list)) {
2819 entry = list_first_entry(&domain->dev_list,
2820 struct iommu_dev_data, list);
Anna-Maria Gleixnerea3fd042018-05-07 14:53:27 +02002821 BUG_ON(!entry->domain);
Joerg Roedel9b29d3c2014-08-05 17:50:15 +02002822 __detach_device(entry);
Joerg Roedel492667d2009-11-27 13:25:47 +01002823 }
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002824
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +01002825 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002826}
2827
Joerg Roedel26508152009-08-26 16:52:40 +02002828static void protection_domain_free(struct protection_domain *domain)
2829{
2830 if (!domain)
2831 return;
2832
Joerg Roedelaeb26f52009-11-20 16:44:01 +01002833 del_domain_from_list(domain);
2834
Joerg Roedel26508152009-08-26 16:52:40 +02002835 if (domain->id)
2836 domain_id_free(domain->id);
2837
2838 kfree(domain);
2839}
2840
Joerg Roedel7a5a5662015-06-30 08:56:11 +02002841static int protection_domain_init(struct protection_domain *domain)
2842{
2843 spin_lock_init(&domain->lock);
2844 mutex_init(&domain->api_lock);
2845 domain->id = domain_id_alloc();
2846 if (!domain->id)
2847 return -ENOMEM;
2848 INIT_LIST_HEAD(&domain->dev_list);
2849
2850 return 0;
2851}
2852
Joerg Roedel26508152009-08-26 16:52:40 +02002853static struct protection_domain *protection_domain_alloc(void)
Joerg Roedelc156e342008-12-02 18:13:27 +01002854{
2855 struct protection_domain *domain;
2856
2857 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2858 if (!domain)
Joerg Roedel26508152009-08-26 16:52:40 +02002859 return NULL;
Joerg Roedelc156e342008-12-02 18:13:27 +01002860
Joerg Roedel7a5a5662015-06-30 08:56:11 +02002861 if (protection_domain_init(domain))
Joerg Roedel26508152009-08-26 16:52:40 +02002862 goto out_err;
2863
Joerg Roedelaeb26f52009-11-20 16:44:01 +01002864 add_domain_to_list(domain);
2865
Joerg Roedel26508152009-08-26 16:52:40 +02002866 return domain;
2867
2868out_err:
2869 kfree(domain);
2870
2871 return NULL;
2872}
2873
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002874static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2875{
2876 struct protection_domain *pdomain;
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002877 struct dma_ops_domain *dma_domain;
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002878
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002879 switch (type) {
2880 case IOMMU_DOMAIN_UNMANAGED:
2881 pdomain = protection_domain_alloc();
2882 if (!pdomain)
2883 return NULL;
2884
2885 pdomain->mode = PAGE_MODE_3_LEVEL;
2886 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2887 if (!pdomain->pt_root) {
2888 protection_domain_free(pdomain);
2889 return NULL;
2890 }
2891
2892 pdomain->domain.geometry.aperture_start = 0;
2893 pdomain->domain.geometry.aperture_end = ~0ULL;
2894 pdomain->domain.geometry.force_aperture = true;
2895
2896 break;
2897 case IOMMU_DOMAIN_DMA:
2898 dma_domain = dma_ops_domain_alloc();
2899 if (!dma_domain) {
2900 pr_err("AMD-Vi: Failed to allocate\n");
2901 return NULL;
2902 }
2903 pdomain = &dma_domain->domain;
2904 break;
Joerg Roedel07f643a32015-05-28 18:41:41 +02002905 case IOMMU_DOMAIN_IDENTITY:
2906 pdomain = protection_domain_alloc();
2907 if (!pdomain)
2908 return NULL;
2909
2910 pdomain->mode = PAGE_MODE_NONE;
2911 break;
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002912 default:
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002913 return NULL;
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002914 }
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002915
2916 return &pdomain->domain;
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002917}
2918
2919static void amd_iommu_domain_free(struct iommu_domain *dom)
Joerg Roedel26508152009-08-26 16:52:40 +02002920{
2921 struct protection_domain *domain;
Joerg Roedelcda70052016-07-07 15:57:04 +02002922 struct dma_ops_domain *dma_dom;
Joerg Roedel98383fc2008-12-02 18:34:12 +01002923
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002924 domain = to_pdomain(dom);
2925
Joerg Roedel98383fc2008-12-02 18:34:12 +01002926 if (domain->dev_cnt > 0)
2927 cleanup_domain(domain);
2928
2929 BUG_ON(domain->dev_cnt != 0);
2930
Joerg Roedelcda70052016-07-07 15:57:04 +02002931 if (!dom)
2932 return;
Joerg Roedel98383fc2008-12-02 18:34:12 +01002933
Joerg Roedelcda70052016-07-07 15:57:04 +02002934 switch (dom->type) {
2935 case IOMMU_DOMAIN_DMA:
Joerg Roedel281e8cc2016-07-07 16:12:02 +02002936 /* Now release the domain */
Joerg Roedelb3311b02016-07-08 13:31:31 +02002937 dma_dom = to_dma_ops_domain(domain);
Joerg Roedelcda70052016-07-07 15:57:04 +02002938 dma_ops_domain_free(dma_dom);
2939 break;
2940 default:
2941 if (domain->mode != PAGE_MODE_NONE)
2942 free_pagetable(domain);
Joerg Roedel52815b72011-11-17 17:24:28 +01002943
Joerg Roedelcda70052016-07-07 15:57:04 +02002944 if (domain->flags & PD_IOMMUV2_MASK)
2945 free_gcr3_table(domain);
2946
2947 protection_domain_free(domain);
2948 break;
2949 }
Joerg Roedel98383fc2008-12-02 18:34:12 +01002950}
2951
Joerg Roedel684f2882008-12-08 12:07:44 +01002952static void amd_iommu_detach_device(struct iommu_domain *dom,
2953 struct device *dev)
2954{
Joerg Roedel657cbb62009-11-23 15:26:46 +01002955 struct iommu_dev_data *dev_data = dev->archdata.iommu;
Joerg Roedel684f2882008-12-08 12:07:44 +01002956 struct amd_iommu *iommu;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002957 int devid;
Joerg Roedel684f2882008-12-08 12:07:44 +01002958
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002959 if (!check_device(dev))
Joerg Roedel684f2882008-12-08 12:07:44 +01002960 return;
2961
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002962 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02002963 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002964 return;
Joerg Roedel684f2882008-12-08 12:07:44 +01002965
Joerg Roedel657cbb62009-11-23 15:26:46 +01002966 if (dev_data->domain != NULL)
Joerg Roedel15898bb2009-11-24 15:39:42 +01002967 detach_device(dev);
Joerg Roedel684f2882008-12-08 12:07:44 +01002968
2969 iommu = amd_iommu_rlookup_table[devid];
2970 if (!iommu)
2971 return;
2972
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05002973#ifdef CONFIG_IRQ_REMAP
2974 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2975 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2976 dev_data->use_vapic = 0;
2977#endif
2978
Joerg Roedel684f2882008-12-08 12:07:44 +01002979 iommu_completion_wait(iommu);
2980}
2981
Joerg Roedel01106062008-12-02 19:34:11 +01002982static int amd_iommu_attach_device(struct iommu_domain *dom,
2983 struct device *dev)
2984{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002985 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel657cbb62009-11-23 15:26:46 +01002986 struct iommu_dev_data *dev_data;
Joerg Roedel01106062008-12-02 19:34:11 +01002987 struct amd_iommu *iommu;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002988 int ret;
Joerg Roedel01106062008-12-02 19:34:11 +01002989
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002990 if (!check_device(dev))
Joerg Roedel01106062008-12-02 19:34:11 +01002991 return -EINVAL;
2992
Joerg Roedel657cbb62009-11-23 15:26:46 +01002993 dev_data = dev->archdata.iommu;
2994
Joerg Roedelf62dda62011-06-09 12:55:35 +02002995 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedel01106062008-12-02 19:34:11 +01002996 if (!iommu)
2997 return -EINVAL;
2998
Joerg Roedel657cbb62009-11-23 15:26:46 +01002999 if (dev_data->domain)
Joerg Roedel15898bb2009-11-24 15:39:42 +01003000 detach_device(dev);
Joerg Roedel01106062008-12-02 19:34:11 +01003001
Joerg Roedel15898bb2009-11-24 15:39:42 +01003002 ret = attach_device(dev, domain);
Joerg Roedel01106062008-12-02 19:34:11 +01003003
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05003004#ifdef CONFIG_IRQ_REMAP
3005 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3006 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3007 dev_data->use_vapic = 1;
3008 else
3009 dev_data->use_vapic = 0;
3010 }
3011#endif
3012
Joerg Roedel01106062008-12-02 19:34:11 +01003013 iommu_completion_wait(iommu);
3014
Joerg Roedel15898bb2009-11-24 15:39:42 +01003015 return ret;
Joerg Roedel01106062008-12-02 19:34:11 +01003016}
3017
Joerg Roedel468e2362010-01-21 16:37:36 +01003018static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003019 phys_addr_t paddr, size_t page_size, int iommu_prot)
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003020{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003021 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003022 int prot = 0;
3023 int ret;
3024
Joerg Roedel132bd682011-11-17 14:18:46 +01003025 if (domain->mode == PAGE_MODE_NONE)
3026 return -EINVAL;
3027
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003028 if (iommu_prot & IOMMU_READ)
3029 prot |= IOMMU_PROT_IR;
3030 if (iommu_prot & IOMMU_WRITE)
3031 prot |= IOMMU_PROT_IW;
3032
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003033 mutex_lock(&domain->api_lock);
Joerg Roedelb911b892016-07-05 14:29:11 +02003034 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003035 mutex_unlock(&domain->api_lock);
3036
Joerg Roedel795e74f72010-05-11 17:40:57 +02003037 return ret;
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003038}
3039
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003040static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3041 size_t page_size)
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003042{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003043 struct protection_domain *domain = to_pdomain(dom);
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003044 size_t unmap_size;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003045
Joerg Roedel132bd682011-11-17 14:18:46 +01003046 if (domain->mode == PAGE_MODE_NONE)
Suravee Suthikulpanitc5611a82018-02-05 05:45:53 -05003047 return 0;
Joerg Roedel132bd682011-11-17 14:18:46 +01003048
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003049 mutex_lock(&domain->api_lock);
Joerg Roedel468e2362010-01-21 16:37:36 +01003050 unmap_size = iommu_unmap_page(domain, iova, page_size);
Joerg Roedel795e74f72010-05-11 17:40:57 +02003051 mutex_unlock(&domain->api_lock);
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003052
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003053 return unmap_size;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003054}
3055
Joerg Roedel645c4c82008-12-02 20:05:50 +01003056static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
Varun Sethibb5547a2013-03-29 01:23:58 +05303057 dma_addr_t iova)
Joerg Roedel645c4c82008-12-02 20:05:50 +01003058{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003059 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel3039ca12015-04-01 14:58:48 +02003060 unsigned long offset_mask, pte_pgsize;
Joerg Roedelf03152b2010-01-21 16:15:24 +01003061 u64 *pte, __pte;
Joerg Roedel645c4c82008-12-02 20:05:50 +01003062
Joerg Roedel132bd682011-11-17 14:18:46 +01003063 if (domain->mode == PAGE_MODE_NONE)
3064 return iova;
3065
Joerg Roedel3039ca12015-04-01 14:58:48 +02003066 pte = fetch_pte(domain, iova, &pte_pgsize);
Joerg Roedel645c4c82008-12-02 20:05:50 +01003067
Joerg Roedela6d41a42009-09-02 17:08:55 +02003068 if (!pte || !IOMMU_PTE_PRESENT(*pte))
Joerg Roedel645c4c82008-12-02 20:05:50 +01003069 return 0;
3070
Joerg Roedelb24b1b62015-04-01 14:58:51 +02003071 offset_mask = pte_pgsize - 1;
Singh, Brijeshb3e9b512018-10-04 21:40:23 +00003072 __pte = __sme_clr(*pte & PM_ADDR_MASK);
Joerg Roedelf03152b2010-01-21 16:15:24 +01003073
Joerg Roedelb24b1b62015-04-01 14:58:51 +02003074 return (__pte & ~offset_mask) | (iova & offset_mask);
Joerg Roedel645c4c82008-12-02 20:05:50 +01003075}
3076
Joerg Roedelab636482014-09-05 10:48:21 +02003077static bool amd_iommu_capable(enum iommu_cap cap)
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003078{
Joerg Roedel80a506b2010-07-27 17:14:24 +02003079 switch (cap) {
3080 case IOMMU_CAP_CACHE_COHERENCY:
Joerg Roedelab636482014-09-05 10:48:21 +02003081 return true;
Joerg Roedelbdddadc2012-07-02 18:38:13 +02003082 case IOMMU_CAP_INTR_REMAP:
Joerg Roedelab636482014-09-05 10:48:21 +02003083 return (irq_remapping_enabled == 1);
Will Deaconcfdeec22014-10-27 11:24:48 +00003084 case IOMMU_CAP_NOEXEC:
3085 return false;
Lu Baolue84b7cc2018-10-08 10:24:19 +08003086 default:
3087 break;
Joerg Roedel80a506b2010-07-27 17:14:24 +02003088 }
3089
Joerg Roedelab636482014-09-05 10:48:21 +02003090 return false;
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003091}
3092
Eric Augere5b52342017-01-19 20:57:47 +00003093static void amd_iommu_get_resv_regions(struct device *dev,
3094 struct list_head *head)
Joerg Roedel35cf2482015-05-28 18:41:37 +02003095{
Eric Auger4397f322017-01-19 20:57:54 +00003096 struct iommu_resv_region *region;
Joerg Roedel35cf2482015-05-28 18:41:37 +02003097 struct unity_map_entry *entry;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04003098 int devid;
Joerg Roedel35cf2482015-05-28 18:41:37 +02003099
3100 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02003101 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04003102 return;
Joerg Roedel35cf2482015-05-28 18:41:37 +02003103
3104 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
Eric Auger4397f322017-01-19 20:57:54 +00003105 size_t length;
3106 int prot = 0;
Joerg Roedel35cf2482015-05-28 18:41:37 +02003107
3108 if (devid < entry->devid_start || devid > entry->devid_end)
3109 continue;
3110
Eric Auger4397f322017-01-19 20:57:54 +00003111 length = entry->address_end - entry->address_start;
3112 if (entry->prot & IOMMU_PROT_IR)
3113 prot |= IOMMU_READ;
3114 if (entry->prot & IOMMU_PROT_IW)
3115 prot |= IOMMU_WRITE;
3116
3117 region = iommu_alloc_resv_region(entry->address_start,
3118 length, prot,
3119 IOMMU_RESV_DIRECT);
Joerg Roedel35cf2482015-05-28 18:41:37 +02003120 if (!region) {
3121 pr_err("Out of memory allocating dm-regions for %s\n",
3122 dev_name(dev));
3123 return;
3124 }
Joerg Roedel35cf2482015-05-28 18:41:37 +02003125 list_add_tail(&region->list, head);
3126 }
Eric Auger4397f322017-01-19 20:57:54 +00003127
3128 region = iommu_alloc_resv_region(MSI_RANGE_START,
3129 MSI_RANGE_END - MSI_RANGE_START + 1,
Robin Murphy9d3a4de2017-03-16 17:00:16 +00003130 0, IOMMU_RESV_MSI);
Eric Auger4397f322017-01-19 20:57:54 +00003131 if (!region)
3132 return;
3133 list_add_tail(&region->list, head);
3134
3135 region = iommu_alloc_resv_region(HT_RANGE_START,
3136 HT_RANGE_END - HT_RANGE_START + 1,
3137 0, IOMMU_RESV_RESERVED);
3138 if (!region)
3139 return;
3140 list_add_tail(&region->list, head);
Joerg Roedel35cf2482015-05-28 18:41:37 +02003141}
3142
Eric Augere5b52342017-01-19 20:57:47 +00003143static void amd_iommu_put_resv_regions(struct device *dev,
Joerg Roedel35cf2482015-05-28 18:41:37 +02003144 struct list_head *head)
3145{
Eric Augere5b52342017-01-19 20:57:47 +00003146 struct iommu_resv_region *entry, *next;
Joerg Roedel35cf2482015-05-28 18:41:37 +02003147
3148 list_for_each_entry_safe(entry, next, head, list)
3149 kfree(entry);
3150}
3151
Eric Augere5b52342017-01-19 20:57:47 +00003152static void amd_iommu_apply_resv_region(struct device *dev,
Joerg Roedel8d54d6c2016-07-05 13:32:20 +02003153 struct iommu_domain *domain,
Eric Augere5b52342017-01-19 20:57:47 +00003154 struct iommu_resv_region *region)
Joerg Roedel8d54d6c2016-07-05 13:32:20 +02003155{
Joerg Roedelb3311b02016-07-08 13:31:31 +02003156 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
Joerg Roedel8d54d6c2016-07-05 13:32:20 +02003157 unsigned long start, end;
3158
3159 start = IOVA_PFN(region->start);
Gary R Hookb92b4fb2017-11-03 10:50:34 -06003160 end = IOVA_PFN(region->start + region->length - 1);
Joerg Roedel8d54d6c2016-07-05 13:32:20 +02003161
3162 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3163}
3164
Baoquan Hedf3f7a62017-08-09 16:33:41 +08003165static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3166 struct device *dev)
3167{
3168 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3169 return dev_data->defer_attach;
3170}
3171
Suravee Suthikulpaniteb5ecd12018-02-21 14:19:45 +07003172static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3173{
3174 struct protection_domain *dom = to_pdomain(domain);
3175
3176 domain_flush_tlb_pde(dom);
3177 domain_flush_complete(dom);
3178}
3179
3180static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3181 unsigned long iova, size_t size)
3182{
3183}
3184
Joerg Roedelb0119e82017-02-01 13:23:08 +01003185const struct iommu_ops amd_iommu_ops = {
Joerg Roedelab636482014-09-05 10:48:21 +02003186 .capable = amd_iommu_capable,
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003187 .domain_alloc = amd_iommu_domain_alloc,
3188 .domain_free = amd_iommu_domain_free,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003189 .attach_dev = amd_iommu_attach_device,
3190 .detach_dev = amd_iommu_detach_device,
Joerg Roedel468e2362010-01-21 16:37:36 +01003191 .map = amd_iommu_map,
3192 .unmap = amd_iommu_unmap,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003193 .iova_to_phys = amd_iommu_iova_to_phys,
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02003194 .add_device = amd_iommu_add_device,
3195 .remove_device = amd_iommu_remove_device,
Wan Zongshunb097d112016-04-01 09:06:04 -04003196 .device_group = amd_iommu_device_group,
Eric Augere5b52342017-01-19 20:57:47 +00003197 .get_resv_regions = amd_iommu_get_resv_regions,
3198 .put_resv_regions = amd_iommu_put_resv_regions,
3199 .apply_resv_region = amd_iommu_apply_resv_region,
Baoquan Hedf3f7a62017-08-09 16:33:41 +08003200 .is_attach_deferred = amd_iommu_is_attach_deferred,
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +02003201 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
Suravee Suthikulpaniteb5ecd12018-02-21 14:19:45 +07003202 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3203 .iotlb_range_add = amd_iommu_iotlb_range_add,
3204 .iotlb_sync = amd_iommu_flush_iotlb_all,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003205};
3206
Joerg Roedel0feae532009-08-26 15:26:30 +02003207/*****************************************************************************
3208 *
3209 * The next functions do a basic initialization of IOMMU for pass through
3210 * mode
3211 *
3212 * In passthrough mode the IOMMU is initialized and enabled but not used for
3213 * DMA-API translation.
3214 *
3215 *****************************************************************************/
3216
Joerg Roedel72e1dcc2011-11-10 19:13:51 +01003217/* IOMMUv2 specific functions */
3218int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3219{
3220 return atomic_notifier_chain_register(&ppr_notifier, nb);
3221}
3222EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3223
3224int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3225{
3226 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3227}
3228EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
Joerg Roedel132bd682011-11-17 14:18:46 +01003229
3230void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3231{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003232 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel132bd682011-11-17 14:18:46 +01003233 unsigned long flags;
3234
3235 spin_lock_irqsave(&domain->lock, flags);
3236
3237 /* Update data structure */
3238 domain->mode = PAGE_MODE_NONE;
3239 domain->updated = true;
3240
3241 /* Make changes visible to IOMMUs */
3242 update_domain(domain);
3243
3244 /* Page-table is not visible to IOMMU anymore, so free it */
3245 free_pagetable(domain);
3246
3247 spin_unlock_irqrestore(&domain->lock, flags);
3248}
3249EXPORT_SYMBOL(amd_iommu_domain_direct_map);
Joerg Roedel52815b72011-11-17 17:24:28 +01003250
3251int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3252{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003253 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel52815b72011-11-17 17:24:28 +01003254 unsigned long flags;
3255 int levels, ret;
3256
3257 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3258 return -EINVAL;
3259
3260 /* Number of GCR3 table levels required */
3261 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3262 levels += 1;
3263
3264 if (levels > amd_iommu_max_glx_val)
3265 return -EINVAL;
3266
3267 spin_lock_irqsave(&domain->lock, flags);
3268
3269 /*
3270 * Save us all sanity checks whether devices already in the
3271 * domain support IOMMUv2. Just force that the domain has no
3272 * devices attached when it is switched into IOMMUv2 mode.
3273 */
3274 ret = -EBUSY;
3275 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3276 goto out;
3277
3278 ret = -ENOMEM;
3279 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3280 if (domain->gcr3_tbl == NULL)
3281 goto out;
3282
3283 domain->glx = levels;
3284 domain->flags |= PD_IOMMUV2_MASK;
3285 domain->updated = true;
3286
3287 update_domain(domain);
3288
3289 ret = 0;
3290
3291out:
3292 spin_unlock_irqrestore(&domain->lock, flags);
3293
3294 return ret;
3295}
3296EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003297
3298static int __flush_pasid(struct protection_domain *domain, int pasid,
3299 u64 address, bool size)
3300{
3301 struct iommu_dev_data *dev_data;
3302 struct iommu_cmd cmd;
3303 int i, ret;
3304
3305 if (!(domain->flags & PD_IOMMUV2_MASK))
3306 return -EINVAL;
3307
3308 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3309
3310 /*
3311 * IOMMU TLB needs to be flushed before Device TLB to
3312 * prevent device TLB refill from IOMMU TLB
3313 */
Suravee Suthikulpanit6b9376e2017-02-24 02:48:17 -06003314 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
Joerg Roedel22e266c2011-11-21 15:59:08 +01003315 if (domain->dev_iommu[i] == 0)
3316 continue;
3317
3318 ret = iommu_queue_command(amd_iommus[i], &cmd);
3319 if (ret != 0)
3320 goto out;
3321 }
3322
3323 /* Wait until IOMMU TLB flushes are complete */
3324 domain_flush_complete(domain);
3325
3326 /* Now flush device TLBs */
3327 list_for_each_entry(dev_data, &domain->dev_list, list) {
3328 struct amd_iommu *iommu;
3329 int qdep;
3330
Joerg Roedel1c1cc452015-07-30 11:24:45 +02003331 /*
3332 There might be non-IOMMUv2 capable devices in an IOMMUv2
3333 * domain.
3334 */
3335 if (!dev_data->ats.enabled)
3336 continue;
Joerg Roedel22e266c2011-11-21 15:59:08 +01003337
3338 qdep = dev_data->ats.qdep;
3339 iommu = amd_iommu_rlookup_table[dev_data->devid];
3340
3341 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3342 qdep, address, size);
3343
3344 ret = iommu_queue_command(iommu, &cmd);
3345 if (ret != 0)
3346 goto out;
3347 }
3348
3349 /* Wait until all device TLBs are flushed */
3350 domain_flush_complete(domain);
3351
3352 ret = 0;
3353
3354out:
3355
3356 return ret;
3357}
3358
3359static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3360 u64 address)
3361{
3362 return __flush_pasid(domain, pasid, address, false);
3363}
3364
3365int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3366 u64 address)
3367{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003368 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003369 unsigned long flags;
3370 int ret;
3371
3372 spin_lock_irqsave(&domain->lock, flags);
3373 ret = __amd_iommu_flush_page(domain, pasid, address);
3374 spin_unlock_irqrestore(&domain->lock, flags);
3375
3376 return ret;
3377}
3378EXPORT_SYMBOL(amd_iommu_flush_page);
3379
3380static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3381{
3382 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3383 true);
3384}
3385
3386int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3387{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003388 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003389 unsigned long flags;
3390 int ret;
3391
3392 spin_lock_irqsave(&domain->lock, flags);
3393 ret = __amd_iommu_flush_tlb(domain, pasid);
3394 spin_unlock_irqrestore(&domain->lock, flags);
3395
3396 return ret;
3397}
3398EXPORT_SYMBOL(amd_iommu_flush_tlb);
3399
Joerg Roedelb16137b2011-11-21 16:50:23 +01003400static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3401{
3402 int index;
3403 u64 *pte;
3404
3405 while (true) {
3406
3407 index = (pasid >> (9 * level)) & 0x1ff;
3408 pte = &root[index];
3409
3410 if (level == 0)
3411 break;
3412
3413 if (!(*pte & GCR3_VALID)) {
3414 if (!alloc)
3415 return NULL;
3416
3417 root = (void *)get_zeroed_page(GFP_ATOMIC);
3418 if (root == NULL)
3419 return NULL;
3420
Tom Lendacky2543a782017-07-17 16:10:24 -05003421 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
Joerg Roedelb16137b2011-11-21 16:50:23 +01003422 }
3423
Tom Lendacky2543a782017-07-17 16:10:24 -05003424 root = iommu_phys_to_virt(*pte & PAGE_MASK);
Joerg Roedelb16137b2011-11-21 16:50:23 +01003425
3426 level -= 1;
3427 }
3428
3429 return pte;
3430}
3431
3432static int __set_gcr3(struct protection_domain *domain, int pasid,
3433 unsigned long cr3)
3434{
3435 u64 *pte;
3436
3437 if (domain->mode != PAGE_MODE_NONE)
3438 return -EINVAL;
3439
3440 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3441 if (pte == NULL)
3442 return -ENOMEM;
3443
3444 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3445
3446 return __amd_iommu_flush_tlb(domain, pasid);
3447}
3448
3449static int __clear_gcr3(struct protection_domain *domain, int pasid)
3450{
3451 u64 *pte;
3452
3453 if (domain->mode != PAGE_MODE_NONE)
3454 return -EINVAL;
3455
3456 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3457 if (pte == NULL)
3458 return 0;
3459
3460 *pte = 0;
3461
3462 return __amd_iommu_flush_tlb(domain, pasid);
3463}
3464
3465int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3466 unsigned long cr3)
3467{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003468 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedelb16137b2011-11-21 16:50:23 +01003469 unsigned long flags;
3470 int ret;
3471
3472 spin_lock_irqsave(&domain->lock, flags);
3473 ret = __set_gcr3(domain, pasid, cr3);
3474 spin_unlock_irqrestore(&domain->lock, flags);
3475
3476 return ret;
3477}
3478EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3479
3480int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3481{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003482 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedelb16137b2011-11-21 16:50:23 +01003483 unsigned long flags;
3484 int ret;
3485
3486 spin_lock_irqsave(&domain->lock, flags);
3487 ret = __clear_gcr3(domain, pasid);
3488 spin_unlock_irqrestore(&domain->lock, flags);
3489
3490 return ret;
3491}
3492EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
Joerg Roedelc99afa22011-11-21 18:19:25 +01003493
3494int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3495 int status, int tag)
3496{
3497 struct iommu_dev_data *dev_data;
3498 struct amd_iommu *iommu;
3499 struct iommu_cmd cmd;
3500
3501 dev_data = get_dev_data(&pdev->dev);
3502 iommu = amd_iommu_rlookup_table[dev_data->devid];
3503
3504 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3505 tag, dev_data->pri_tlp);
3506
3507 return iommu_queue_command(iommu, &cmd);
3508}
3509EXPORT_SYMBOL(amd_iommu_complete_ppr);
Joerg Roedelf3572db82011-11-23 12:36:25 +01003510
3511struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3512{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003513 struct protection_domain *pdomain;
Joerg Roedelf3572db82011-11-23 12:36:25 +01003514
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003515 pdomain = get_domain(&pdev->dev);
3516 if (IS_ERR(pdomain))
Joerg Roedelf3572db82011-11-23 12:36:25 +01003517 return NULL;
3518
3519 /* Only return IOMMUv2 domains */
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003520 if (!(pdomain->flags & PD_IOMMUV2_MASK))
Joerg Roedelf3572db82011-11-23 12:36:25 +01003521 return NULL;
3522
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003523 return &pdomain->domain;
Joerg Roedelf3572db82011-11-23 12:36:25 +01003524}
3525EXPORT_SYMBOL(amd_iommu_get_v2_domain);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01003526
3527void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3528{
3529 struct iommu_dev_data *dev_data;
3530
3531 if (!amd_iommu_v2_supported())
3532 return;
3533
3534 dev_data = get_dev_data(&pdev->dev);
3535 dev_data->errata |= (1 << erratum);
3536}
3537EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
Joerg Roedel52efdb82011-12-07 12:01:36 +01003538
3539int amd_iommu_device_info(struct pci_dev *pdev,
3540 struct amd_iommu_device_info *info)
3541{
3542 int max_pasids;
3543 int pos;
3544
3545 if (pdev == NULL || info == NULL)
3546 return -EINVAL;
3547
3548 if (!amd_iommu_v2_supported())
3549 return -EINVAL;
3550
3551 memset(info, 0, sizeof(*info));
3552
Gil Kupfercef74402018-05-10 17:56:02 -05003553 if (!pci_ats_disabled()) {
3554 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3555 if (pos)
3556 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3557 }
Joerg Roedel52efdb82011-12-07 12:01:36 +01003558
3559 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3560 if (pos)
3561 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3562
3563 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3564 if (pos) {
3565 int features;
3566
3567 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3568 max_pasids = min(max_pasids, (1 << 20));
3569
3570 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3571 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3572
3573 features = pci_pasid_features(pdev);
3574 if (features & PCI_PASID_CAP_EXEC)
3575 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3576 if (features & PCI_PASID_CAP_PRIV)
3577 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3578 }
3579
3580 return 0;
3581}
3582EXPORT_SYMBOL(amd_iommu_device_info);
Joerg Roedel2b324502012-06-21 16:29:10 +02003583
3584#ifdef CONFIG_IRQ_REMAP
3585
3586/*****************************************************************************
3587 *
3588 * Interrupt Remapping Implementation
3589 *
3590 *****************************************************************************/
3591
Jiang Liu7c71d302015-04-13 14:11:33 +08003592static struct irq_chip amd_ir_chip;
Arnd Bergmann94c793a2018-04-04 12:56:59 +02003593static DEFINE_SPINLOCK(iommu_table_lock);
Jiang Liu7c71d302015-04-13 14:11:33 +08003594
Joerg Roedel2b324502012-06-21 16:29:10 +02003595static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3596{
3597 u64 dte;
3598
3599 dte = amd_iommu_dev_table[devid].data[2];
3600 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
Tom Lendacky2543a782017-07-17 16:10:24 -05003601 dte |= iommu_virt_to_phys(table->table);
Joerg Roedel2b324502012-06-21 16:29:10 +02003602 dte |= DTE_IRQ_REMAP_INTCTL;
3603 dte |= DTE_IRQ_TABLE_LEN;
3604 dte |= DTE_IRQ_REMAP_ENABLE;
3605
3606 amd_iommu_dev_table[devid].data[2] = dte;
3607}
3608
Scott Wooddf42a042018-02-14 17:36:28 -06003609static struct irq_remap_table *get_irq_table(u16 devid)
3610{
3611 struct irq_remap_table *table;
3612
3613 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3614 "%s: no iommu for devid %x\n", __func__, devid))
3615 return NULL;
3616
3617 table = irq_lookup_table[devid];
3618 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3619 return NULL;
3620
3621 return table;
3622}
3623
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003624static struct irq_remap_table *__alloc_irq_table(void)
3625{
3626 struct irq_remap_table *table;
3627
3628 table = kzalloc(sizeof(*table), GFP_KERNEL);
3629 if (!table)
3630 return NULL;
3631
3632 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3633 if (!table->table) {
3634 kfree(table);
3635 return NULL;
3636 }
3637 raw_spin_lock_init(&table->lock);
3638
3639 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3640 memset(table->table, 0,
3641 MAX_IRQS_PER_TABLE * sizeof(u32));
3642 else
3643 memset(table->table, 0,
3644 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3645 return table;
3646}
3647
Sebastian Andrzej Siewior2fcc1e82018-03-22 16:22:39 +01003648static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3649 struct irq_remap_table *table)
3650{
3651 irq_lookup_table[devid] = table;
3652 set_dte_irq_entry(devid, table);
3653 iommu_flush_dte(iommu, devid);
3654}
3655
Sebastian Andrzej Siewiorfde65dd2018-03-22 16:22:37 +01003656static struct irq_remap_table *alloc_irq_table(u16 devid)
Joerg Roedel2b324502012-06-21 16:29:10 +02003657{
3658 struct irq_remap_table *table = NULL;
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003659 struct irq_remap_table *new_table = NULL;
Joerg Roedel2b324502012-06-21 16:29:10 +02003660 struct amd_iommu *iommu;
3661 unsigned long flags;
3662 u16 alias;
3663
Sebastian Andrzej Siewiorea6166f2018-03-22 16:22:36 +01003664 spin_lock_irqsave(&iommu_table_lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003665
3666 iommu = amd_iommu_rlookup_table[devid];
3667 if (!iommu)
3668 goto out_unlock;
3669
3670 table = irq_lookup_table[devid];
3671 if (table)
Baoquan He09284b92016-09-20 09:05:34 +08003672 goto out_unlock;
Joerg Roedel2b324502012-06-21 16:29:10 +02003673
3674 alias = amd_iommu_alias_table[devid];
3675 table = irq_lookup_table[alias];
3676 if (table) {
Sebastian Andrzej Siewior2fcc1e82018-03-22 16:22:39 +01003677 set_remap_table_entry(iommu, devid, table);
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003678 goto out_wait;
Joerg Roedel2b324502012-06-21 16:29:10 +02003679 }
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003680 spin_unlock_irqrestore(&iommu_table_lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003681
3682 /* Nothing there yet, allocate new irq remapping table */
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003683 new_table = __alloc_irq_table();
3684 if (!new_table)
3685 return NULL;
3686
3687 spin_lock_irqsave(&iommu_table_lock, flags);
3688
3689 table = irq_lookup_table[devid];
3690 if (table)
Baoquan He09284b92016-09-20 09:05:34 +08003691 goto out_unlock;
Joerg Roedel2b324502012-06-21 16:29:10 +02003692
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003693 table = irq_lookup_table[alias];
3694 if (table) {
3695 set_remap_table_entry(iommu, devid, table);
3696 goto out_wait;
Joerg Roedel2b324502012-06-21 16:29:10 +02003697 }
3698
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003699 table = new_table;
3700 new_table = NULL;
Joerg Roedel2b324502012-06-21 16:29:10 +02003701
Sebastian Andrzej Siewior2fcc1e82018-03-22 16:22:39 +01003702 set_remap_table_entry(iommu, devid, table);
3703 if (devid != alias)
3704 set_remap_table_entry(iommu, alias, table);
Joerg Roedel2b324502012-06-21 16:29:10 +02003705
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003706out_wait:
Joerg Roedel2b324502012-06-21 16:29:10 +02003707 iommu_completion_wait(iommu);
3708
3709out_unlock:
Sebastian Andrzej Siewiorea6166f2018-03-22 16:22:36 +01003710 spin_unlock_irqrestore(&iommu_table_lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003711
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003712 if (new_table) {
3713 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3714 kfree(new_table);
3715 }
Joerg Roedel2b324502012-06-21 16:29:10 +02003716 return table;
3717}
3718
Joerg Roedel37946d92017-10-06 12:16:39 +02003719static int alloc_irq_index(u16 devid, int count, bool align)
Joerg Roedel2b324502012-06-21 16:29:10 +02003720{
3721 struct irq_remap_table *table;
Joerg Roedel37946d92017-10-06 12:16:39 +02003722 int index, c, alignment = 1;
Joerg Roedel2b324502012-06-21 16:29:10 +02003723 unsigned long flags;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05003724 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3725
3726 if (!iommu)
3727 return -ENODEV;
Joerg Roedel2b324502012-06-21 16:29:10 +02003728
Sebastian Andrzej Siewiorfde65dd2018-03-22 16:22:37 +01003729 table = alloc_irq_table(devid);
Joerg Roedel2b324502012-06-21 16:29:10 +02003730 if (!table)
3731 return -ENODEV;
3732
Joerg Roedel37946d92017-10-06 12:16:39 +02003733 if (align)
3734 alignment = roundup_pow_of_two(count);
3735
Scott Wood27790392018-01-21 03:28:54 -06003736 raw_spin_lock_irqsave(&table->lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003737
3738 /* Scan table for free entries */
Joerg Roedel37946d92017-10-06 12:16:39 +02003739 for (index = ALIGN(table->min_index, alignment), c = 0;
Alex Williamson07d1c912017-11-03 10:50:31 -06003740 index < MAX_IRQS_PER_TABLE;) {
Joerg Roedel37946d92017-10-06 12:16:39 +02003741 if (!iommu->irte_ops->is_allocated(table, index)) {
Joerg Roedel2b324502012-06-21 16:29:10 +02003742 c += 1;
Joerg Roedel37946d92017-10-06 12:16:39 +02003743 } else {
3744 c = 0;
Alex Williamson07d1c912017-11-03 10:50:31 -06003745 index = ALIGN(index + 1, alignment);
Joerg Roedel37946d92017-10-06 12:16:39 +02003746 continue;
3747 }
Joerg Roedel2b324502012-06-21 16:29:10 +02003748
3749 if (c == count) {
Joerg Roedel2b324502012-06-21 16:29:10 +02003750 for (; c != 0; --c)
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05003751 iommu->irte_ops->set_allocated(table, index - c + 1);
Joerg Roedel2b324502012-06-21 16:29:10 +02003752
3753 index -= count - 1;
Joerg Roedel2b324502012-06-21 16:29:10 +02003754 goto out;
3755 }
Alex Williamson07d1c912017-11-03 10:50:31 -06003756
3757 index++;
Joerg Roedel2b324502012-06-21 16:29:10 +02003758 }
3759
3760 index = -ENOSPC;
3761
3762out:
Scott Wood27790392018-01-21 03:28:54 -06003763 raw_spin_unlock_irqrestore(&table->lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003764
3765 return index;
3766}
3767
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05003768static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3769 struct amd_ir_data *data)
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003770{
3771 struct irq_remap_table *table;
3772 struct amd_iommu *iommu;
3773 unsigned long flags;
3774 struct irte_ga *entry;
3775
3776 iommu = amd_iommu_rlookup_table[devid];
3777 if (iommu == NULL)
3778 return -EINVAL;
3779
Scott Wooddf42a042018-02-14 17:36:28 -06003780 table = get_irq_table(devid);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003781 if (!table)
3782 return -ENOMEM;
3783
Scott Wood27790392018-01-21 03:28:54 -06003784 raw_spin_lock_irqsave(&table->lock, flags);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003785
3786 entry = (struct irte_ga *)table->table;
3787 entry = &entry[index];
3788 entry->lo.fields_remap.valid = 0;
3789 entry->hi.val = irte->hi.val;
3790 entry->lo.val = irte->lo.val;
3791 entry->lo.fields_remap.valid = 1;
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05003792 if (data)
3793 data->ref = entry;
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003794
Scott Wood27790392018-01-21 03:28:54 -06003795 raw_spin_unlock_irqrestore(&table->lock, flags);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003796
3797 iommu_flush_irt(iommu, devid);
3798 iommu_completion_wait(iommu);
3799
3800 return 0;
3801}
3802
3803static int modify_irte(u16 devid, int index, union irte *irte)
Joerg Roedel2b324502012-06-21 16:29:10 +02003804{
3805 struct irq_remap_table *table;
3806 struct amd_iommu *iommu;
3807 unsigned long flags;
3808
3809 iommu = amd_iommu_rlookup_table[devid];
3810 if (iommu == NULL)
3811 return -EINVAL;
3812
Scott Wooddf42a042018-02-14 17:36:28 -06003813 table = get_irq_table(devid);
Joerg Roedel2b324502012-06-21 16:29:10 +02003814 if (!table)
3815 return -ENOMEM;
3816
Scott Wood27790392018-01-21 03:28:54 -06003817 raw_spin_lock_irqsave(&table->lock, flags);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003818 table->table[index] = irte->val;
Scott Wood27790392018-01-21 03:28:54 -06003819 raw_spin_unlock_irqrestore(&table->lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003820
3821 iommu_flush_irt(iommu, devid);
3822 iommu_completion_wait(iommu);
3823
3824 return 0;
3825}
3826
3827static void free_irte(u16 devid, int index)
3828{
3829 struct irq_remap_table *table;
3830 struct amd_iommu *iommu;
3831 unsigned long flags;
3832
3833 iommu = amd_iommu_rlookup_table[devid];
3834 if (iommu == NULL)
3835 return;
3836
Scott Wooddf42a042018-02-14 17:36:28 -06003837 table = get_irq_table(devid);
Joerg Roedel2b324502012-06-21 16:29:10 +02003838 if (!table)
3839 return;
3840
Scott Wood27790392018-01-21 03:28:54 -06003841 raw_spin_lock_irqsave(&table->lock, flags);
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05003842 iommu->irte_ops->clear_allocated(table, index);
Scott Wood27790392018-01-21 03:28:54 -06003843 raw_spin_unlock_irqrestore(&table->lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003844
3845 iommu_flush_irt(iommu, devid);
3846 iommu_completion_wait(iommu);
3847}
3848
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003849static void irte_prepare(void *entry,
3850 u32 delivery_mode, u32 dest_mode,
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05003851 u8 vector, u32 dest_apicid, int devid)
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003852{
3853 union irte *irte = (union irte *) entry;
3854
3855 irte->val = 0;
3856 irte->fields.vector = vector;
3857 irte->fields.int_type = delivery_mode;
3858 irte->fields.destination = dest_apicid;
3859 irte->fields.dm = dest_mode;
3860 irte->fields.valid = 1;
3861}
3862
3863static void irte_ga_prepare(void *entry,
3864 u32 delivery_mode, u32 dest_mode,
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05003865 u8 vector, u32 dest_apicid, int devid)
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003866{
3867 struct irte_ga *irte = (struct irte_ga *) entry;
3868
3869 irte->lo.val = 0;
3870 irte->hi.val = 0;
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003871 irte->lo.fields_remap.int_type = delivery_mode;
3872 irte->lo.fields_remap.dm = dest_mode;
3873 irte->hi.fields.vector = vector;
Suravee Suthikulpanit90fcffd2018-06-27 10:31:22 -05003874 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3875 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003876 irte->lo.fields_remap.valid = 1;
3877}
3878
3879static void irte_activate(void *entry, u16 devid, u16 index)
3880{
3881 union irte *irte = (union irte *) entry;
3882
3883 irte->fields.valid = 1;
3884 modify_irte(devid, index, irte);
3885}
3886
3887static void irte_ga_activate(void *entry, u16 devid, u16 index)
3888{
3889 struct irte_ga *irte = (struct irte_ga *) entry;
3890
3891 irte->lo.fields_remap.valid = 1;
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05003892 modify_irte_ga(devid, index, irte, NULL);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003893}
3894
3895static void irte_deactivate(void *entry, u16 devid, u16 index)
3896{
3897 union irte *irte = (union irte *) entry;
3898
3899 irte->fields.valid = 0;
3900 modify_irte(devid, index, irte);
3901}
3902
3903static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3904{
3905 struct irte_ga *irte = (struct irte_ga *) entry;
3906
3907 irte->lo.fields_remap.valid = 0;
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05003908 modify_irte_ga(devid, index, irte, NULL);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003909}
3910
3911static void irte_set_affinity(void *entry, u16 devid, u16 index,
3912 u8 vector, u32 dest_apicid)
3913{
3914 union irte *irte = (union irte *) entry;
3915
3916 irte->fields.vector = vector;
3917 irte->fields.destination = dest_apicid;
3918 modify_irte(devid, index, irte);
3919}
3920
3921static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3922 u8 vector, u32 dest_apicid)
3923{
3924 struct irte_ga *irte = (struct irte_ga *) entry;
3925
Scott Wood01ee04b2018-01-28 14:22:19 -06003926 if (!irte->lo.fields_remap.guest_mode) {
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05003927 irte->hi.fields.vector = vector;
Suravee Suthikulpanit90fcffd2018-06-27 10:31:22 -05003928 irte->lo.fields_remap.destination =
3929 APICID_TO_IRTE_DEST_LO(dest_apicid);
3930 irte->hi.fields.destination =
3931 APICID_TO_IRTE_DEST_HI(dest_apicid);
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05003932 modify_irte_ga(devid, index, irte, NULL);
3933 }
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003934}
3935
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05003936#define IRTE_ALLOCATED (~1U)
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003937static void irte_set_allocated(struct irq_remap_table *table, int index)
3938{
3939 table->table[index] = IRTE_ALLOCATED;
3940}
3941
3942static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3943{
3944 struct irte_ga *ptr = (struct irte_ga *)table->table;
3945 struct irte_ga *irte = &ptr[index];
3946
3947 memset(&irte->lo.val, 0, sizeof(u64));
3948 memset(&irte->hi.val, 0, sizeof(u64));
3949 irte->hi.fields.vector = 0xff;
3950}
3951
3952static bool irte_is_allocated(struct irq_remap_table *table, int index)
3953{
3954 union irte *ptr = (union irte *)table->table;
3955 union irte *irte = &ptr[index];
3956
3957 return irte->val != 0;
3958}
3959
3960static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3961{
3962 struct irte_ga *ptr = (struct irte_ga *)table->table;
3963 struct irte_ga *irte = &ptr[index];
3964
3965 return irte->hi.fields.vector != 0;
3966}
3967
3968static void irte_clear_allocated(struct irq_remap_table *table, int index)
3969{
3970 table->table[index] = 0;
3971}
3972
3973static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3974{
3975 struct irte_ga *ptr = (struct irte_ga *)table->table;
3976 struct irte_ga *irte = &ptr[index];
3977
3978 memset(&irte->lo.val, 0, sizeof(u64));
3979 memset(&irte->hi.val, 0, sizeof(u64));
3980}
3981
Jiang Liu7c71d302015-04-13 14:11:33 +08003982static int get_devid(struct irq_alloc_info *info)
Joerg Roedel5527de72012-06-26 11:17:32 +02003983{
Jiang Liu7c71d302015-04-13 14:11:33 +08003984 int devid = -1;
Joerg Roedel5527de72012-06-26 11:17:32 +02003985
Jiang Liu7c71d302015-04-13 14:11:33 +08003986 switch (info->type) {
3987 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3988 devid = get_ioapic_devid(info->ioapic_id);
3989 break;
3990 case X86_IRQ_ALLOC_TYPE_HPET:
3991 devid = get_hpet_devid(info->hpet_id);
3992 break;
3993 case X86_IRQ_ALLOC_TYPE_MSI:
3994 case X86_IRQ_ALLOC_TYPE_MSIX:
3995 devid = get_device_id(&info->msi_dev->dev);
3996 break;
3997 default:
3998 BUG_ON(1);
3999 break;
Joerg Roedel5527de72012-06-26 11:17:32 +02004000 }
4001
Jiang Liu7c71d302015-04-13 14:11:33 +08004002 return devid;
Joerg Roedel5527de72012-06-26 11:17:32 +02004003}
4004
Jiang Liu7c71d302015-04-13 14:11:33 +08004005static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
Joerg Roedel5527de72012-06-26 11:17:32 +02004006{
Jiang Liu7c71d302015-04-13 14:11:33 +08004007 struct amd_iommu *iommu;
4008 int devid;
Joerg Roedel5527de72012-06-26 11:17:32 +02004009
Jiang Liu7c71d302015-04-13 14:11:33 +08004010 if (!info)
4011 return NULL;
Joerg Roedel5527de72012-06-26 11:17:32 +02004012
Jiang Liu7c71d302015-04-13 14:11:33 +08004013 devid = get_devid(info);
4014 if (devid >= 0) {
4015 iommu = amd_iommu_rlookup_table[devid];
4016 if (iommu)
4017 return iommu->ir_domain;
4018 }
Joerg Roedel5527de72012-06-26 11:17:32 +02004019
Jiang Liu7c71d302015-04-13 14:11:33 +08004020 return NULL;
Joerg Roedel5527de72012-06-26 11:17:32 +02004021}
4022
Jiang Liu7c71d302015-04-13 14:11:33 +08004023static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004024{
Jiang Liu7c71d302015-04-13 14:11:33 +08004025 struct amd_iommu *iommu;
4026 int devid;
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004027
Jiang Liu7c71d302015-04-13 14:11:33 +08004028 if (!info)
4029 return NULL;
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004030
Jiang Liu7c71d302015-04-13 14:11:33 +08004031 switch (info->type) {
4032 case X86_IRQ_ALLOC_TYPE_MSI:
4033 case X86_IRQ_ALLOC_TYPE_MSIX:
4034 devid = get_device_id(&info->msi_dev->dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02004035 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04004036 return NULL;
4037
Dan Carpenter1fb260b2016-01-07 12:36:06 +03004038 iommu = amd_iommu_rlookup_table[devid];
4039 if (iommu)
4040 return iommu->msi_domain;
Jiang Liu7c71d302015-04-13 14:11:33 +08004041 break;
4042 default:
4043 break;
4044 }
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004045
Jiang Liu7c71d302015-04-13 14:11:33 +08004046 return NULL;
Joerg Roedeld9761952012-06-26 16:00:08 +02004047}
4048
Joerg Roedel6b474b82012-06-26 16:46:04 +02004049struct irq_remap_ops amd_iommu_irq_ops = {
Joerg Roedel6b474b82012-06-26 16:46:04 +02004050 .prepare = amd_iommu_prepare,
4051 .enable = amd_iommu_enable,
4052 .disable = amd_iommu_disable,
4053 .reenable = amd_iommu_reenable,
4054 .enable_faulting = amd_iommu_enable_faulting,
Jiang Liu7c71d302015-04-13 14:11:33 +08004055 .get_ir_irq_domain = get_ir_irq_domain,
4056 .get_irq_domain = get_irq_domain,
Joerg Roedel6b474b82012-06-26 16:46:04 +02004057};
Jiang Liu7c71d302015-04-13 14:11:33 +08004058
4059static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4060 struct irq_cfg *irq_cfg,
4061 struct irq_alloc_info *info,
4062 int devid, int index, int sub_handle)
4063{
4064 struct irq_2_irte *irte_info = &data->irq_2_irte;
4065 struct msi_msg *msg = &data->msi_entry;
Jiang Liu7c71d302015-04-13 14:11:33 +08004066 struct IO_APIC_route_entry *entry;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004067 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4068
4069 if (!iommu)
4070 return;
Jiang Liu7c71d302015-04-13 14:11:33 +08004071
Jiang Liu7c71d302015-04-13 14:11:33 +08004072 data->irq_2_irte.devid = devid;
4073 data->irq_2_irte.index = index + sub_handle;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004074 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4075 apic->irq_dest_mode, irq_cfg->vector,
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05004076 irq_cfg->dest_apicid, devid);
Jiang Liu7c71d302015-04-13 14:11:33 +08004077
4078 switch (info->type) {
4079 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4080 /* Setup IOAPIC entry */
4081 entry = info->ioapic_entry;
4082 info->ioapic_entry = NULL;
4083 memset(entry, 0, sizeof(*entry));
4084 entry->vector = index;
4085 entry->mask = 0;
4086 entry->trigger = info->ioapic_trigger;
4087 entry->polarity = info->ioapic_polarity;
4088 /* Mask level triggered irqs. */
4089 if (info->ioapic_trigger)
4090 entry->mask = 1;
4091 break;
4092
4093 case X86_IRQ_ALLOC_TYPE_HPET:
4094 case X86_IRQ_ALLOC_TYPE_MSI:
4095 case X86_IRQ_ALLOC_TYPE_MSIX:
4096 msg->address_hi = MSI_ADDR_BASE_HI;
4097 msg->address_lo = MSI_ADDR_BASE_LO;
4098 msg->data = irte_info->index;
4099 break;
4100
4101 default:
4102 BUG_ON(1);
4103 break;
4104 }
4105}
4106
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05004107struct amd_irte_ops irte_32_ops = {
4108 .prepare = irte_prepare,
4109 .activate = irte_activate,
4110 .deactivate = irte_deactivate,
4111 .set_affinity = irte_set_affinity,
4112 .set_allocated = irte_set_allocated,
4113 .is_allocated = irte_is_allocated,
4114 .clear_allocated = irte_clear_allocated,
4115};
4116
4117struct amd_irte_ops irte_128_ops = {
4118 .prepare = irte_ga_prepare,
4119 .activate = irte_ga_activate,
4120 .deactivate = irte_ga_deactivate,
4121 .set_affinity = irte_ga_set_affinity,
4122 .set_allocated = irte_ga_set_allocated,
4123 .is_allocated = irte_ga_is_allocated,
4124 .clear_allocated = irte_ga_clear_allocated,
4125};
4126
Jiang Liu7c71d302015-04-13 14:11:33 +08004127static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4128 unsigned int nr_irqs, void *arg)
4129{
4130 struct irq_alloc_info *info = arg;
4131 struct irq_data *irq_data;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004132 struct amd_ir_data *data = NULL;
Jiang Liu7c71d302015-04-13 14:11:33 +08004133 struct irq_cfg *cfg;
4134 int i, ret, devid;
Sebastian Andrzej Siewior29d049b2018-03-22 16:22:42 +01004135 int index;
Jiang Liu7c71d302015-04-13 14:11:33 +08004136
4137 if (!info)
4138 return -EINVAL;
4139 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4140 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4141 return -EINVAL;
4142
4143 /*
4144 * With IRQ remapping enabled, don't need contiguous CPU vectors
4145 * to support multiple MSI interrupts.
4146 */
4147 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4148 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4149
4150 devid = get_devid(info);
4151 if (devid < 0)
4152 return -EINVAL;
4153
4154 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4155 if (ret < 0)
4156 return ret;
4157
Jiang Liu7c71d302015-04-13 14:11:33 +08004158 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
Sebastian Andrzej Siewiorfde65dd2018-03-22 16:22:37 +01004159 struct irq_remap_table *table;
4160 struct amd_iommu *iommu;
4161
4162 table = alloc_irq_table(devid);
4163 if (table) {
4164 if (!table->min_index) {
4165 /*
4166 * Keep the first 32 indexes free for IOAPIC
4167 * interrupts.
4168 */
4169 table->min_index = 32;
4170 iommu = amd_iommu_rlookup_table[devid];
4171 for (i = 0; i < 32; ++i)
4172 iommu->irte_ops->set_allocated(table, i);
4173 }
4174 WARN_ON(table->min_index != 32);
Jiang Liu7c71d302015-04-13 14:11:33 +08004175 index = info->ioapic_pin;
Sebastian Andrzej Siewiorfde65dd2018-03-22 16:22:37 +01004176 } else {
Sebastian Andrzej Siewior29d049b2018-03-22 16:22:42 +01004177 index = -ENOMEM;
Sebastian Andrzej Siewiorfde65dd2018-03-22 16:22:37 +01004178 }
Jiang Liu7c71d302015-04-13 14:11:33 +08004179 } else {
Joerg Roedel53b9ec32017-10-06 12:22:06 +02004180 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4181
4182 index = alloc_irq_index(devid, nr_irqs, align);
Jiang Liu7c71d302015-04-13 14:11:33 +08004183 }
4184 if (index < 0) {
4185 pr_warn("Failed to allocate IRTE\n");
Wei Yongjun517abe42016-07-28 02:10:26 +00004186 ret = index;
Jiang Liu7c71d302015-04-13 14:11:33 +08004187 goto out_free_parent;
4188 }
4189
4190 for (i = 0; i < nr_irqs; i++) {
4191 irq_data = irq_domain_get_irq_data(domain, virq + i);
4192 cfg = irqd_cfg(irq_data);
4193 if (!irq_data || !cfg) {
4194 ret = -EINVAL;
4195 goto out_free_data;
4196 }
4197
Joerg Roedela130e692015-08-13 11:07:25 +02004198 ret = -ENOMEM;
4199 data = kzalloc(sizeof(*data), GFP_KERNEL);
4200 if (!data)
4201 goto out_free_data;
4202
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004203 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4204 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4205 else
4206 data->entry = kzalloc(sizeof(struct irte_ga),
4207 GFP_KERNEL);
4208 if (!data->entry) {
4209 kfree(data);
4210 goto out_free_data;
4211 }
4212
Jiang Liu7c71d302015-04-13 14:11:33 +08004213 irq_data->hwirq = (devid << 16) + i;
4214 irq_data->chip_data = data;
4215 irq_data->chip = &amd_ir_chip;
4216 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4217 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4218 }
Joerg Roedela130e692015-08-13 11:07:25 +02004219
Jiang Liu7c71d302015-04-13 14:11:33 +08004220 return 0;
4221
4222out_free_data:
4223 for (i--; i >= 0; i--) {
4224 irq_data = irq_domain_get_irq_data(domain, virq + i);
4225 if (irq_data)
4226 kfree(irq_data->chip_data);
4227 }
4228 for (i = 0; i < nr_irqs; i++)
4229 free_irte(devid, index + i);
4230out_free_parent:
4231 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4232 return ret;
4233}
4234
4235static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4236 unsigned int nr_irqs)
4237{
4238 struct irq_2_irte *irte_info;
4239 struct irq_data *irq_data;
4240 struct amd_ir_data *data;
4241 int i;
4242
4243 for (i = 0; i < nr_irqs; i++) {
4244 irq_data = irq_domain_get_irq_data(domain, virq + i);
4245 if (irq_data && irq_data->chip_data) {
4246 data = irq_data->chip_data;
4247 irte_info = &data->irq_2_irte;
4248 free_irte(irte_info->devid, irte_info->index);
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004249 kfree(data->entry);
Jiang Liu7c71d302015-04-13 14:11:33 +08004250 kfree(data);
4251 }
4252 }
4253 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4254}
4255
Thomas Gleixner5ba204a2017-09-13 23:29:48 +02004256static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4257 struct amd_ir_data *ir_data,
4258 struct irq_2_irte *irte_info,
4259 struct irq_cfg *cfg);
4260
Thomas Gleixner72491642017-09-13 23:29:10 +02004261static int irq_remapping_activate(struct irq_domain *domain,
Thomas Gleixner702cb0a2017-12-29 16:59:06 +01004262 struct irq_data *irq_data, bool reserve)
Jiang Liu7c71d302015-04-13 14:11:33 +08004263{
4264 struct amd_ir_data *data = irq_data->chip_data;
4265 struct irq_2_irte *irte_info = &data->irq_2_irte;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004266 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
Thomas Gleixner5ba204a2017-09-13 23:29:48 +02004267 struct irq_cfg *cfg = irqd_cfg(irq_data);
Jiang Liu7c71d302015-04-13 14:11:33 +08004268
Thomas Gleixner5ba204a2017-09-13 23:29:48 +02004269 if (!iommu)
4270 return 0;
4271
4272 iommu->irte_ops->activate(data->entry, irte_info->devid,
4273 irte_info->index);
4274 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
Thomas Gleixner72491642017-09-13 23:29:10 +02004275 return 0;
Jiang Liu7c71d302015-04-13 14:11:33 +08004276}
4277
4278static void irq_remapping_deactivate(struct irq_domain *domain,
4279 struct irq_data *irq_data)
4280{
4281 struct amd_ir_data *data = irq_data->chip_data;
4282 struct irq_2_irte *irte_info = &data->irq_2_irte;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004283 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
Jiang Liu7c71d302015-04-13 14:11:33 +08004284
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004285 if (iommu)
4286 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4287 irte_info->index);
Jiang Liu7c71d302015-04-13 14:11:33 +08004288}
4289
Tobias Klausere2f9d452017-05-24 16:31:16 +02004290static const struct irq_domain_ops amd_ir_domain_ops = {
Jiang Liu7c71d302015-04-13 14:11:33 +08004291 .alloc = irq_remapping_alloc,
4292 .free = irq_remapping_free,
4293 .activate = irq_remapping_activate,
4294 .deactivate = irq_remapping_deactivate,
4295};
4296
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05004297static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4298{
4299 struct amd_iommu *iommu;
4300 struct amd_iommu_pi_data *pi_data = vcpu_info;
4301 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4302 struct amd_ir_data *ir_data = data->chip_data;
4303 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4304 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05004305 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4306
4307 /* Note:
4308 * This device has never been set up for guest mode.
4309 * we should not modify the IRTE
4310 */
4311 if (!dev_data || !dev_data->use_vapic)
4312 return 0;
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05004313
4314 pi_data->ir_data = ir_data;
4315
4316 /* Note:
4317 * SVM tries to set up for VAPIC mode, but we are in
4318 * legacy mode. So, we force legacy mode instead.
4319 */
4320 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4321 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4322 __func__);
4323 pi_data->is_guest_mode = false;
4324 }
4325
4326 iommu = amd_iommu_rlookup_table[irte_info->devid];
4327 if (iommu == NULL)
4328 return -EINVAL;
4329
4330 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4331 if (pi_data->is_guest_mode) {
4332 /* Setting */
4333 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4334 irte->hi.fields.vector = vcpu_pi_info->vector;
Suravee Suthikulpanitefe6f242017-07-05 21:29:59 -05004335 irte->lo.fields_vapic.ga_log_intr = 1;
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05004336 irte->lo.fields_vapic.guest_mode = 1;
4337 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4338
4339 ir_data->cached_ga_tag = pi_data->ga_tag;
4340 } else {
4341 /* Un-Setting */
4342 struct irq_cfg *cfg = irqd_cfg(data);
4343
4344 irte->hi.val = 0;
4345 irte->lo.val = 0;
4346 irte->hi.fields.vector = cfg->vector;
4347 irte->lo.fields_remap.guest_mode = 0;
Suravee Suthikulpanit90fcffd2018-06-27 10:31:22 -05004348 irte->lo.fields_remap.destination =
4349 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4350 irte->hi.fields.destination =
4351 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05004352 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4353 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4354
4355 /*
4356 * This communicates the ga_tag back to the caller
4357 * so that it can do all the necessary clean up.
4358 */
4359 ir_data->cached_ga_tag = 0;
4360 }
4361
4362 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4363}
4364
Thomas Gleixner5ba204a2017-09-13 23:29:48 +02004365
4366static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4367 struct amd_ir_data *ir_data,
4368 struct irq_2_irte *irte_info,
4369 struct irq_cfg *cfg)
4370{
4371
4372 /*
4373 * Atomically updates the IRTE with the new destination, vector
4374 * and flushes the interrupt entry cache.
4375 */
4376 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4377 irte_info->index, cfg->vector,
4378 cfg->dest_apicid);
4379}
4380
Jiang Liu7c71d302015-04-13 14:11:33 +08004381static int amd_ir_set_affinity(struct irq_data *data,
4382 const struct cpumask *mask, bool force)
4383{
4384 struct amd_ir_data *ir_data = data->chip_data;
4385 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4386 struct irq_cfg *cfg = irqd_cfg(data);
4387 struct irq_data *parent = data->parent_data;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004388 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
Jiang Liu7c71d302015-04-13 14:11:33 +08004389 int ret;
4390
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004391 if (!iommu)
4392 return -ENODEV;
4393
Jiang Liu7c71d302015-04-13 14:11:33 +08004394 ret = parent->chip->irq_set_affinity(parent, mask, force);
4395 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4396 return ret;
4397
Thomas Gleixner5ba204a2017-09-13 23:29:48 +02004398 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
Jiang Liu7c71d302015-04-13 14:11:33 +08004399 /*
4400 * After this point, all the interrupts will start arriving
4401 * at the new destination. So, time to cleanup the previous
4402 * vector allocation.
4403 */
Jiang Liuc6c20022015-04-14 10:30:02 +08004404 send_cleanup_vector(cfg);
Jiang Liu7c71d302015-04-13 14:11:33 +08004405
4406 return IRQ_SET_MASK_OK_DONE;
4407}
4408
4409static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4410{
4411 struct amd_ir_data *ir_data = irq_data->chip_data;
4412
4413 *msg = ir_data->msi_entry;
4414}
4415
4416static struct irq_chip amd_ir_chip = {
Thomas Gleixner290be192017-06-20 01:37:02 +02004417 .name = "AMD-IR",
Thomas Gleixner8a2b7d12018-06-04 17:33:56 +02004418 .irq_ack = apic_ack_irq,
Thomas Gleixner290be192017-06-20 01:37:02 +02004419 .irq_set_affinity = amd_ir_set_affinity,
4420 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4421 .irq_compose_msi_msg = ir_compose_msi_msg,
Jiang Liu7c71d302015-04-13 14:11:33 +08004422};
4423
4424int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4425{
Thomas Gleixner3e49a812017-06-20 01:37:12 +02004426 struct fwnode_handle *fn;
4427
4428 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4429 if (!fn)
4430 return -ENOMEM;
4431 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4432 irq_domain_free_fwnode(fn);
Jiang Liu7c71d302015-04-13 14:11:33 +08004433 if (!iommu->ir_domain)
4434 return -ENOMEM;
4435
4436 iommu->ir_domain->parent = arch_get_ir_parent_domain();
Thomas Gleixner3e49a812017-06-20 01:37:12 +02004437 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4438 "AMD-IR-MSI",
4439 iommu->index);
Jiang Liu7c71d302015-04-13 14:11:33 +08004440 return 0;
4441}
Suravee Suthikulpanit8dbea3f2016-08-23 13:52:38 -05004442
4443int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4444{
4445 unsigned long flags;
4446 struct amd_iommu *iommu;
Sebastian Andrzej Siewior4fde5412018-03-22 16:22:38 +01004447 struct irq_remap_table *table;
Suravee Suthikulpanit8dbea3f2016-08-23 13:52:38 -05004448 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4449 int devid = ir_data->irq_2_irte.devid;
4450 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4451 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4452
4453 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4454 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4455 return 0;
4456
4457 iommu = amd_iommu_rlookup_table[devid];
4458 if (!iommu)
4459 return -ENODEV;
4460
Sebastian Andrzej Siewior4fde5412018-03-22 16:22:38 +01004461 table = get_irq_table(devid);
4462 if (!table)
Suravee Suthikulpanit8dbea3f2016-08-23 13:52:38 -05004463 return -ENODEV;
4464
Sebastian Andrzej Siewior4fde5412018-03-22 16:22:38 +01004465 raw_spin_lock_irqsave(&table->lock, flags);
Suravee Suthikulpanit8dbea3f2016-08-23 13:52:38 -05004466
4467 if (ref->lo.fields_vapic.guest_mode) {
Suravee Suthikulpanit90fcffd2018-06-27 10:31:22 -05004468 if (cpu >= 0) {
4469 ref->lo.fields_vapic.destination =
4470 APICID_TO_IRTE_DEST_LO(cpu);
4471 ref->hi.fields.destination =
4472 APICID_TO_IRTE_DEST_HI(cpu);
4473 }
Suravee Suthikulpanit8dbea3f2016-08-23 13:52:38 -05004474 ref->lo.fields_vapic.is_run = is_run;
4475 barrier();
4476 }
4477
Sebastian Andrzej Siewior4fde5412018-03-22 16:22:38 +01004478 raw_spin_unlock_irqrestore(&table->lock, flags);
Suravee Suthikulpanit8dbea3f2016-08-23 13:52:38 -05004479
4480 iommu_flush_irt(iommu, devid);
4481 iommu_completion_wait(iommu);
4482 return 0;
4483}
4484EXPORT_SYMBOL(amd_iommu_update_ga);
Joerg Roedel2b324502012-06-21 16:29:10 +02004485#endif