blob: 0c70c0815fdcd161e155bb6a298df717926a22d5 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Paul Walmsleyc0718df2011-03-10 22:17:45 -07002/*
3 * OMAP4 Voltage Controller (VC) data
4 *
5 * Copyright (C) 2007, 2010 Texas Instruments, Inc.
6 * Rajendra Nayak <rnayak@ti.com>
7 * Lesly A M <x0080970@ti.com>
8 * Thara Gopinath <thara@ti.com>
9 *
10 * Copyright (C) 2008, 2011 Nokia Corporation
11 * Kalle Jokiniemi
12 * Paul Walmsley
Paul Walmsleyc0718df2011-03-10 22:17:45 -070013 */
14#include <linux/io.h>
15#include <linux/err.h>
16#include <linux/init.h>
17
Tony Lindgren4e653312011-11-10 22:45:17 +010018#include "common.h"
Paul Walmsleyc0718df2011-03-10 22:17:45 -070019
20#include "prm44xx.h"
21#include "prm-regbits-44xx.h"
22#include "voltage.h"
23
24#include "vc.h"
25
26/*
27 * VC data common to 44xx chips
28 * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
29 */
Kevin Hilmand84adcf2011-03-22 16:14:57 -070030static const struct omap_vc_common omap4_vc_common = {
Paul Walmsleyc0718df2011-03-10 22:17:45 -070031 .bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET,
32 .data_shift = OMAP4430_DATA_SHIFT,
33 .slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT,
34 .regaddr_shift = OMAP4430_REGADDR_SHIFT,
35 .valid = OMAP4430_VALID_MASK,
36 .cmd_on_shift = OMAP4430_ON_SHIFT,
37 .cmd_on_mask = OMAP4430_ON_MASK,
38 .cmd_onlp_shift = OMAP4430_ONLP_SHIFT,
39 .cmd_ret_shift = OMAP4430_RET_SHIFT,
40 .cmd_off_shift = OMAP4430_OFF_SHIFT,
Kevin Hilmanf5395482011-03-30 16:36:30 -070041 .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET,
Tony Lindgren102bcb62015-05-04 08:54:41 -070042 .i2c_cfg_clear_mask = OMAP4430_SRMODEEN_MASK | OMAP4430_HSMODEEN_MASK,
Kevin Hilmanf5395482011-03-30 16:36:30 -070043 .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK,
44 .i2c_mcode_mask = OMAP4430_HSMCODE_MASK,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070045};
46
47/* VC instance data for each controllable voltage line */
Kevin Hilmand84adcf2011-03-22 16:14:57 -070048struct omap_vc_channel omap4_vc_mpu = {
Kevin Hilman8abc0b52011-06-02 17:28:13 -070049 .flags = OMAP_VC_CHANNEL_DEFAULT | OMAP_VC_CHANNEL_CFG_MUTANT,
Kevin Hilmand84adcf2011-03-22 16:14:57 -070050 .common = &omap4_vc_common,
Kevin Hilman5876c942011-07-20 16:35:46 -070051 .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
52 .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
53 .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
54 .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070055 .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070056 .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070057 .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
Kevin Hilmane4e021c2011-06-09 11:01:55 -070058 .smps_cmdra_mask = OMAP4430_CMDRA_VDD_MPU_L_MASK,
Kevin Hilman24d31942011-03-29 15:57:16 -070059 .cfg_channel_sa_shift = OMAP4430_SA_VDD_MPU_L_SHIFT,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070060};
61
Kevin Hilmand84adcf2011-03-22 16:14:57 -070062struct omap_vc_channel omap4_vc_iva = {
63 .common = &omap4_vc_common,
Kevin Hilman5876c942011-07-20 16:35:46 -070064 .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
65 .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
66 .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
67 .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070068 .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070069 .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070070 .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
Kevin Hilmane4e021c2011-06-09 11:01:55 -070071 .smps_cmdra_mask = OMAP4430_CMDRA_VDD_IVA_L_MASK,
Kevin Hilman24d31942011-03-29 15:57:16 -070072 .cfg_channel_sa_shift = OMAP4430_SA_VDD_IVA_L_SHIFT,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070073};
74
Kevin Hilmand84adcf2011-03-22 16:14:57 -070075struct omap_vc_channel omap4_vc_core = {
76 .common = &omap4_vc_common,
Kevin Hilman5876c942011-07-20 16:35:46 -070077 .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
78 .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
79 .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
80 .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070081 .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070082 .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070083 .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
Kevin Hilmane4e021c2011-06-09 11:01:55 -070084 .smps_cmdra_mask = OMAP4430_CMDRA_VDD_CORE_L_MASK,
Kevin Hilman24d31942011-03-29 15:57:16 -070085 .cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT,
Paul Walmsleyc0718df2011-03-10 22:17:45 -070086};
87
Tero Kristo8b5d8c02012-09-25 19:33:35 +030088/*
89 * Voltage levels for different operating modes: on, sleep, retention and off
90 */
91#define OMAP4_ON_VOLTAGE_UV 1375000
92#define OMAP4_ONLP_VOLTAGE_UV 1375000
93#define OMAP4_RET_VOLTAGE_UV 837500
94#define OMAP4_OFF_VOLTAGE_UV 0
95
96struct omap_vc_param omap4_mpu_vc_data = {
97 .on = OMAP4_ON_VOLTAGE_UV,
98 .onlp = OMAP4_ONLP_VOLTAGE_UV,
99 .ret = OMAP4_RET_VOLTAGE_UV,
100 .off = OMAP4_OFF_VOLTAGE_UV,
101};
102
103struct omap_vc_param omap4_iva_vc_data = {
104 .on = OMAP4_ON_VOLTAGE_UV,
105 .onlp = OMAP4_ONLP_VOLTAGE_UV,
106 .ret = OMAP4_RET_VOLTAGE_UV,
107 .off = OMAP4_OFF_VOLTAGE_UV,
108};
109
110struct omap_vc_param omap4_core_vc_data = {
111 .on = OMAP4_ON_VOLTAGE_UV,
112 .onlp = OMAP4_ONLP_VOLTAGE_UV,
113 .ret = OMAP4_RET_VOLTAGE_UV,
114 .off = OMAP4_OFF_VOLTAGE_UV,
115};