blob: d7ea6af74743e297c589efdbde246197c95b0688 [file] [log] [blame]
Thomas Gleixner8e8e69d2019-05-29 07:17:59 -07001// SPDX-License-Identifier: GPL-2.0-only
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06002/*
3 * SPI bus driver for the Topcliff PCH used by Intel SoCs
Grant Likely65308c42010-09-29 17:31:34 +09004 *
Tomoya MORINAGA2b246282011-10-28 09:35:22 +09005 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06006 */
7
Grant Likely65308c42010-09-29 17:31:34 +09008#include <linux/delay.h>
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06009#include <linux/pci.h>
10#include <linux/wait.h>
11#include <linux/spi/spi.h>
12#include <linux/interrupt.h>
13#include <linux/sched.h>
14#include <linux/spi/spidev.h>
15#include <linux/module.h>
16#include <linux/device.h>
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +090017#include <linux/platform_device.h>
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -060018
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +090019#include <linux/dmaengine.h>
20#include <linux/pch_dma.h>
21
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -060022/* Register offsets */
23#define PCH_SPCR 0x00 /* SPI control register */
24#define PCH_SPBRR 0x04 /* SPI baud rate register */
25#define PCH_SPSR 0x08 /* SPI status register */
26#define PCH_SPDWR 0x0C /* SPI write data register */
27#define PCH_SPDRR 0x10 /* SPI read data register */
28#define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
29#define PCH_SRST 0x1C /* SPI reset register */
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +090030#define PCH_ADDRESS_SIZE 0x20
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -060031
32#define PCH_SPSR_TFD 0x000007C0
33#define PCH_SPSR_RFD 0x0000F800
34
35#define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
36#define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
37
38#define PCH_RX_THOLD 7
39#define PCH_RX_THOLD_MAX 15
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -060040
Tomoya MORINAGAf3e03e2e2011-09-06 17:16:38 +090041#define PCH_TX_THOLD 2
42
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -060043#define PCH_MAX_BAUDRATE 5000000
44#define PCH_MAX_FIFO_DEPTH 16
45
46#define STATUS_RUNNING 1
47#define STATUS_EXITING 2
48#define PCH_SLEEP_TIME 10
49
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -060050#define SSN_LOW 0x02U
Tomoya MORINAGA8b7aa962011-09-06 17:16:35 +090051#define SSN_HIGH 0x03U
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -060052#define SSN_NO_CONTROL 0x00U
53#define PCH_MAX_CS 0xFF
54#define PCI_DEVICE_ID_GE_SPI 0x8816
55
56#define SPCR_SPE_BIT (1 << 0)
57#define SPCR_MSTR_BIT (1 << 1)
58#define SPCR_LSBF_BIT (1 << 4)
59#define SPCR_CPHA_BIT (1 << 5)
60#define SPCR_CPOL_BIT (1 << 6)
61#define SPCR_TFIE_BIT (1 << 8)
62#define SPCR_RFIE_BIT (1 << 9)
63#define SPCR_FIE_BIT (1 << 10)
64#define SPCR_ORIE_BIT (1 << 11)
65#define SPCR_MDFIE_BIT (1 << 12)
66#define SPCR_FICLR_BIT (1 << 24)
67#define SPSR_TFI_BIT (1 << 0)
68#define SPSR_RFI_BIT (1 << 1)
69#define SPSR_FI_BIT (1 << 2)
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +090070#define SPSR_ORF_BIT (1 << 3)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -060071#define SPBRR_SIZE_BIT (1 << 10)
72
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +090073#define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
74 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
Grant Likely65308c42010-09-29 17:31:34 +090075
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -060076#define SPCR_RFIC_FIELD 20
77#define SPCR_TFIC_FIELD 16
78
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +090079#define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
80#define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
81#define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -060082
83#define PCH_CLOCK_HZ 50000000
84#define PCH_MAX_SPBR 1023
85
Tomoya MORINAGA2b246282011-10-28 09:35:22 +090086/* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +090087#define PCI_DEVICE_ID_ML7213_SPI 0x802c
Tomoya MORINAGA2e2de2e32011-06-17 09:34:25 +090088#define PCI_DEVICE_ID_ML7223_SPI 0x800F
Tomoya MORINAGA92b3a5c2011-10-28 09:35:21 +090089#define PCI_DEVICE_ID_ML7831_SPI 0x8816
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +090090
91/*
92 * Set the number of SPI instance max
93 * Intel EG20T PCH : 1ch
Tomoya MORINAGA2b246282011-10-28 09:35:22 +090094 * LAPIS Semiconductor ML7213 IOH : 2ch
95 * LAPIS Semiconductor ML7223 IOH : 1ch
96 * LAPIS Semiconductor ML7831 IOH : 1ch
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +090097*/
98#define PCH_SPI_MAX_DEV 2
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -060099
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900100#define PCH_BUF_SIZE 4096
101#define PCH_DMA_TRANS_SIZE 12
102
103static int use_dma = 1;
104
105struct pch_spi_dma_ctrl {
106 struct dma_async_tx_descriptor *desc_tx;
107 struct dma_async_tx_descriptor *desc_rx;
108 struct pch_dma_slave param_tx;
109 struct pch_dma_slave param_rx;
110 struct dma_chan *chan_tx;
111 struct dma_chan *chan_rx;
112 struct scatterlist *sg_tx_p;
113 struct scatterlist *sg_rx_p;
114 struct scatterlist sg_tx;
115 struct scatterlist sg_rx;
116 int nent;
117 void *tx_buf_virt;
118 void *rx_buf_virt;
119 dma_addr_t tx_buf_dma;
120 dma_addr_t rx_buf_dma;
121};
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600122/**
123 * struct pch_spi_data - Holds the SPI channel specific details
124 * @io_remap_addr: The remapped PCI base address
125 * @master: Pointer to the SPI master structure
126 * @work: Reference to work queue handler
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600127 * @wait: Wait queue for waking up upon receiving an
128 * interrupt.
129 * @transfer_complete: Status of SPI Transfer
130 * @bcurrent_msg_processing: Status flag for message processing
131 * @lock: Lock for protecting this structure
132 * @queue: SPI Message queue
133 * @status: Status of the SPI driver
134 * @bpw_len: Length of data to be transferred in bits per
135 * word
136 * @transfer_active: Flag showing active transfer
137 * @tx_index: Transmit data count; for bookkeeping during
138 * transfer
139 * @rx_index: Receive data count; for bookkeeping during
140 * transfer
141 * @tx_buff: Buffer for data to be transmitted
142 * @rx_index: Buffer for Received data
143 * @n_curnt_chip: The chip number that this SPI driver currently
144 * operates on
145 * @current_chip: Reference to the current chip that this SPI
146 * driver currently operates on
147 * @current_msg: The current message that this SPI driver is
148 * handling
149 * @cur_trans: The current transfer that this SPI driver is
150 * handling
151 * @board_dat: Reference to the SPI device data structure
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +0900152 * @plat_dev: platform_device structure
153 * @ch: SPI channel number
154 * @irq_reg_sts: Status of IRQ registration
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600155 */
156struct pch_spi_data {
157 void __iomem *io_remap_addr;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900158 unsigned long io_base_addr;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600159 struct spi_master *master;
160 struct work_struct work;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600161 wait_queue_head_t wait;
162 u8 transfer_complete;
163 u8 bcurrent_msg_processing;
164 spinlock_t lock;
165 struct list_head queue;
166 u8 status;
167 u32 bpw_len;
168 u8 transfer_active;
169 u32 tx_index;
170 u32 rx_index;
171 u16 *pkt_tx_buff;
172 u16 *pkt_rx_buff;
173 u8 n_curnt_chip;
174 struct spi_device *current_chip;
175 struct spi_message *current_msg;
176 struct spi_transfer *cur_trans;
177 struct pch_spi_board_data *board_dat;
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +0900178 struct platform_device *plat_dev;
179 int ch;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900180 struct pch_spi_dma_ctrl dma;
181 int use_dma;
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +0900182 u8 irq_reg_sts;
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +0900183 int save_total_len;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600184};
185
186/**
187 * struct pch_spi_board_data - Holds the SPI device specific details
188 * @pdev: Pointer to the PCI device
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600189 * @suspend_sts: Status of suspend
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +0900190 * @num: The number of SPI device instance
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600191 */
192struct pch_spi_board_data {
193 struct pci_dev *pdev;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600194 u8 suspend_sts;
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +0900195 int num;
196};
197
198struct pch_pd_dev_save {
199 int num;
200 struct platform_device *pd_save[PCH_SPI_MAX_DEV];
201 struct pch_spi_board_data *board_dat;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600202};
203
Jingoo Han9a21e472013-12-03 08:25:19 +0900204static const struct pci_device_id pch_spi_pcidev_id[] = {
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +0900205 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
206 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
Tomoya MORINAGA2e2de2e32011-06-17 09:34:25 +0900207 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
Tomoya MORINAGA92b3a5c2011-10-28 09:35:21 +0900208 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +0900209 { }
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600210};
211
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600212/**
213 * pch_spi_writereg() - Performs register writes
214 * @master: Pointer to struct spi_master.
215 * @idx: Register offset.
216 * @val: Value to be written to register.
217 */
218static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
219{
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600220 struct pch_spi_data *data = spi_master_get_devdata(master);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600221 iowrite32(val, (data->io_remap_addr + idx));
222}
223
224/**
225 * pch_spi_readreg() - Performs register reads
226 * @master: Pointer to struct spi_master.
227 * @idx: Register offset.
228 */
229static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
230{
231 struct pch_spi_data *data = spi_master_get_devdata(master);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600232 return ioread32(data->io_remap_addr + idx);
233}
234
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600235static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
236 u32 set, u32 clr)
237{
238 u32 tmp = pch_spi_readreg(master, idx);
239 tmp = (tmp & ~clr) | set;
240 pch_spi_writereg(master, idx, tmp);
241}
242
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600243static void pch_spi_set_master_mode(struct spi_master *master)
244{
245 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
246}
247
248/**
249 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
250 * @master: Pointer to struct spi_master.
251 */
252static void pch_spi_clear_fifo(struct spi_master *master)
253{
254 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
255 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
256}
257
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600258static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
259 void __iomem *io_remap_addr)
260{
261 u32 n_read, tx_index, rx_index, bpw_len;
262 u16 *pkt_rx_buffer, *pkt_tx_buff;
263 int read_cnt;
264 u32 reg_spcr_val;
265 void __iomem *spsr;
266 void __iomem *spdrr;
267 void __iomem *spdwr;
268
269 spsr = io_remap_addr + PCH_SPSR;
270 iowrite32(reg_spsr_val, spsr);
271
272 if (data->transfer_active) {
273 rx_index = data->rx_index;
274 tx_index = data->tx_index;
275 bpw_len = data->bpw_len;
276 pkt_rx_buffer = data->pkt_rx_buff;
277 pkt_tx_buff = data->pkt_tx_buff;
278
279 spdrr = io_remap_addr + PCH_SPDRR;
280 spdwr = io_remap_addr + PCH_SPDWR;
281
282 n_read = PCH_READABLE(reg_spsr_val);
283
284 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
285 pkt_rx_buffer[rx_index++] = ioread32(spdrr);
286 if (tx_index < bpw_len)
287 iowrite32(pkt_tx_buff[tx_index++], spdwr);
288 }
289
290 /* disable RFI if not needed */
291 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
292 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
Grant Likely65308c42010-09-29 17:31:34 +0900293 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600294
295 /* reset rx threshold */
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900296 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600297 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900298
299 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600300 }
301
302 /* update counts */
303 data->tx_index = tx_index;
304 data->rx_index = rx_index;
305
Danny Kukawkade3bd7e2012-02-14 15:35:03 +0100306 /* if transfer complete interrupt */
307 if (reg_spsr_val & SPSR_FI_BIT) {
308 if ((tx_index == bpw_len) && (rx_index == tx_index)) {
309 /* disable interrupts */
310 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
311 PCH_ALL);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600312
Danny Kukawkade3bd7e2012-02-14 15:35:03 +0100313 /* transfer is completed;
314 inform pch_spi_process_messages */
315 data->transfer_complete = true;
316 data->transfer_active = false;
317 wake_up(&data->wait);
318 } else {
Alexander Stein342451d2014-03-25 08:10:32 +0100319 dev_vdbg(&data->master->dev,
Danny Kukawkade3bd7e2012-02-14 15:35:03 +0100320 "%s : Transfer is not completed",
321 __func__);
322 }
Tomoya MORINAGA373b0eb2011-09-06 17:16:36 +0900323 }
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600324 }
325}
326
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600327/**
328 * pch_spi_handler() - Interrupt handler
329 * @irq: The interrupt number.
330 * @dev_id: Pointer to struct pch_spi_board_data.
331 */
332static irqreturn_t pch_spi_handler(int irq, void *dev_id)
333{
334 u32 reg_spsr_val;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600335 void __iomem *spsr;
336 void __iomem *io_remap_addr;
337 irqreturn_t ret = IRQ_NONE;
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +0900338 struct pch_spi_data *data = dev_id;
339 struct pch_spi_board_data *board_dat = data->board_dat;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600340
341 if (board_dat->suspend_sts) {
342 dev_dbg(&board_dat->pdev->dev,
343 "%s returning due to suspend\n", __func__);
344 return IRQ_NONE;
345 }
346
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600347 io_remap_addr = data->io_remap_addr;
348 spsr = io_remap_addr + PCH_SPSR;
349
350 reg_spsr_val = ioread32(spsr);
351
Tomoya MORINAGA25e803f2011-09-06 17:16:37 +0900352 if (reg_spsr_val & SPSR_ORF_BIT) {
353 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
Sachin Kamatf5d8ee32013-05-31 17:17:48 +0530354 if (data->current_msg->complete) {
Tomoya MORINAGA25e803f2011-09-06 17:16:37 +0900355 data->transfer_complete = true;
356 data->current_msg->status = -EIO;
357 data->current_msg->complete(data->current_msg->context);
358 data->bcurrent_msg_processing = false;
359 data->current_msg = NULL;
360 data->cur_trans = NULL;
361 }
362 }
363
364 if (data->use_dma)
365 return IRQ_NONE;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900366
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600367 /* Check if the interrupt is for SPI device */
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600368 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
369 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
370 ret = IRQ_HANDLED;
371 }
372
373 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
374 __func__, ret);
375
376 return ret;
377}
378
379/**
380 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
381 * @master: Pointer to struct spi_master.
382 * @speed_hz: Baud rate.
383 */
384static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
385{
Grant Likely65308c42010-09-29 17:31:34 +0900386 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600387
388 /* if baud rate is less than we can support limit it */
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600389 if (n_spbr > PCH_MAX_SPBR)
390 n_spbr = PCH_MAX_SPBR;
391
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900392 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600393}
394
395/**
396 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
397 * @master: Pointer to struct spi_master.
398 * @bits_per_word: Bits per word for SPI transfer.
399 */
400static void pch_spi_set_bits_per_word(struct spi_master *master,
401 u8 bits_per_word)
402{
403 if (bits_per_word == 8)
404 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
405 else
406 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
407}
408
409/**
410 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
411 * @spi: Pointer to struct spi_device.
412 */
413static void pch_spi_setup_transfer(struct spi_device *spi)
414{
Grant Likely65308c42010-09-29 17:31:34 +0900415 u32 flags = 0;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600416
417 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
418 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
419 spi->max_speed_hz);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600420 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
421
422 /* set bits per word */
423 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
424
Grant Likely65308c42010-09-29 17:31:34 +0900425 if (!(spi->mode & SPI_LSB_FIRST))
426 flags |= SPCR_LSBF_BIT;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600427 if (spi->mode & SPI_CPOL)
Grant Likely65308c42010-09-29 17:31:34 +0900428 flags |= SPCR_CPOL_BIT;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600429 if (spi->mode & SPI_CPHA)
Grant Likely65308c42010-09-29 17:31:34 +0900430 flags |= SPCR_CPHA_BIT;
431 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
432 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600433
434 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
435 pch_spi_clear_fifo(spi->master);
436}
437
438/**
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600439 * pch_spi_reset() - Clears SPI registers
440 * @master: Pointer to struct spi_master.
441 */
442static void pch_spi_reset(struct spi_master *master)
443{
444 /* write 1 to reset SPI */
445 pch_spi_writereg(master, PCH_SRST, 0x1);
446
447 /* clear reset */
448 pch_spi_writereg(master, PCH_SRST, 0x0);
449}
450
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600451static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
452{
453
454 struct spi_transfer *transfer;
455 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
456 int retval;
457 unsigned long flags;
458
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900459 spin_lock_irqsave(&data->lock, flags);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600460 /* validate Tx/Rx buffers and Transfer length */
461 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
Grant Likely65308c42010-09-29 17:31:34 +0900462 if (!transfer->tx_buf && !transfer->rx_buf) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600463 dev_err(&pspi->dev,
464 "%s Tx and Rx buffer NULL\n", __func__);
465 retval = -EINVAL;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900466 goto err_return_spinlock;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600467 }
468
Grant Likely65308c42010-09-29 17:31:34 +0900469 if (!transfer->len) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600470 dev_err(&pspi->dev, "%s Transfer length invalid\n",
471 __func__);
472 retval = -EINVAL;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900473 goto err_return_spinlock;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600474 }
475
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +0300476 dev_dbg(&pspi->dev,
477 "%s Tx/Rx buffer valid. Transfer length valid\n",
478 __func__);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600479 }
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900480 spin_unlock_irqrestore(&data->lock, flags);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600481
Grant Likely65308c42010-09-29 17:31:34 +0900482 /* We won't process any messages if we have been asked to terminate */
483 if (data->status == STATUS_EXITING) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600484 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
485 retval = -ESHUTDOWN;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900486 goto err_out;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600487 }
488
489 /* If suspended ,return -EINVAL */
490 if (data->board_dat->suspend_sts) {
Grant Likely65308c42010-09-29 17:31:34 +0900491 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600492 retval = -EINVAL;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900493 goto err_out;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600494 }
495
496 /* set status of message */
497 pmsg->actual_length = 0;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600498 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
499
500 pmsg->status = -EINPROGRESS;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900501 spin_lock_irqsave(&data->lock, flags);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600502 /* add message to queue */
503 list_add_tail(&pmsg->queue, &data->queue);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900504 spin_unlock_irqrestore(&data->lock, flags);
505
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600506 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
507
Bhaktipriya Shridhar0d357732016-07-10 19:42:13 +0530508 schedule_work(&data->work);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600509 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
510
511 retval = 0;
512
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600513err_out:
514 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
515 return retval;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900516err_return_spinlock:
517 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
518 spin_unlock_irqrestore(&data->lock, flags);
519 return retval;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600520}
521
522static inline void pch_spi_select_chip(struct pch_spi_data *data,
523 struct spi_device *pspi)
524{
Grant Likely65308c42010-09-29 17:31:34 +0900525 if (data->current_chip != NULL) {
526 if (pspi->chip_select != data->n_curnt_chip) {
527 dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600528 data->current_chip = NULL;
529 }
530 }
531
532 data->current_chip = pspi;
533
534 data->n_curnt_chip = data->current_chip->chip_select;
535
536 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
537 pch_spi_setup_transfer(pspi);
538}
539
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900540static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600541{
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600542 int size;
543 u32 n_writes;
544 int j;
Wei Yongjuncd8d9842013-04-27 14:06:00 +0800545 struct spi_message *pmsg, *tmp;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600546 const u8 *tx_buf;
547 const u16 *tx_sbuf;
548
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600549 /* set baud rate if needed */
550 if (data->cur_trans->speed_hz) {
Grant Likely65308c42010-09-29 17:31:34 +0900551 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
552 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600553 }
554
555 /* set bits per word if needed */
Grant Likely65308c42010-09-29 17:31:34 +0900556 if (data->cur_trans->bits_per_word &&
557 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
558 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600559 pch_spi_set_bits_per_word(data->master,
Grant Likely65308c42010-09-29 17:31:34 +0900560 data->cur_trans->bits_per_word);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600561 *bpw = data->cur_trans->bits_per_word;
562 } else {
563 *bpw = data->current_msg->spi->bits_per_word;
564 }
565
566 /* reset Tx/Rx index */
567 data->tx_index = 0;
568 data->rx_index = 0;
569
570 data->bpw_len = data->cur_trans->len / (*bpw / 8);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600571
572 /* find alloc size */
Grant Likely65308c42010-09-29 17:31:34 +0900573 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
574
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600575 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
576 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600577 if (data->pkt_tx_buff != NULL) {
578 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
Grant Likely65308c42010-09-29 17:31:34 +0900579 if (!data->pkt_rx_buff)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600580 kfree(data->pkt_tx_buff);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600581 }
582
Grant Likely65308c42010-09-29 17:31:34 +0900583 if (!data->pkt_rx_buff) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600584 /* flush queue and set status of all transfers to -ENOMEM */
Wei Yongjuncd8d9842013-04-27 14:06:00 +0800585 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600586 pmsg->status = -ENOMEM;
587
Sachin Kamatf5d8ee32013-05-31 17:17:48 +0530588 if (pmsg->complete)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600589 pmsg->complete(pmsg->context);
590
591 /* delete from queue */
592 list_del_init(&pmsg->queue);
593 }
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600594 return;
595 }
596
597 /* copy Tx Data */
Grant Likely65308c42010-09-29 17:31:34 +0900598 if (data->cur_trans->tx_buf != NULL) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600599 if (*bpw == 8) {
Grant Likely65308c42010-09-29 17:31:34 +0900600 tx_buf = data->cur_trans->tx_buf;
601 for (j = 0; j < data->bpw_len; j++)
602 data->pkt_tx_buff[j] = *tx_buf++;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600603 } else {
Grant Likely65308c42010-09-29 17:31:34 +0900604 tx_sbuf = data->cur_trans->tx_buf;
605 for (j = 0; j < data->bpw_len; j++)
606 data->pkt_tx_buff[j] = *tx_sbuf++;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600607 }
608 }
609
610 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
Grant Likely65308c42010-09-29 17:31:34 +0900611 n_writes = data->bpw_len;
612 if (n_writes > PCH_MAX_FIFO_DEPTH)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600613 n_writes = PCH_MAX_FIFO_DEPTH;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600614
Markus Elfringb9963562017-01-13 16:36:09 +0100615 dev_dbg(&data->master->dev,
616 "\n%s:Pulling down SSN low - writing 0x2 to SSNXCR\n",
617 __func__);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600618 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
619
Grant Likely65308c42010-09-29 17:31:34 +0900620 for (j = 0; j < n_writes; j++)
621 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600622
623 /* update tx_index */
624 data->tx_index = j;
625
626 /* reset transfer complete flag */
627 data->transfer_complete = false;
628 data->transfer_active = true;
629}
630
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900631static void pch_spi_nomore_transfer(struct pch_spi_data *data)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600632{
Wei Yongjuncd8d9842013-04-27 14:06:00 +0800633 struct spi_message *pmsg, *tmp;
Grant Likely65308c42010-09-29 17:31:34 +0900634 dev_dbg(&data->master->dev, "%s called\n", __func__);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600635 /* Invoke complete callback
Grant Likely65308c42010-09-29 17:31:34 +0900636 * [To the spi core..indicating end of transfer] */
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600637 data->current_msg->status = 0;
638
Sachin Kamatf5d8ee32013-05-31 17:17:48 +0530639 if (data->current_msg->complete) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600640 dev_dbg(&data->master->dev,
641 "%s:Invoking callback of SPI core\n", __func__);
642 data->current_msg->complete(data->current_msg->context);
643 }
644
645 /* update status in global variable */
646 data->bcurrent_msg_processing = false;
647
648 dev_dbg(&data->master->dev,
649 "%s:data->bcurrent_msg_processing = false\n", __func__);
650
651 data->current_msg = NULL;
652 data->cur_trans = NULL;
653
Grant Likely65308c42010-09-29 17:31:34 +0900654 /* check if we have items in list and not suspending
655 * return 1 if list empty */
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600656 if ((list_empty(&data->queue) == 0) &&
Grant Likely65308c42010-09-29 17:31:34 +0900657 (!data->board_dat->suspend_sts) &&
658 (data->status != STATUS_EXITING)) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600659 /* We have some more work to do (either there is more tranint
Grant Likely65308c42010-09-29 17:31:34 +0900660 * bpw;sfer requests in the current message or there are
661 *more messages)
662 */
663 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
Bhaktipriya Shridhar0d357732016-07-10 19:42:13 +0530664 schedule_work(&data->work);
Grant Likely65308c42010-09-29 17:31:34 +0900665 } else if (data->board_dat->suspend_sts ||
666 data->status == STATUS_EXITING) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600667 dev_dbg(&data->master->dev,
668 "%s suspend/remove initiated, flushing queue\n",
669 __func__);
Wei Yongjuncd8d9842013-04-27 14:06:00 +0800670 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600671 pmsg->status = -EIO;
672
Grant Likely65308c42010-09-29 17:31:34 +0900673 if (pmsg->complete)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600674 pmsg->complete(pmsg->context);
675
676 /* delete from queue */
677 list_del_init(&pmsg->queue);
678 }
679 }
680}
681
682static void pch_spi_set_ir(struct pch_spi_data *data)
683{
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900684 /* enable interrupts, set threshold, enable SPI */
685 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
Justin P. Mattock77e58ef2010-12-31 09:50:31 -0800686 /* set receive threshold to PCH_RX_THOLD */
Grant Likely65308c42010-09-29 17:31:34 +0900687 pch_spi_setclr_reg(data->master, PCH_SPCR,
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900688 PCH_RX_THOLD << SPCR_RFIC_FIELD |
689 SPCR_FIE_BIT | SPCR_RFIE_BIT |
690 SPCR_ORIE_BIT | SPCR_SPE_BIT,
691 MASK_RFIC_SPCR_BITS | PCH_ALL);
692 else
Justin P. Mattock77e58ef2010-12-31 09:50:31 -0800693 /* set receive threshold to maximum */
Grant Likely65308c42010-09-29 17:31:34 +0900694 pch_spi_setclr_reg(data->master, PCH_SPCR,
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900695 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
696 SPCR_FIE_BIT | SPCR_ORIE_BIT |
697 SPCR_SPE_BIT,
698 MASK_RFIC_SPCR_BITS | PCH_ALL);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600699
700 /* Wait until the transfer completes; go to sleep after
701 initiating the transfer. */
702 dev_dbg(&data->master->dev,
703 "%s:waiting for transfer to get over\n", __func__);
704
705 wait_event_interruptible(data->wait, data->transfer_complete);
706
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600707 /* clear all interrupts */
708 pch_spi_writereg(data->master, PCH_SPSR,
Grant Likely65308c42010-09-29 17:31:34 +0900709 pch_spi_readreg(data->master, PCH_SPSR));
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900710 /* Disable interrupts and SPI transfer */
711 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
712 /* clear FIFO */
713 pch_spi_clear_fifo(data->master);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600714}
715
716static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
717{
718 int j;
719 u8 *rx_buf;
720 u16 *rx_sbuf;
721
722 /* copy Rx Data */
Grant Likely65308c42010-09-29 17:31:34 +0900723 if (!data->cur_trans->rx_buf)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600724 return;
725
726 if (bpw == 8) {
Grant Likely65308c42010-09-29 17:31:34 +0900727 rx_buf = data->cur_trans->rx_buf;
728 for (j = 0; j < data->bpw_len; j++)
729 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600730 } else {
Grant Likely65308c42010-09-29 17:31:34 +0900731 rx_sbuf = data->cur_trans->rx_buf;
732 for (j = 0; j < data->bpw_len; j++)
733 *rx_sbuf++ = data->pkt_rx_buff[j];
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -0600734 }
735}
736
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900737static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
738{
739 int j;
740 u8 *rx_buf;
741 u16 *rx_sbuf;
742 const u8 *rx_dma_buf;
743 const u16 *rx_dma_sbuf;
744
745 /* copy Rx Data */
746 if (!data->cur_trans->rx_buf)
747 return;
748
749 if (bpw == 8) {
750 rx_buf = data->cur_trans->rx_buf;
751 rx_dma_buf = data->dma.rx_buf_virt;
752 for (j = 0; j < data->bpw_len; j++)
753 *rx_buf++ = *rx_dma_buf++ & 0xFF;
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +0900754 data->cur_trans->rx_buf = rx_buf;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900755 } else {
756 rx_sbuf = data->cur_trans->rx_buf;
757 rx_dma_sbuf = data->dma.rx_buf_virt;
758 for (j = 0; j < data->bpw_len; j++)
759 *rx_sbuf++ = *rx_dma_sbuf++;
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +0900760 data->cur_trans->rx_buf = rx_sbuf;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900761 }
762}
763
Tomoya MORINAGA25e803f2011-09-06 17:16:37 +0900764static int pch_spi_start_transfer(struct pch_spi_data *data)
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900765{
766 struct pch_spi_dma_ctrl *dma;
767 unsigned long flags;
Tomoya MORINAGA25e803f2011-09-06 17:16:37 +0900768 int rtn;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900769
770 dma = &data->dma;
771
772 spin_lock_irqsave(&data->lock, flags);
773
774 /* disable interrupts, SPI set enable */
775 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
776
777 spin_unlock_irqrestore(&data->lock, flags);
778
779 /* Wait until the transfer completes; go to sleep after
780 initiating the transfer. */
781 dev_dbg(&data->master->dev,
782 "%s:waiting for transfer to get over\n", __func__);
Tomoya MORINAGA25e803f2011-09-06 17:16:37 +0900783 rtn = wait_event_interruptible_timeout(data->wait,
784 data->transfer_complete,
785 msecs_to_jiffies(2 * HZ));
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +0900786 if (!rtn)
787 dev_err(&data->master->dev,
788 "%s wait-event timeout\n", __func__);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900789
790 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
791 DMA_FROM_DEVICE);
Tomoya MORINAGA27504be2011-09-06 17:16:34 +0900792
793 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
794 DMA_FROM_DEVICE);
795 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
796
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900797 async_tx_ack(dma->desc_rx);
798 async_tx_ack(dma->desc_tx);
799 kfree(dma->sg_tx_p);
800 kfree(dma->sg_rx_p);
801
802 spin_lock_irqsave(&data->lock, flags);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900803
804 /* clear fifo threshold, disable interrupts, disable SPI transfer */
805 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
806 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
807 SPCR_SPE_BIT);
808 /* clear all interrupts */
809 pch_spi_writereg(data->master, PCH_SPSR,
810 pch_spi_readreg(data->master, PCH_SPSR));
811 /* clear FIFO */
812 pch_spi_clear_fifo(data->master);
813
814 spin_unlock_irqrestore(&data->lock, flags);
Tomoya MORINAGA25e803f2011-09-06 17:16:37 +0900815
816 return rtn;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900817}
818
819static void pch_dma_rx_complete(void *arg)
820{
821 struct pch_spi_data *data = arg;
822
823 /* transfer is completed;inform pch_spi_process_messages_dma */
824 data->transfer_complete = true;
825 wake_up_interruptible(&data->wait);
826}
827
828static bool pch_spi_filter(struct dma_chan *chan, void *slave)
829{
830 struct pch_dma_slave *param = slave;
831
832 if ((chan->chan_id == param->chan_id) &&
833 (param->dma_dev == chan->device->dev)) {
834 chan->private = param;
835 return true;
836 } else {
837 return false;
838 }
839}
840
841static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
842{
843 dma_cap_mask_t mask;
844 struct dma_chan *chan;
845 struct pci_dev *dma_dev;
846 struct pch_dma_slave *param;
847 struct pch_spi_dma_ctrl *dma;
848 unsigned int width;
849
850 if (bpw == 8)
851 width = PCH_DMA_WIDTH_1_BYTE;
852 else
853 width = PCH_DMA_WIDTH_2_BYTES;
854
855 dma = &data->dma;
856 dma_cap_zero(mask);
857 dma_cap_set(DMA_SLAVE, mask);
858
859 /* Get DMA's dev information */
Andy Shevchenkoa90821052014-07-30 18:50:30 +0300860 dma_dev = pci_get_slot(data->board_dat->pdev->bus,
861 PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900862
863 /* Set Tx DMA */
864 param = &dma->param_tx;
865 param->dma_dev = &dma_dev->dev;
zhengbin10e413f2019-11-28 10:51:52 +0800866 param->chan_id = data->ch * 2; /* Tx = 0, 2 */
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900867 param->tx_reg = data->io_base_addr + PCH_SPDWR;
868 param->width = width;
869 chan = dma_request_channel(mask, pch_spi_filter, param);
870 if (!chan) {
871 dev_err(&data->master->dev,
872 "ERROR: dma_request_channel FAILS(Tx)\n");
873 data->use_dma = 0;
874 return;
875 }
876 dma->chan_tx = chan;
877
878 /* Set Rx DMA */
879 param = &dma->param_rx;
880 param->dma_dev = &dma_dev->dev;
zhengbin10e413f2019-11-28 10:51:52 +0800881 param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900882 param->rx_reg = data->io_base_addr + PCH_SPDRR;
883 param->width = width;
884 chan = dma_request_channel(mask, pch_spi_filter, param);
885 if (!chan) {
886 dev_err(&data->master->dev,
887 "ERROR: dma_request_channel FAILS(Rx)\n");
888 dma_release_channel(dma->chan_tx);
889 dma->chan_tx = NULL;
890 data->use_dma = 0;
891 return;
892 }
893 dma->chan_rx = chan;
894}
895
896static void pch_spi_release_dma(struct pch_spi_data *data)
897{
898 struct pch_spi_dma_ctrl *dma;
899
900 dma = &data->dma;
901 if (dma->chan_tx) {
902 dma_release_channel(dma->chan_tx);
903 dma->chan_tx = NULL;
904 }
905 if (dma->chan_rx) {
906 dma_release_channel(dma->chan_rx);
907 dma->chan_rx = NULL;
908 }
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900909}
910
911static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
912{
913 const u8 *tx_buf;
914 const u16 *tx_sbuf;
915 u8 *tx_dma_buf;
916 u16 *tx_dma_sbuf;
917 struct scatterlist *sg;
918 struct dma_async_tx_descriptor *desc_tx;
919 struct dma_async_tx_descriptor *desc_rx;
920 int num;
921 int i;
922 int size;
923 int rem;
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +0900924 int head;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900925 unsigned long flags;
926 struct pch_spi_dma_ctrl *dma;
927
928 dma = &data->dma;
929
930 /* set baud rate if needed */
931 if (data->cur_trans->speed_hz) {
932 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
933 spin_lock_irqsave(&data->lock, flags);
934 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
935 spin_unlock_irqrestore(&data->lock, flags);
936 }
937
938 /* set bits per word if needed */
939 if (data->cur_trans->bits_per_word &&
940 (data->current_msg->spi->bits_per_word !=
941 data->cur_trans->bits_per_word)) {
942 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
943 spin_lock_irqsave(&data->lock, flags);
944 pch_spi_set_bits_per_word(data->master,
945 data->cur_trans->bits_per_word);
946 spin_unlock_irqrestore(&data->lock, flags);
947 *bpw = data->cur_trans->bits_per_word;
948 } else {
949 *bpw = data->current_msg->spi->bits_per_word;
950 }
951 data->bpw_len = data->cur_trans->len / (*bpw / 8);
952
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +0900953 if (data->bpw_len > PCH_BUF_SIZE) {
954 data->bpw_len = PCH_BUF_SIZE;
955 data->cur_trans->len -= PCH_BUF_SIZE;
956 }
957
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900958 /* copy Tx Data */
959 if (data->cur_trans->tx_buf != NULL) {
960 if (*bpw == 8) {
961 tx_buf = data->cur_trans->tx_buf;
962 tx_dma_buf = dma->tx_buf_virt;
963 for (i = 0; i < data->bpw_len; i++)
964 *tx_dma_buf++ = *tx_buf++;
965 } else {
966 tx_sbuf = data->cur_trans->tx_buf;
967 tx_dma_sbuf = dma->tx_buf_virt;
968 for (i = 0; i < data->bpw_len; i++)
969 *tx_dma_sbuf++ = *tx_sbuf++;
970 }
971 }
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +0900972
973 /* Calculate Rx parameter for DMA transmitting */
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900974 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +0900975 if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
976 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
977 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
978 } else {
979 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
980 rem = PCH_DMA_TRANS_SIZE;
981 }
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900982 size = PCH_DMA_TRANS_SIZE;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900983 } else {
984 num = 1;
985 size = data->bpw_len;
986 rem = data->bpw_len;
987 }
988 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
989 __func__, num, size, rem);
990 spin_lock_irqsave(&data->lock, flags);
991
992 /* set receive fifo threshold and transmit fifo threshold */
993 pch_spi_setclr_reg(data->master, PCH_SPCR,
994 ((size - 1) << SPCR_RFIC_FIELD) |
Tomoya MORINAGAf3e03e2e2011-09-06 17:16:38 +0900995 (PCH_TX_THOLD << SPCR_TFIC_FIELD),
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +0900996 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
997
998 spin_unlock_irqrestore(&data->lock, flags);
999
1000 /* RX */
Markus Elfring84aa0ba2017-01-13 15:25:22 +01001001 dma->sg_rx_p = kcalloc(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC);
YueHaibinge902cdc2019-01-23 20:00:22 +08001002 if (!dma->sg_rx_p)
1003 return;
1004
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001005 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1006 /* offset, length setting */
1007 sg = dma->sg_rx_p;
1008 for (i = 0; i < num; i++, sg++) {
Tomoya MORINAGAf3e03e2e2011-09-06 17:16:38 +09001009 if (i == (num - 2)) {
1010 sg->offset = size * i;
1011 sg->offset = sg->offset * (*bpw / 8);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001012 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1013 sg->offset);
1014 sg_dma_len(sg) = rem;
Tomoya MORINAGAf3e03e2e2011-09-06 17:16:38 +09001015 } else if (i == (num - 1)) {
1016 sg->offset = size * (i - 1) + rem;
1017 sg->offset = sg->offset * (*bpw / 8);
1018 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1019 sg->offset);
1020 sg_dma_len(sg) = size;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001021 } else {
Tomoya MORINAGAf3e03e2e2011-09-06 17:16:38 +09001022 sg->offset = size * i;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001023 sg->offset = sg->offset * (*bpw / 8);
1024 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1025 sg->offset);
1026 sg_dma_len(sg) = size;
1027 }
1028 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1029 }
1030 sg = dma->sg_rx_p;
Alexandre Bounine16052822012-03-08 16:11:18 -05001031 desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
Vinod Koula485df42011-10-14 10:47:38 +05301032 num, DMA_DEV_TO_MEM,
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001033 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1034 if (!desc_rx) {
Geert Uytterhoeven2857d802014-07-11 18:13:25 +02001035 dev_err(&data->master->dev,
1036 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001037 return;
1038 }
1039 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1040 desc_rx->callback = pch_dma_rx_complete;
1041 desc_rx->callback_param = data;
1042 dma->nent = num;
1043 dma->desc_rx = desc_rx;
1044
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +09001045 /* Calculate Tx parameter for DMA transmitting */
1046 if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1047 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1048 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1049 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1050 rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1051 } else {
1052 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1053 rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1054 PCH_DMA_TRANS_SIZE - head;
1055 }
Tomoya MORINAGAf3e03e2e2011-09-06 17:16:38 +09001056 size = PCH_DMA_TRANS_SIZE;
Tomoya MORINAGAf3e03e2e2011-09-06 17:16:38 +09001057 } else {
1058 num = 1;
1059 size = data->bpw_len;
1060 rem = data->bpw_len;
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +09001061 head = 0;
Tomoya MORINAGAf3e03e2e2011-09-06 17:16:38 +09001062 }
1063
Markus Elfring84aa0ba2017-01-13 15:25:22 +01001064 dma->sg_tx_p = kcalloc(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC);
YueHaibinge902cdc2019-01-23 20:00:22 +08001065 if (!dma->sg_tx_p)
1066 return;
1067
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001068 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1069 /* offset, length setting */
1070 sg = dma->sg_tx_p;
1071 for (i = 0; i < num; i++, sg++) {
1072 if (i == 0) {
1073 sg->offset = 0;
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +09001074 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1075 sg->offset);
1076 sg_dma_len(sg) = size + head;
1077 } else if (i == (num - 1)) {
1078 sg->offset = head + size * i;
1079 sg->offset = sg->offset * (*bpw / 8);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001080 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1081 sg->offset);
1082 sg_dma_len(sg) = rem;
1083 } else {
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +09001084 sg->offset = head + size * i;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001085 sg->offset = sg->offset * (*bpw / 8);
1086 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1087 sg->offset);
1088 sg_dma_len(sg) = size;
1089 }
1090 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1091 }
1092 sg = dma->sg_tx_p;
Alexandre Bounine16052822012-03-08 16:11:18 -05001093 desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
Vinod Koula485df42011-10-14 10:47:38 +05301094 sg, num, DMA_MEM_TO_DEV,
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001095 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1096 if (!desc_tx) {
Geert Uytterhoeven2857d802014-07-11 18:13:25 +02001097 dev_err(&data->master->dev,
1098 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001099 return;
1100 }
1101 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1102 desc_tx->callback = NULL;
1103 desc_tx->callback_param = data;
1104 dma->nent = num;
1105 dma->desc_tx = desc_tx;
1106
Alexander Steinc1b20aa2014-02-19 10:36:09 +01001107 dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001108
1109 spin_lock_irqsave(&data->lock, flags);
1110 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1111 desc_rx->tx_submit(desc_rx);
1112 desc_tx->tx_submit(desc_tx);
1113 spin_unlock_irqrestore(&data->lock, flags);
1114
1115 /* reset transfer complete flag */
1116 data->transfer_complete = false;
1117}
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001118
1119static void pch_spi_process_messages(struct work_struct *pwork)
1120{
Wei Yongjuncd8d9842013-04-27 14:06:00 +08001121 struct spi_message *pmsg, *tmp;
Grant Likely65308c42010-09-29 17:31:34 +09001122 struct pch_spi_data *data;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001123 int bpw;
1124
Grant Likely65308c42010-09-29 17:31:34 +09001125 data = container_of(pwork, struct pch_spi_data, work);
Grant Likely8e41b522010-10-13 23:03:15 -06001126 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001127
1128 spin_lock(&data->lock);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001129 /* check if suspend has been initiated;if yes flush queue */
Grant Likely65308c42010-09-29 17:31:34 +09001130 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +03001131 dev_dbg(&data->master->dev,
1132 "%s suspend/remove initiated, flushing queue\n", __func__);
Wei Yongjuncd8d9842013-04-27 14:06:00 +08001133 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001134 pmsg->status = -EIO;
1135
Sachin Kamatf5d8ee32013-05-31 17:17:48 +05301136 if (pmsg->complete) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001137 spin_unlock(&data->lock);
1138 pmsg->complete(pmsg->context);
1139 spin_lock(&data->lock);
1140 }
1141
1142 /* delete from queue */
1143 list_del_init(&pmsg->queue);
1144 }
1145
1146 spin_unlock(&data->lock);
1147 return;
1148 }
1149
1150 data->bcurrent_msg_processing = true;
1151 dev_dbg(&data->master->dev,
1152 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1153
1154 /* Get the message from the queue and delete it from there. */
Grant Likely65308c42010-09-29 17:31:34 +09001155 data->current_msg = list_entry(data->queue.next, struct spi_message,
1156 queue);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001157
1158 list_del_init(&data->current_msg->queue);
1159
1160 data->current_msg->status = 0;
1161
1162 pch_spi_select_chip(data, data->current_msg->spi);
1163
1164 spin_unlock(&data->lock);
1165
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001166 if (data->use_dma)
1167 pch_spi_request_dma(data,
1168 data->current_msg->spi->bits_per_word);
Tomoya MORINAGA8b7aa962011-09-06 17:16:35 +09001169 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001170 do {
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +09001171 int cnt;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001172 /* If we are already processing a message get the next
1173 transfer structure from the message otherwise retrieve
1174 the 1st transfer request from the message. */
1175 spin_lock(&data->lock);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001176 if (data->cur_trans == NULL) {
1177 data->cur_trans =
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001178 list_entry(data->current_msg->transfers.next,
1179 struct spi_transfer, transfer_list);
Markus Elfringb9963562017-01-13 16:36:09 +01001180 dev_dbg(&data->master->dev,
1181 "%s :Getting 1st transfer message\n",
1182 __func__);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001183 } else {
1184 data->cur_trans =
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001185 list_entry(data->cur_trans->transfer_list.next,
1186 struct spi_transfer, transfer_list);
Markus Elfringb9963562017-01-13 16:36:09 +01001187 dev_dbg(&data->master->dev,
1188 "%s :Getting next transfer message\n",
1189 __func__);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001190 }
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001191 spin_unlock(&data->lock);
1192
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +09001193 if (!data->cur_trans->len)
1194 goto out;
1195 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1196 data->save_total_len = data->cur_trans->len;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001197 if (data->use_dma) {
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +09001198 int i;
1199 char *save_rx_buf = data->cur_trans->rx_buf;
1200 for (i = 0; i < cnt; i ++) {
1201 pch_spi_handle_dma(data, &bpw);
Tomoya MORINAGA0f57e162011-12-09 13:13:29 +09001202 if (!pch_spi_start_transfer(data)) {
1203 data->transfer_complete = true;
1204 data->current_msg->status = -EIO;
1205 data->current_msg->complete
1206 (data->current_msg->context);
1207 data->bcurrent_msg_processing = false;
1208 data->current_msg = NULL;
1209 data->cur_trans = NULL;
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +09001210 goto out;
Tomoya MORINAGA0f57e162011-12-09 13:13:29 +09001211 }
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +09001212 pch_spi_copy_rx_data_for_dma(data, bpw);
1213 }
1214 data->cur_trans->rx_buf = save_rx_buf;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001215 } else {
1216 pch_spi_set_tx(data, &bpw);
1217 pch_spi_set_ir(data);
1218 pch_spi_copy_rx_data(data, bpw);
1219 kfree(data->pkt_rx_buff);
1220 data->pkt_rx_buff = NULL;
1221 kfree(data->pkt_tx_buff);
1222 data->pkt_tx_buff = NULL;
1223 }
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001224 /* increment message count */
Tomoya MORINAGA7d05b3e2011-12-09 13:13:27 +09001225 data->cur_trans->len = data->save_total_len;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001226 data->current_msg->actual_length += data->cur_trans->len;
1227
1228 dev_dbg(&data->master->dev,
1229 "%s:data->current_msg->actual_length=%d\n",
1230 __func__, data->current_msg->actual_length);
1231
Alexandru Ardeleane74dc5c2019-09-26 13:51:37 +03001232 spi_transfer_delay_exec(data->cur_trans);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001233
1234 spin_lock(&data->lock);
1235
1236 /* No more transfer in this message. */
1237 if ((data->cur_trans->transfer_list.next) ==
1238 &(data->current_msg->transfers)) {
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001239 pch_spi_nomore_transfer(data);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001240 }
1241
1242 spin_unlock(&data->lock);
1243
Grant Likely65308c42010-09-29 17:31:34 +09001244 } while (data->cur_trans != NULL);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001245
Tomoya MORINAGA25e803f2011-09-06 17:16:37 +09001246out:
Tomoya MORINAGA8b7aa962011-09-06 17:16:35 +09001247 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001248 if (data->use_dma)
1249 pch_spi_release_dma(data);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001250}
1251
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001252static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1253 struct pch_spi_data *data)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001254{
1255 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1256
Bhaktipriya Shridhar0d357732016-07-10 19:42:13 +05301257 flush_work(&data->work);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001258}
1259
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001260static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1261 struct pch_spi_data *data)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001262{
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001263 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1264
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001265 /* reset PCH SPI h/w */
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001266 pch_spi_reset(data->master);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001267 dev_dbg(&board_dat->pdev->dev,
1268 "%s pch_spi_reset invoked successfully\n", __func__);
1269
Grant Likely65308c42010-09-29 17:31:34 +09001270 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001271
Christophe JAILLET9677e7d2016-11-18 23:49:27 +01001272 return 0;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001273}
1274
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001275static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1276 struct pch_spi_data *data)
1277{
1278 struct pch_spi_dma_ctrl *dma;
1279
1280 dma = &data->dma;
1281 if (dma->tx_buf_dma)
1282 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1283 dma->tx_buf_virt, dma->tx_buf_dma);
1284 if (dma->rx_buf_dma)
1285 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1286 dma->rx_buf_virt, dma->rx_buf_dma);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001287}
1288
Aditya Pakkif37d8e62019-03-13 11:55:41 -05001289static int pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001290 struct pch_spi_data *data)
1291{
1292 struct pch_spi_dma_ctrl *dma;
Aditya Pakkif37d8e62019-03-13 11:55:41 -05001293 int ret;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001294
1295 dma = &data->dma;
Aditya Pakkif37d8e62019-03-13 11:55:41 -05001296 ret = 0;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001297 /* Get Consistent memory for Tx DMA */
1298 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1299 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
Aditya Pakkif37d8e62019-03-13 11:55:41 -05001300 if (!dma->tx_buf_virt)
1301 ret = -ENOMEM;
1302
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001303 /* Get Consistent memory for Rx DMA */
1304 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1305 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
Aditya Pakkif37d8e62019-03-13 11:55:41 -05001306 if (!dma->rx_buf_virt)
1307 ret = -ENOMEM;
1308
1309 return ret;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001310}
1311
Grant Likelyfd4a3192012-12-07 16:57:14 +00001312static int pch_spi_pd_probe(struct platform_device *plat_dev)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001313{
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001314 int ret;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001315 struct spi_master *master;
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001316 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1317 struct pch_spi_data *data;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001318
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001319 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1320
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001321 master = spi_alloc_master(&board_dat->pdev->dev,
1322 sizeof(struct pch_spi_data));
1323 if (!master) {
1324 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1325 plat_dev->id);
1326 return -ENOMEM;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001327 }
1328
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001329 data = spi_master_get_devdata(master);
1330 data->master = master;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001331
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001332 platform_set_drvdata(plat_dev, data);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001333
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001334 /* baseaddress + address offset) */
1335 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1336 PCH_ADDRESS_SIZE * plat_dev->id;
Dan Carpenter95538212013-09-24 10:54:51 +03001337 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001338 if (!data->io_remap_addr) {
1339 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1340 ret = -ENOMEM;
1341 goto err_pci_iomap;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001342 }
Dan Carpenter95538212013-09-24 10:54:51 +03001343 data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001344
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001345 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1346 plat_dev->id, data->io_remap_addr);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001347
1348 /* initialize members of SPI master */
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001349 master->num_chipselect = PCH_MAX_CS;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001350 master->transfer = pch_spi_transfer;
Tomoya MORINAGAf258b442011-12-09 13:13:28 +09001351 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
Stephen Warren24778be2013-05-21 20:36:35 -06001352 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
Axel Linfe3a1ad2014-02-10 22:26:40 +08001353 master->max_speed_hz = PCH_MAX_BAUDRATE;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001354
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001355 data->board_dat = board_dat;
1356 data->plat_dev = plat_dev;
1357 data->n_curnt_chip = 255;
1358 data->status = STATUS_RUNNING;
1359 data->ch = plat_dev->id;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001360 data->use_dma = use_dma;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001361
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001362 INIT_LIST_HEAD(&data->queue);
1363 spin_lock_init(&data->lock);
1364 INIT_WORK(&data->work, pch_spi_process_messages);
1365 init_waitqueue_head(&data->wait);
Grant Likely65308c42010-09-29 17:31:34 +09001366
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001367 ret = pch_spi_get_resources(board_dat, data);
1368 if (ret) {
1369 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001370 goto err_spi_get_resources;
1371 }
1372
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001373 ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1374 IRQF_SHARED, KBUILD_MODNAME, data);
1375 if (ret) {
1376 dev_err(&plat_dev->dev,
1377 "%s request_irq failed\n", __func__);
1378 goto err_request_irq;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001379 }
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001380 data->irq_reg_sts = true;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001381
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001382 pch_spi_set_master_mode(master);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001383
Alexander Stein7995d742014-02-26 16:31:19 +01001384 if (use_dma) {
1385 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
Aditya Pakkif37d8e62019-03-13 11:55:41 -05001386 ret = pch_alloc_dma_buf(board_dat, data);
1387 if (ret)
1388 goto err_spi_register_master;
Alexander Stein7995d742014-02-26 16:31:19 +01001389 }
1390
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001391 ret = spi_register_master(master);
1392 if (ret != 0) {
1393 dev_err(&plat_dev->dev,
1394 "%s spi_register_master FAILED\n", __func__);
1395 goto err_spi_register_master;
1396 }
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001397
1398 return 0;
1399
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001400err_spi_register_master:
Alexander Stein7995d742014-02-26 16:31:19 +01001401 pch_free_dma_buf(board_dat, data);
Lars-Peter Clausene1e57622013-05-20 17:54:35 +02001402 free_irq(board_dat->pdev->irq, data);
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001403err_request_irq:
1404 pch_spi_free_resources(board_dat, data);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001405err_spi_get_resources:
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001406 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1407err_pci_iomap:
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001408 spi_master_put(master);
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001409
1410 return ret;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001411}
1412
Grant Likelyfd4a3192012-12-07 16:57:14 +00001413static int pch_spi_pd_remove(struct platform_device *plat_dev)
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001414{
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001415 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1416 struct pch_spi_data *data = platform_get_drvdata(plat_dev);
Grant Likely65308c42010-09-29 17:31:34 +09001417 int count;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001418 unsigned long flags;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001419
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001420 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1421 __func__, plat_dev->id, board_dat->pdev->irq);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001422
1423 if (use_dma)
1424 pch_free_dma_buf(board_dat, data);
1425
Grant Likely65308c42010-09-29 17:31:34 +09001426 /* check for any pending messages; no action is taken if the queue
1427 * is still full; but at least we tried. Unload anyway */
1428 count = 500;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001429 spin_lock_irqsave(&data->lock, flags);
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001430 data->status = STATUS_EXITING;
1431 while ((list_empty(&data->queue) == 0) && --count) {
Grant Likely65308c42010-09-29 17:31:34 +09001432 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1433 __func__);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001434 spin_unlock_irqrestore(&data->lock, flags);
Grant Likely65308c42010-09-29 17:31:34 +09001435 msleep(PCH_SLEEP_TIME);
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001436 spin_lock_irqsave(&data->lock, flags);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001437 }
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001438 spin_unlock_irqrestore(&data->lock, flags);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001439
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001440 pch_spi_free_resources(board_dat, data);
1441 /* disable interrupts & free IRQ */
1442 if (data->irq_reg_sts) {
1443 /* disable interrupts */
1444 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1445 data->irq_reg_sts = false;
1446 free_irq(board_dat->pdev->irq, data);
1447 }
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001448
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001449 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1450 spi_unregister_master(data->master);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001451
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001452 return 0;
1453}
1454#ifdef CONFIG_PM
1455static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1456 pm_message_t state)
1457{
1458 u8 count;
1459 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1460 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001461
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001462 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001463
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001464 if (!board_dat) {
1465 dev_err(&pd_dev->dev,
1466 "%s pci_get_drvdata returned NULL\n", __func__);
1467 return -EFAULT;
1468 }
1469
1470 /* check if the current message is processed:
1471 Only after thats done the transfer will be suspended */
1472 count = 255;
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001473 while ((--count) > 0) {
1474 if (!(data->bcurrent_msg_processing))
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001475 break;
1476 msleep(PCH_SLEEP_TIME);
1477 }
1478
1479 /* Free IRQ */
1480 if (data->irq_reg_sts) {
1481 /* disable all interrupts */
1482 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1483 pch_spi_reset(data->master);
1484 free_irq(board_dat->pdev->irq, data);
1485
1486 data->irq_reg_sts = false;
1487 dev_dbg(&pd_dev->dev,
1488 "%s free_irq invoked successfully.\n", __func__);
1489 }
1490
1491 return 0;
1492}
1493
1494static int pch_spi_pd_resume(struct platform_device *pd_dev)
1495{
1496 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1497 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1498 int retval;
1499
1500 if (!board_dat) {
1501 dev_err(&pd_dev->dev,
1502 "%s pci_get_drvdata returned NULL\n", __func__);
1503 return -EFAULT;
1504 }
1505
1506 if (!data->irq_reg_sts) {
1507 /* register IRQ */
1508 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1509 IRQF_SHARED, KBUILD_MODNAME, data);
1510 if (retval < 0) {
1511 dev_err(&pd_dev->dev,
1512 "%s request_irq failed\n", __func__);
1513 return retval;
1514 }
1515
1516 /* reset PCH SPI h/w */
1517 pch_spi_reset(data->master);
1518 pch_spi_set_master_mode(data->master);
1519 data->irq_reg_sts = true;
1520 }
1521 return 0;
1522}
1523#else
1524#define pch_spi_pd_suspend NULL
1525#define pch_spi_pd_resume NULL
1526#endif
1527
1528static struct platform_driver pch_spi_pd_driver = {
1529 .driver = {
1530 .name = "pch-spi",
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001531 },
1532 .probe = pch_spi_pd_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +00001533 .remove = pch_spi_pd_remove,
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001534 .suspend = pch_spi_pd_suspend,
1535 .resume = pch_spi_pd_resume
1536};
1537
Axel Linb86e81d2014-03-24 15:46:55 +08001538static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001539{
1540 struct pch_spi_board_data *board_dat;
1541 struct platform_device *pd_dev = NULL;
1542 int retval;
1543 int i;
1544 struct pch_pd_dev_save *pd_dev_save;
1545
Markus Elfringbaa35f52017-01-13 15:46:35 +01001546 pd_dev_save = kzalloc(sizeof(*pd_dev_save), GFP_KERNEL);
Jingoo Hanfe75cbc2014-04-29 17:23:10 +09001547 if (!pd_dev_save)
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001548 return -ENOMEM;
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001549
Markus Elfringbaa35f52017-01-13 15:46:35 +01001550 board_dat = kzalloc(sizeof(*board_dat), GFP_KERNEL);
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001551 if (!board_dat) {
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001552 retval = -ENOMEM;
1553 goto err_no_mem;
1554 }
1555
1556 retval = pci_request_regions(pdev, KBUILD_MODNAME);
1557 if (retval) {
1558 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1559 goto pci_request_regions;
1560 }
1561
1562 board_dat->pdev = pdev;
1563 board_dat->num = id->driver_data;
1564 pd_dev_save->num = id->driver_data;
1565 pd_dev_save->board_dat = board_dat;
1566
1567 retval = pci_enable_device(pdev);
1568 if (retval) {
1569 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1570 goto pci_enable_device;
1571 }
1572
1573 for (i = 0; i < board_dat->num; i++) {
1574 pd_dev = platform_device_alloc("pch-spi", i);
1575 if (!pd_dev) {
1576 dev_err(&pdev->dev, "platform_device_alloc failed\n");
Wei Yongjunbac902d2013-05-22 10:55:41 +08001577 retval = -ENOMEM;
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001578 goto err_platform_device;
1579 }
1580 pd_dev_save->pd_save[i] = pd_dev;
1581 pd_dev->dev.parent = &pdev->dev;
1582
1583 retval = platform_device_add_data(pd_dev, board_dat,
1584 sizeof(*board_dat));
1585 if (retval) {
1586 dev_err(&pdev->dev,
1587 "platform_device_add_data failed\n");
1588 platform_device_put(pd_dev);
1589 goto err_platform_device;
1590 }
1591
1592 retval = platform_device_add(pd_dev);
1593 if (retval) {
1594 dev_err(&pdev->dev, "platform_device_add failed\n");
1595 platform_device_put(pd_dev);
1596 goto err_platform_device;
1597 }
1598 }
1599
1600 pci_set_drvdata(pdev, pd_dev_save);
1601
1602 return 0;
1603
1604err_platform_device:
Axel Linb86e81d2014-03-24 15:46:55 +08001605 while (--i >= 0)
1606 platform_device_unregister(pd_dev_save->pd_save[i]);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001607 pci_disable_device(pdev);
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001608pci_enable_device:
1609 pci_release_regions(pdev);
1610pci_request_regions:
1611 kfree(board_dat);
1612err_no_mem:
1613 kfree(pd_dev_save);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001614
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001615 return retval;
1616}
1617
Grant Likelyfd4a3192012-12-07 16:57:14 +00001618static void pch_spi_remove(struct pci_dev *pdev)
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001619{
1620 int i;
1621 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1622
1623 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1624
1625 for (i = 0; i < pd_dev_save->num; i++)
1626 platform_device_unregister(pd_dev_save->pd_save[i]);
1627
1628 pci_disable_device(pdev);
1629 pci_release_regions(pdev);
1630 kfree(pd_dev_save->board_dat);
1631 kfree(pd_dev_save);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001632}
1633
1634#ifdef CONFIG_PM
1635static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1636{
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001637 int retval;
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001638 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001639
1640 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1641
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001642 pd_dev_save->board_dat->suspend_sts = true;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001643
1644 /* save config space */
1645 retval = pci_save_state(pdev);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001646 if (retval == 0) {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001647 pci_enable_wake(pdev, PCI_D3hot, 0);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001648 pci_disable_device(pdev);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001649 pci_set_power_state(pdev, PCI_D3hot);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001650 } else {
1651 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1652 }
1653
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001654 return retval;
1655}
1656
1657static int pch_spi_resume(struct pci_dev *pdev)
1658{
1659 int retval;
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001660 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001661 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1662
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001663 pci_set_power_state(pdev, PCI_D0);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001664 pci_restore_state(pdev);
1665
1666 retval = pci_enable_device(pdev);
1667 if (retval < 0) {
1668 dev_err(&pdev->dev,
1669 "%s pci_enable_device failed\n", __func__);
1670 } else {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001671 pci_enable_wake(pdev, PCI_D3hot, 0);
1672
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001673 /* set suspend status to false */
1674 pd_dev_save->board_dat->suspend_sts = false;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001675 }
1676
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001677 return retval;
1678}
1679#else
1680#define pch_spi_suspend NULL
1681#define pch_spi_resume NULL
1682
1683#endif
1684
Danny Kukawkac88db232012-02-02 14:20:30 +01001685static struct pci_driver pch_spi_pcidev_driver = {
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001686 .name = "pch_spi",
1687 .id_table = pch_spi_pcidev_id,
1688 .probe = pch_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +00001689 .remove = pch_spi_remove,
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001690 .suspend = pch_spi_suspend,
1691 .resume = pch_spi_resume,
1692};
1693
1694static int __init pch_spi_init(void)
1695{
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001696 int ret;
1697 ret = platform_driver_register(&pch_spi_pd_driver);
1698 if (ret)
1699 return ret;
1700
Danny Kukawkac88db232012-02-02 14:20:30 +01001701 ret = pci_register_driver(&pch_spi_pcidev_driver);
Wei Yongjun0113f222013-04-25 15:18:02 +08001702 if (ret) {
1703 platform_driver_unregister(&pch_spi_pd_driver);
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001704 return ret;
Wei Yongjun0113f222013-04-25 15:18:02 +08001705 }
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001706
1707 return 0;
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001708}
1709module_init(pch_spi_init);
1710
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001711static void __exit pch_spi_exit(void)
1712{
Danny Kukawkac88db232012-02-02 14:20:30 +01001713 pci_unregister_driver(&pch_spi_pcidev_driver);
Tomoya MORINAGAf016aeb2011-06-07 14:50:10 +09001714 platform_driver_unregister(&pch_spi_pd_driver);
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001715}
1716module_exit(pch_spi_exit);
1717
Tomoya MORINAGAc37f3c22011-06-07 14:50:11 +09001718module_param(use_dma, int, 0644);
1719MODULE_PARM_DESC(use_dma,
1720 "to use DMA for data transfers pass 1 else 0; default 1");
1721
Masayuki Ohtakee8b17b52010-10-08 12:44:49 -06001722MODULE_LICENSE("GPL");
Tomoya MORINAGA2b246282011-10-28 09:35:22 +09001723MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
Alexander Stein2f1603c2013-08-12 17:26:27 +02001724MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1725