Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2014-2017 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #ifndef _INTEL_DEVICE_INFO_H_ |
| 26 | #define _INTEL_DEVICE_INFO_H_ |
| 27 | |
Chris Wilson | 4bdafb9 | 2018-09-26 21:12:22 +0100 | [diff] [blame] | 28 | #include <uapi/drm/i915_drm.h> |
| 29 | |
Jani Nikula | 439c8dc | 2021-03-26 15:21:33 +0200 | [diff] [blame] | 30 | #include "intel_step.h" |
| 31 | |
Chris Wilson | 112ed2d | 2019-04-24 18:48:39 +0100 | [diff] [blame] | 32 | #include "gt/intel_engine_types.h" |
| 33 | #include "gt/intel_context_types.h" |
| 34 | #include "gt/intel_sseu.h" |
| 35 | |
Fei Yang | 5e352e3 | 2023-05-09 09:51:59 -0700 | [diff] [blame] | 36 | #include "gem/i915_gem_object_types.h" |
| 37 | |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 38 | struct drm_printer; |
| 39 | struct drm_i915_private; |
Matt Roper | 70fff19 | 2022-09-06 16:49:25 -0700 | [diff] [blame] | 40 | struct intel_gt_definition; |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 41 | |
| 42 | /* Keep in gen based order, and chronological order within a gen */ |
| 43 | enum intel_platform { |
| 44 | INTEL_PLATFORM_UNINITIALIZED = 0, |
| 45 | /* gen2 */ |
| 46 | INTEL_I830, |
| 47 | INTEL_I845G, |
| 48 | INTEL_I85X, |
| 49 | INTEL_I865G, |
| 50 | /* gen3 */ |
| 51 | INTEL_I915G, |
| 52 | INTEL_I915GM, |
| 53 | INTEL_I945G, |
| 54 | INTEL_I945GM, |
| 55 | INTEL_G33, |
| 56 | INTEL_PINEVIEW, |
| 57 | /* gen4 */ |
| 58 | INTEL_I965G, |
| 59 | INTEL_I965GM, |
| 60 | INTEL_G45, |
| 61 | INTEL_GM45, |
| 62 | /* gen5 */ |
| 63 | INTEL_IRONLAKE, |
| 64 | /* gen6 */ |
| 65 | INTEL_SANDYBRIDGE, |
| 66 | /* gen7 */ |
| 67 | INTEL_IVYBRIDGE, |
| 68 | INTEL_VALLEYVIEW, |
| 69 | INTEL_HASWELL, |
| 70 | /* gen8 */ |
| 71 | INTEL_BROADWELL, |
| 72 | INTEL_CHERRYVIEW, |
| 73 | /* gen9 */ |
| 74 | INTEL_SKYLAKE, |
| 75 | INTEL_BROXTON, |
| 76 | INTEL_KABYLAKE, |
| 77 | INTEL_GEMINILAKE, |
| 78 | INTEL_COFFEELAKE, |
Chris Wilson | 5f4ae27 | 2020-06-02 15:05:40 +0100 | [diff] [blame] | 79 | INTEL_COMETLAKE, |
Rodrigo Vivi | 41231001 | 2018-01-11 16:00:04 -0200 | [diff] [blame] | 80 | /* gen11 */ |
| 81 | INTEL_ICELAKE, |
Bob Paauwe | 897f296 | 2019-03-22 10:58:43 -0700 | [diff] [blame] | 82 | INTEL_ELKHARTLAKE, |
Tejas Upadhyay | 24ea098 | 2020-10-14 00:59:48 +0530 | [diff] [blame] | 83 | INTEL_JASPERLAKE, |
Daniele Ceraolo Spurio | abd3a0f | 2019-07-11 10:30:56 -0700 | [diff] [blame] | 84 | /* gen12 */ |
| 85 | INTEL_TIGERLAKE, |
Matt Roper | 123f62d | 2020-05-04 15:52:06 -0700 | [diff] [blame] | 86 | INTEL_ROCKETLAKE, |
Abdiel Janulgue | 05e2658 | 2020-07-13 11:23:17 -0700 | [diff] [blame] | 87 | INTEL_DG1, |
Caz Yokoyama | 0883d63 | 2021-01-19 11:29:31 -0800 | [diff] [blame] | 88 | INTEL_ALDERLAKE_S, |
Clinton Taylor | bdd27ca | 2021-05-06 19:19:23 +0300 | [diff] [blame] | 89 | INTEL_ALDERLAKE_P, |
Matt Roper | 9e22cfc | 2021-07-21 15:30:28 -0700 | [diff] [blame] | 90 | INTEL_DG2, |
Radhakrishna Sripada | bcf9b29 | 2022-07-07 17:03:34 -0700 | [diff] [blame] | 91 | INTEL_METEORLAKE, |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 92 | INTEL_MAX_PLATFORMS |
| 93 | }; |
| 94 | |
Tvrtko Ursulin | 805446c | 2019-03-27 14:23:28 +0000 | [diff] [blame] | 95 | /* |
| 96 | * Subplatform bits share the same namespace per parent platform. In other words |
| 97 | * it is fine for the same bit to be used on multiple parent platforms. |
| 98 | */ |
| 99 | |
Matt Roper | 86df414 | 2022-01-20 15:50:16 -0800 | [diff] [blame] | 100 | #define INTEL_SUBPLATFORM_BITS (3) |
Tvrtko Ursulin | 56afa70 | 2021-01-21 16:19:36 +0000 | [diff] [blame] | 101 | #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) |
Tvrtko Ursulin | 805446c | 2019-03-27 14:23:28 +0000 | [diff] [blame] | 102 | |
| 103 | /* HSW/BDW/SKL/KBL/CFL */ |
| 104 | #define INTEL_SUBPLATFORM_ULT (0) |
| 105 | #define INTEL_SUBPLATFORM_ULX (1) |
Tvrtko Ursulin | 805446c | 2019-03-27 14:23:28 +0000 | [diff] [blame] | 106 | |
Lucas De Marchi | 244dba4 | 2021-07-28 14:59:42 -0700 | [diff] [blame] | 107 | /* ICL */ |
Tvrtko Ursulin | 805446c | 2019-03-27 14:23:28 +0000 | [diff] [blame] | 108 | #define INTEL_SUBPLATFORM_PORTF (0) |
| 109 | |
José Roberto de Souza | b9ef893 | 2022-02-22 06:14:24 -0800 | [diff] [blame] | 110 | /* TGL */ |
| 111 | #define INTEL_SUBPLATFORM_UY (0) |
| 112 | |
Matt Roper | 9e22cfc | 2021-07-21 15:30:28 -0700 | [diff] [blame] | 113 | /* DG2 */ |
| 114 | #define INTEL_SUBPLATFORM_G10 0 |
| 115 | #define INTEL_SUBPLATFORM_G11 1 |
Matt Roper | 86df414 | 2022-01-20 15:50:16 -0800 | [diff] [blame] | 116 | #define INTEL_SUBPLATFORM_G12 2 |
Matt Roper | 9e22cfc | 2021-07-21 15:30:28 -0700 | [diff] [blame] | 117 | |
Matt Atwood | 72c3c8d | 2022-04-18 11:51:57 +0530 | [diff] [blame] | 118 | /* ADL */ |
| 119 | #define INTEL_SUBPLATFORM_RPL 0 |
Anusha Srivatsa | 52407c2 | 2021-12-02 22:35:43 -0800 | [diff] [blame] | 120 | |
Tejas Upadhyay | 7e28d0b | 2021-12-10 10:48:02 +0530 | [diff] [blame] | 121 | /* ADL-P */ |
Matt Atwood | 72c3c8d | 2022-04-18 11:51:57 +0530 | [diff] [blame] | 122 | /* |
| 123 | * As #define INTEL_SUBPLATFORM_RPL 0 will apply |
| 124 | * here too, SUBPLATFORM_N will have different |
| 125 | * bit set |
| 126 | */ |
| 127 | #define INTEL_SUBPLATFORM_N 1 |
Chaitanya Kumar Borah | 61b795a | 2023-01-30 15:38:05 +0530 | [diff] [blame] | 128 | #define INTEL_SUBPLATFORM_RPLU 2 |
Tejas Upadhyay | 7e28d0b | 2021-12-10 10:48:02 +0530 | [diff] [blame] | 129 | |
Chris Wilson | cbecbcc | 2019-03-14 22:38:36 +0000 | [diff] [blame] | 130 | enum intel_ppgtt_type { |
Chris Wilson | 4bdafb9 | 2018-09-26 21:12:22 +0100 | [diff] [blame] | 131 | INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, |
| 132 | INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, |
| 133 | INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, |
Chris Wilson | 4bdafb9 | 2018-09-26 21:12:22 +0100 | [diff] [blame] | 134 | }; |
| 135 | |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 136 | #define DEV_INFO_FOR_EACH_FLAG(func) \ |
| 137 | func(is_mobile); \ |
| 138 | func(is_lp); \ |
Jani Nikula | 7ef5ef5 | 2019-05-06 16:48:01 +0300 | [diff] [blame] | 139 | func(require_force_probe); \ |
José Roberto de Souza | dc90fe3 | 2019-10-24 12:51:19 -0700 | [diff] [blame] | 140 | func(is_dgfx); \ |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 141 | /* Keep has_* in alphabetical order */ \ |
| 142 | func(has_64bit_reloc); \ |
Stuart Summers | c83125b | 2021-12-08 19:46:10 +0530 | [diff] [blame] | 143 | func(has_64k_pages); \ |
Chris Wilson | 55277e1 | 2019-01-03 11:21:04 +0000 | [diff] [blame] | 144 | func(gpu_reset_clobbers_display); \ |
Tvrtko Ursulin | b409db0 | 2022-05-19 10:08:00 +0100 | [diff] [blame] | 145 | func(has_reset_engine); \ |
Stuart Summers | 1eb3133 | 2022-05-10 23:02:26 -0700 | [diff] [blame] | 146 | func(has_3d_pipeline); \ |
CQ Tang | 5e3094c | 2022-02-19 00:17:50 +0530 | [diff] [blame] | 147 | func(has_flat_ccs); \ |
Michel Thierry | a7a7a0e | 2019-07-30 11:04:06 -0700 | [diff] [blame] | 148 | func(has_global_mocs); \ |
Matt Roper | c2c7075 | 2022-09-15 18:46:46 -0700 | [diff] [blame] | 149 | func(has_gmd_id); \ |
Tvrtko Ursulin | 39921e5 | 2022-05-19 10:08:02 +0100 | [diff] [blame] | 150 | func(has_gt_uc); \ |
Tomas Winkler | 1e3dc1d | 2022-04-19 12:33:08 -0700 | [diff] [blame] | 151 | func(has_heci_pxp); \ |
| 152 | func(has_heci_gscfi); \ |
Daniele Ceraolo Spurio | db3b3f3 | 2022-01-20 13:29:47 -0800 | [diff] [blame] | 153 | func(has_guc_deprivilege); \ |
Jonathan Cavitt | 29e66833 | 2023-10-17 11:08:00 -0700 | [diff] [blame] | 154 | func(has_guc_tlb_invalidation); \ |
Ayaz A Siddiqui | 9d67edb | 2022-05-05 14:38:03 -0700 | [diff] [blame] | 155 | func(has_l3_ccs_read); \ |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 156 | func(has_l3_dpf); \ |
| 157 | func(has_llc); \ |
| 158 | func(has_logical_ring_contexts); \ |
Tvrtko Ursulin | 3d6c72b | 2022-05-19 10:07:59 +0100 | [diff] [blame] | 159 | func(has_logical_ring_elsq); \ |
Ashutosh Dixit | 85a040b | 2022-05-19 09:57:30 +0100 | [diff] [blame] | 160 | func(has_media_ratio_mode); \ |
Matt Roper | e0d7371 | 2022-06-08 10:07:00 -0700 | [diff] [blame] | 161 | func(has_mslice_steering); \ |
Umesh Nerlige Ramappa | cceb084 | 2022-10-26 22:20:51 +0000 | [diff] [blame] | 162 | func(has_oa_bpc_reporting); \ |
Lionel Landwerlin | 0fa9349 | 2022-10-26 22:21:01 +0000 | [diff] [blame] | 163 | func(has_oa_slice_contrib_limits); \ |
Umesh Nerlige Ramappa | 1cc064d | 2023-03-23 15:58:59 -0700 | [diff] [blame] | 164 | func(has_oam); \ |
Matt Roper | 5ac342e | 2022-06-01 08:07:25 -0700 | [diff] [blame] | 165 | func(has_one_eu_per_fuse_bit); \ |
Daniele Ceraolo Spurio | e6aa713 | 2021-09-24 12:14:38 -0700 | [diff] [blame] | 166 | func(has_pxp); \ |
Tvrtko Ursulin | fdbec9f | 2022-05-19 10:08:01 +0100 | [diff] [blame] | 167 | func(has_rc6); \ |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 168 | func(has_rc6p); \ |
Chris Wilson | 91cbdb8 | 2019-04-19 14:48:36 +0100 | [diff] [blame] | 169 | func(has_rps); \ |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 170 | func(has_runtime_pm); \ |
| 171 | func(has_snoop); \ |
Chris Wilson | 900ccf3 | 2018-07-20 11:19:10 +0100 | [diff] [blame] | 172 | func(has_coherent_ggtt); \ |
Matt Roper | 73c7a8a | 2022-08-26 14:27:18 -0700 | [diff] [blame] | 173 | func(tuning_thread_rr_after_dep); \ |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 174 | func(unfenced_needs_alignment); \ |
José Roberto de Souza | d53db44 | 2018-11-30 15:20:48 -0800 | [diff] [blame] | 175 | func(hws_needs_physical); |
| 176 | |
Radhakrishna Sripada | ef7e222 | 2022-10-11 08:38:50 -0700 | [diff] [blame] | 177 | struct intel_ip_version { |
José Roberto de Souza | a5b7ef2 | 2021-10-19 17:23:51 -0700 | [diff] [blame] | 178 | u8 ver; |
| 179 | u8 rel; |
Matt Roper | c2c7075 | 2022-09-15 18:46:46 -0700 | [diff] [blame] | 180 | u8 step; |
José Roberto de Souza | a5b7ef2 | 2021-10-19 17:23:51 -0700 | [diff] [blame] | 181 | }; |
| 182 | |
Jani Nikula | 2c93e7b | 2022-08-19 15:02:36 +0300 | [diff] [blame] | 183 | struct intel_runtime_info { |
Matt Roper | c2c7075 | 2022-09-15 18:46:46 -0700 | [diff] [blame] | 184 | /* |
| 185 | * Single "graphics" IP version that represents |
| 186 | * render, compute and copy behavior. |
| 187 | */ |
Radhakrishna Sripada | f9e932a | 2022-09-02 15:10:54 -0700 | [diff] [blame] | 188 | struct { |
Radhakrishna Sripada | ef7e222 | 2022-10-11 08:38:50 -0700 | [diff] [blame] | 189 | struct intel_ip_version ip; |
Radhakrishna Sripada | f9e932a | 2022-09-02 15:10:54 -0700 | [diff] [blame] | 190 | } graphics; |
| 191 | struct { |
Radhakrishna Sripada | ef7e222 | 2022-10-11 08:38:50 -0700 | [diff] [blame] | 192 | struct intel_ip_version ip; |
Radhakrishna Sripada | f9e932a | 2022-09-02 15:10:54 -0700 | [diff] [blame] | 193 | } media; |
Jani Nikula | 43ba44a | 2022-08-19 15:02:37 +0300 | [diff] [blame] | 194 | |
Jani Nikula | 2c93e7b | 2022-08-19 15:02:36 +0300 | [diff] [blame] | 195 | /* |
| 196 | * Platform mask is used for optimizing or-ed IS_PLATFORM calls into |
| 197 | * single runtime conditionals, and also to provide groundwork for |
| 198 | * future per platform, or per SKU build optimizations. |
| 199 | * |
| 200 | * Array can be extended when necessary if the corresponding |
| 201 | * BUILD_BUG_ON is hit. |
| 202 | */ |
| 203 | u32 platform_mask[2]; |
| 204 | |
| 205 | u16 device_id; |
Lucas De Marchi | 93babb0 | 2021-04-12 22:09:54 -0700 | [diff] [blame] | 206 | |
Jani Nikula | 2c93e7b | 2022-08-19 15:02:36 +0300 | [diff] [blame] | 207 | u32 rawclk_freq; |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 208 | |
Jani Nikula | 2c93e7b | 2022-08-19 15:02:36 +0300 | [diff] [blame] | 209 | struct intel_step_info step; |
Jani Nikula | e6f1964 | 2022-08-19 15:02:38 +0300 | [diff] [blame] | 210 | |
Jani Nikula | 9d0bad1 | 2022-08-19 15:02:39 +0300 | [diff] [blame] | 211 | unsigned int page_sizes; /* page sizes supported by the HW */ |
Michael J. Ruhl | 31a02eb | 2020-04-17 15:51:07 -0400 | [diff] [blame] | 212 | |
Chris Wilson | cbecbcc | 2019-03-14 22:38:36 +0000 | [diff] [blame] | 213 | enum intel_ppgtt_type ppgtt_type; |
| 214 | unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ |
| 215 | |
Jani Nikula | 39a445b | 2022-08-19 15:02:41 +0300 | [diff] [blame] | 216 | bool has_pooled_eu; |
Jani Nikula | 2c93e7b | 2022-08-19 15:02:36 +0300 | [diff] [blame] | 217 | }; |
| 218 | |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 219 | struct intel_device_info { |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 220 | enum intel_platform platform; |
| 221 | |
Chris Wilson | 4bdafb9 | 2018-09-26 21:12:22 +0100 | [diff] [blame] | 222 | unsigned int dma_mask_size; /* available DMA address bits */ |
Tvrtko Ursulin | 4552f50 | 2018-02-22 11:16:58 +0000 | [diff] [blame] | 223 | |
Matt Roper | 70fff19 | 2022-09-06 16:49:25 -0700 | [diff] [blame] | 224 | const struct intel_gt_definition *extra_gt_list; |
| 225 | |
John Harrison | 938c778 | 2021-07-23 12:10:24 -0700 | [diff] [blame] | 226 | u8 gt; /* GT number, 0 if undefined */ |
| 227 | |
Jani Nikula | 8776711 | 2023-06-27 18:13:59 +0300 | [diff] [blame] | 228 | intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */ |
| 229 | u32 memory_regions; /* regions supported by the HW */ |
| 230 | |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 231 | #define DEFINE_FLAG(name) u8 name:1 |
| 232 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); |
| 233 | #undef DEFINE_FLAG |
José Roberto de Souza | d53db44 | 2018-11-30 15:20:48 -0800 | [diff] [blame] | 234 | |
Tvrtko Ursulin | 805446c | 2019-03-27 14:23:28 +0000 | [diff] [blame] | 235 | /* |
Jani Nikula | 2c93e7b | 2022-08-19 15:02:36 +0300 | [diff] [blame] | 236 | * Initial runtime info. Do not access outside of i915_driver_create(). |
Tvrtko Ursulin | 805446c | 2019-03-27 14:23:28 +0000 | [diff] [blame] | 237 | */ |
Jani Nikula | 2c93e7b | 2022-08-19 15:02:36 +0300 | [diff] [blame] | 238 | const struct intel_runtime_info __runtime; |
Fei Yang | 5e352e3 | 2023-05-09 09:51:59 -0700 | [diff] [blame] | 239 | |
| 240 | u32 cachelevel_to_pat[I915_MAX_CACHE_LEVEL]; |
| 241 | u32 max_pat_index; |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 242 | }; |
| 243 | |
Chris Wilson | 3fed180 | 2018-02-07 21:05:43 +0000 | [diff] [blame] | 244 | struct intel_driver_caps { |
| 245 | unsigned int scheduler; |
Chris Wilson | 481827b | 2018-07-06 11:14:41 +0100 | [diff] [blame] | 246 | bool has_logical_contexts:1; |
Chris Wilson | 3fed180 | 2018-02-07 21:05:43 +0000 | [diff] [blame] | 247 | }; |
| 248 | |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 249 | const char *intel_platform_name(enum intel_platform platform); |
| 250 | |
Jani Nikula | 446a20c | 2023-04-11 13:56:43 +0300 | [diff] [blame] | 251 | void intel_device_info_driver_create(struct drm_i915_private *i915, u16 device_id, |
| 252 | const struct intel_device_info *match_info); |
Matt Roper | c2c7075 | 2022-09-15 18:46:46 -0700 | [diff] [blame] | 253 | void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv); |
Jani Nikula | 1400cc7 | 2018-12-31 16:56:43 +0200 | [diff] [blame] | 254 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); |
Chris Wilson | 7240497 | 2019-12-07 18:29:37 +0000 | [diff] [blame] | 255 | |
Jani Nikula | c7d3c84 | 2022-08-19 15:02:35 +0300 | [diff] [blame] | 256 | void intel_device_info_print(const struct intel_device_info *info, |
| 257 | const struct intel_runtime_info *runtime, |
| 258 | struct drm_printer *p); |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 259 | |
Chris Wilson | 3fed180 | 2018-02-07 21:05:43 +0000 | [diff] [blame] | 260 | void intel_driver_caps_print(const struct intel_driver_caps *caps, |
| 261 | struct drm_printer *p); |
| 262 | |
Michal Wajdeczko | b978520 | 2017-12-21 21:57:32 +0000 | [diff] [blame] | 263 | #endif |