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Michal Wajdeczkob9785202017-12-21 21:57:32 +00001/*
2 * Copyright © 2014-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DEVICE_INFO_H_
26#define _INTEL_DEVICE_INFO_H_
27
Chris Wilson4bdafb92018-09-26 21:12:22 +010028#include <uapi/drm/i915_drm.h>
29
Jani Nikula439c8dc2021-03-26 15:21:33 +020030#include "intel_step.h"
31
Chris Wilson112ed2d2019-04-24 18:48:39 +010032#include "gt/intel_engine_types.h"
33#include "gt/intel_context_types.h"
34#include "gt/intel_sseu.h"
35
Fei Yang5e352e32023-05-09 09:51:59 -070036#include "gem/i915_gem_object_types.h"
37
Michal Wajdeczkob9785202017-12-21 21:57:32 +000038struct drm_printer;
39struct drm_i915_private;
Matt Roper70fff192022-09-06 16:49:25 -070040struct intel_gt_definition;
Michal Wajdeczkob9785202017-12-21 21:57:32 +000041
42/* Keep in gen based order, and chronological order within a gen */
43enum intel_platform {
44 INTEL_PLATFORM_UNINITIALIZED = 0,
45 /* gen2 */
46 INTEL_I830,
47 INTEL_I845G,
48 INTEL_I85X,
49 INTEL_I865G,
50 /* gen3 */
51 INTEL_I915G,
52 INTEL_I915GM,
53 INTEL_I945G,
54 INTEL_I945GM,
55 INTEL_G33,
56 INTEL_PINEVIEW,
57 /* gen4 */
58 INTEL_I965G,
59 INTEL_I965GM,
60 INTEL_G45,
61 INTEL_GM45,
62 /* gen5 */
63 INTEL_IRONLAKE,
64 /* gen6 */
65 INTEL_SANDYBRIDGE,
66 /* gen7 */
67 INTEL_IVYBRIDGE,
68 INTEL_VALLEYVIEW,
69 INTEL_HASWELL,
70 /* gen8 */
71 INTEL_BROADWELL,
72 INTEL_CHERRYVIEW,
73 /* gen9 */
74 INTEL_SKYLAKE,
75 INTEL_BROXTON,
76 INTEL_KABYLAKE,
77 INTEL_GEMINILAKE,
78 INTEL_COFFEELAKE,
Chris Wilson5f4ae272020-06-02 15:05:40 +010079 INTEL_COMETLAKE,
Rodrigo Vivi412310012018-01-11 16:00:04 -020080 /* gen11 */
81 INTEL_ICELAKE,
Bob Paauwe897f2962019-03-22 10:58:43 -070082 INTEL_ELKHARTLAKE,
Tejas Upadhyay24ea0982020-10-14 00:59:48 +053083 INTEL_JASPERLAKE,
Daniele Ceraolo Spurioabd3a0f2019-07-11 10:30:56 -070084 /* gen12 */
85 INTEL_TIGERLAKE,
Matt Roper123f62d2020-05-04 15:52:06 -070086 INTEL_ROCKETLAKE,
Abdiel Janulgue05e26582020-07-13 11:23:17 -070087 INTEL_DG1,
Caz Yokoyama0883d632021-01-19 11:29:31 -080088 INTEL_ALDERLAKE_S,
Clinton Taylorbdd27ca2021-05-06 19:19:23 +030089 INTEL_ALDERLAKE_P,
Matt Roper9e22cfc2021-07-21 15:30:28 -070090 INTEL_DG2,
Radhakrishna Sripadabcf9b292022-07-07 17:03:34 -070091 INTEL_METEORLAKE,
Michal Wajdeczkob9785202017-12-21 21:57:32 +000092 INTEL_MAX_PLATFORMS
93};
94
Tvrtko Ursulin805446c2019-03-27 14:23:28 +000095/*
96 * Subplatform bits share the same namespace per parent platform. In other words
97 * it is fine for the same bit to be used on multiple parent platforms.
98 */
99
Matt Roper86df4142022-01-20 15:50:16 -0800100#define INTEL_SUBPLATFORM_BITS (3)
Tvrtko Ursulin56afa702021-01-21 16:19:36 +0000101#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
Tvrtko Ursulin805446c2019-03-27 14:23:28 +0000102
103/* HSW/BDW/SKL/KBL/CFL */
104#define INTEL_SUBPLATFORM_ULT (0)
105#define INTEL_SUBPLATFORM_ULX (1)
Tvrtko Ursulin805446c2019-03-27 14:23:28 +0000106
Lucas De Marchi244dba42021-07-28 14:59:42 -0700107/* ICL */
Tvrtko Ursulin805446c2019-03-27 14:23:28 +0000108#define INTEL_SUBPLATFORM_PORTF (0)
109
José Roberto de Souzab9ef8932022-02-22 06:14:24 -0800110/* TGL */
111#define INTEL_SUBPLATFORM_UY (0)
112
Matt Roper9e22cfc2021-07-21 15:30:28 -0700113/* DG2 */
114#define INTEL_SUBPLATFORM_G10 0
115#define INTEL_SUBPLATFORM_G11 1
Matt Roper86df4142022-01-20 15:50:16 -0800116#define INTEL_SUBPLATFORM_G12 2
Matt Roper9e22cfc2021-07-21 15:30:28 -0700117
Matt Atwood72c3c8d2022-04-18 11:51:57 +0530118/* ADL */
119#define INTEL_SUBPLATFORM_RPL 0
Anusha Srivatsa52407c22021-12-02 22:35:43 -0800120
Tejas Upadhyay7e28d0b2021-12-10 10:48:02 +0530121/* ADL-P */
Matt Atwood72c3c8d2022-04-18 11:51:57 +0530122/*
123 * As #define INTEL_SUBPLATFORM_RPL 0 will apply
124 * here too, SUBPLATFORM_N will have different
125 * bit set
126 */
127#define INTEL_SUBPLATFORM_N 1
Chaitanya Kumar Borah61b795a2023-01-30 15:38:05 +0530128#define INTEL_SUBPLATFORM_RPLU 2
Tejas Upadhyay7e28d0b2021-12-10 10:48:02 +0530129
Chris Wilsoncbecbcc2019-03-14 22:38:36 +0000130enum intel_ppgtt_type {
Chris Wilson4bdafb92018-09-26 21:12:22 +0100131 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
132 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
133 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
Chris Wilson4bdafb92018-09-26 21:12:22 +0100134};
135
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000136#define DEV_INFO_FOR_EACH_FLAG(func) \
137 func(is_mobile); \
138 func(is_lp); \
Jani Nikula7ef5ef52019-05-06 16:48:01 +0300139 func(require_force_probe); \
José Roberto de Souzadc90fe32019-10-24 12:51:19 -0700140 func(is_dgfx); \
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000141 /* Keep has_* in alphabetical order */ \
142 func(has_64bit_reloc); \
Stuart Summersc83125b2021-12-08 19:46:10 +0530143 func(has_64k_pages); \
Chris Wilson55277e12019-01-03 11:21:04 +0000144 func(gpu_reset_clobbers_display); \
Tvrtko Ursulinb409db02022-05-19 10:08:00 +0100145 func(has_reset_engine); \
Stuart Summers1eb31332022-05-10 23:02:26 -0700146 func(has_3d_pipeline); \
CQ Tang5e3094c2022-02-19 00:17:50 +0530147 func(has_flat_ccs); \
Michel Thierrya7a7a0e2019-07-30 11:04:06 -0700148 func(has_global_mocs); \
Matt Roperc2c70752022-09-15 18:46:46 -0700149 func(has_gmd_id); \
Tvrtko Ursulin39921e52022-05-19 10:08:02 +0100150 func(has_gt_uc); \
Tomas Winkler1e3dc1d2022-04-19 12:33:08 -0700151 func(has_heci_pxp); \
152 func(has_heci_gscfi); \
Daniele Ceraolo Spuriodb3b3f32022-01-20 13:29:47 -0800153 func(has_guc_deprivilege); \
Jonathan Cavitt29e668332023-10-17 11:08:00 -0700154 func(has_guc_tlb_invalidation); \
Ayaz A Siddiqui9d67edb2022-05-05 14:38:03 -0700155 func(has_l3_ccs_read); \
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000156 func(has_l3_dpf); \
157 func(has_llc); \
158 func(has_logical_ring_contexts); \
Tvrtko Ursulin3d6c72b2022-05-19 10:07:59 +0100159 func(has_logical_ring_elsq); \
Ashutosh Dixit85a040b2022-05-19 09:57:30 +0100160 func(has_media_ratio_mode); \
Matt Ropere0d73712022-06-08 10:07:00 -0700161 func(has_mslice_steering); \
Umesh Nerlige Ramappacceb0842022-10-26 22:20:51 +0000162 func(has_oa_bpc_reporting); \
Lionel Landwerlin0fa93492022-10-26 22:21:01 +0000163 func(has_oa_slice_contrib_limits); \
Umesh Nerlige Ramappa1cc064d2023-03-23 15:58:59 -0700164 func(has_oam); \
Matt Roper5ac342e2022-06-01 08:07:25 -0700165 func(has_one_eu_per_fuse_bit); \
Daniele Ceraolo Spurioe6aa7132021-09-24 12:14:38 -0700166 func(has_pxp); \
Tvrtko Ursulinfdbec9f2022-05-19 10:08:01 +0100167 func(has_rc6); \
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000168 func(has_rc6p); \
Chris Wilson91cbdb82019-04-19 14:48:36 +0100169 func(has_rps); \
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000170 func(has_runtime_pm); \
171 func(has_snoop); \
Chris Wilson900ccf32018-07-20 11:19:10 +0100172 func(has_coherent_ggtt); \
Matt Roper73c7a8a2022-08-26 14:27:18 -0700173 func(tuning_thread_rr_after_dep); \
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000174 func(unfenced_needs_alignment); \
José Roberto de Souzad53db442018-11-30 15:20:48 -0800175 func(hws_needs_physical);
176
Radhakrishna Sripadaef7e2222022-10-11 08:38:50 -0700177struct intel_ip_version {
José Roberto de Souzaa5b7ef22021-10-19 17:23:51 -0700178 u8 ver;
179 u8 rel;
Matt Roperc2c70752022-09-15 18:46:46 -0700180 u8 step;
José Roberto de Souzaa5b7ef22021-10-19 17:23:51 -0700181};
182
Jani Nikula2c93e7b2022-08-19 15:02:36 +0300183struct intel_runtime_info {
Matt Roperc2c70752022-09-15 18:46:46 -0700184 /*
185 * Single "graphics" IP version that represents
186 * render, compute and copy behavior.
187 */
Radhakrishna Sripadaf9e932a2022-09-02 15:10:54 -0700188 struct {
Radhakrishna Sripadaef7e2222022-10-11 08:38:50 -0700189 struct intel_ip_version ip;
Radhakrishna Sripadaf9e932a2022-09-02 15:10:54 -0700190 } graphics;
191 struct {
Radhakrishna Sripadaef7e2222022-10-11 08:38:50 -0700192 struct intel_ip_version ip;
Radhakrishna Sripadaf9e932a2022-09-02 15:10:54 -0700193 } media;
Jani Nikula43ba44a2022-08-19 15:02:37 +0300194
Jani Nikula2c93e7b2022-08-19 15:02:36 +0300195 /*
196 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
197 * single runtime conditionals, and also to provide groundwork for
198 * future per platform, or per SKU build optimizations.
199 *
200 * Array can be extended when necessary if the corresponding
201 * BUILD_BUG_ON is hit.
202 */
203 u32 platform_mask[2];
204
205 u16 device_id;
Lucas De Marchi93babb02021-04-12 22:09:54 -0700206
Jani Nikula2c93e7b2022-08-19 15:02:36 +0300207 u32 rawclk_freq;
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000208
Jani Nikula2c93e7b2022-08-19 15:02:36 +0300209 struct intel_step_info step;
Jani Nikulae6f19642022-08-19 15:02:38 +0300210
Jani Nikula9d0bad12022-08-19 15:02:39 +0300211 unsigned int page_sizes; /* page sizes supported by the HW */
Michael J. Ruhl31a02eb2020-04-17 15:51:07 -0400212
Chris Wilsoncbecbcc2019-03-14 22:38:36 +0000213 enum intel_ppgtt_type ppgtt_type;
214 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
215
Jani Nikula39a445b2022-08-19 15:02:41 +0300216 bool has_pooled_eu;
Jani Nikula2c93e7b2022-08-19 15:02:36 +0300217};
218
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000219struct intel_device_info {
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000220 enum intel_platform platform;
221
Chris Wilson4bdafb92018-09-26 21:12:22 +0100222 unsigned int dma_mask_size; /* available DMA address bits */
Tvrtko Ursulin4552f502018-02-22 11:16:58 +0000223
Matt Roper70fff192022-09-06 16:49:25 -0700224 const struct intel_gt_definition *extra_gt_list;
225
John Harrison938c7782021-07-23 12:10:24 -0700226 u8 gt; /* GT number, 0 if undefined */
227
Jani Nikula87767112023-06-27 18:13:59 +0300228 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
229 u32 memory_regions; /* regions supported by the HW */
230
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000231#define DEFINE_FLAG(name) u8 name:1
232 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
233#undef DEFINE_FLAG
José Roberto de Souzad53db442018-11-30 15:20:48 -0800234
Tvrtko Ursulin805446c2019-03-27 14:23:28 +0000235 /*
Jani Nikula2c93e7b2022-08-19 15:02:36 +0300236 * Initial runtime info. Do not access outside of i915_driver_create().
Tvrtko Ursulin805446c2019-03-27 14:23:28 +0000237 */
Jani Nikula2c93e7b2022-08-19 15:02:36 +0300238 const struct intel_runtime_info __runtime;
Fei Yang5e352e32023-05-09 09:51:59 -0700239
240 u32 cachelevel_to_pat[I915_MAX_CACHE_LEVEL];
241 u32 max_pat_index;
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000242};
243
Chris Wilson3fed1802018-02-07 21:05:43 +0000244struct intel_driver_caps {
245 unsigned int scheduler;
Chris Wilson481827b2018-07-06 11:14:41 +0100246 bool has_logical_contexts:1;
Chris Wilson3fed1802018-02-07 21:05:43 +0000247};
248
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000249const char *intel_platform_name(enum intel_platform platform);
250
Jani Nikula446a20c2023-04-11 13:56:43 +0300251void intel_device_info_driver_create(struct drm_i915_private *i915, u16 device_id,
252 const struct intel_device_info *match_info);
Matt Roperc2c70752022-09-15 18:46:46 -0700253void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);
Jani Nikula1400cc72018-12-31 16:56:43 +0200254void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
Chris Wilson72404972019-12-07 18:29:37 +0000255
Jani Nikulac7d3c842022-08-19 15:02:35 +0300256void intel_device_info_print(const struct intel_device_info *info,
257 const struct intel_runtime_info *runtime,
258 struct drm_printer *p);
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000259
Chris Wilson3fed1802018-02-07 21:05:43 +0000260void intel_driver_caps_print(const struct intel_driver_caps *caps,
261 struct drm_printer *p);
262
Michal Wajdeczkob9785202017-12-21 21:57:32 +0000263#endif