blob: 25fe149a8d9a58b5fadbd0ea293a21427f8d1ada [file] [log] [blame]
Thomas Gleixner1802d0b2019-05-27 08:55:21 +02001// SPDX-License-Identifier: GPL-2.0-only
Leilk Liua5682312015-08-07 15:19:50 +08002/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Leilk Liu <leilk.liu@mediatek.com>
Leilk Liua5682312015-08-07 15:19:50 +08005 */
6
7#include <linux/clk.h>
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/interrupt.h>
Leilk Liudd69a0a2015-08-24 11:45:15 +080011#include <linux/io.h>
Leilk Liua5682312015-08-07 15:19:50 +080012#include <linux/ioport.h>
13#include <linux/module.h>
14#include <linux/of.h>
Leilk Liu37457602015-10-26 16:09:44 +080015#include <linux/of_gpio.h>
Leilk Liua5682312015-08-07 15:19:50 +080016#include <linux/platform_device.h>
17#include <linux/platform_data/spi-mt65xx.h>
18#include <linux/pm_runtime.h>
19#include <linux/spi/spi.h>
luhua.xufdeae8f2019-09-11 05:55:31 -040020#include <linux/dma-mapping.h>
Leilk Liua5682312015-08-07 15:19:50 +080021
22#define SPI_CFG0_REG 0x0000
23#define SPI_CFG1_REG 0x0004
24#define SPI_TX_SRC_REG 0x0008
25#define SPI_RX_DST_REG 0x000c
26#define SPI_TX_DATA_REG 0x0010
27#define SPI_RX_DATA_REG 0x0014
28#define SPI_CMD_REG 0x0018
29#define SPI_STATUS0_REG 0x001c
30#define SPI_PAD_SEL_REG 0x0024
Leilk Liu058fe492017-06-12 09:24:39 +080031#define SPI_CFG2_REG 0x0028
luhua.xufdeae8f2019-09-11 05:55:31 -040032#define SPI_TX_SRC_REG_64 0x002c
33#define SPI_RX_DST_REG_64 0x0030
Leilk Liua5682312015-08-07 15:19:50 +080034
35#define SPI_CFG0_SCK_HIGH_OFFSET 0
36#define SPI_CFG0_SCK_LOW_OFFSET 8
37#define SPI_CFG0_CS_HOLD_OFFSET 16
38#define SPI_CFG0_CS_SETUP_OFFSET 24
Leilk Liu058fe492017-06-12 09:24:39 +080039#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
40#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
41#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
Leilk Liua5682312015-08-07 15:19:50 +080042
43#define SPI_CFG1_CS_IDLE_OFFSET 0
44#define SPI_CFG1_PACKET_LOOP_OFFSET 8
45#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
46#define SPI_CFG1_GET_TICK_DLY_OFFSET 30
47
48#define SPI_CFG1_CS_IDLE_MASK 0xff
49#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
50#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
51
Leilk Liua71d6ea2015-08-20 17:19:08 +080052#define SPI_CMD_ACT BIT(0)
53#define SPI_CMD_RESUME BIT(1)
Leilk Liua5682312015-08-07 15:19:50 +080054#define SPI_CMD_RST BIT(2)
55#define SPI_CMD_PAUSE_EN BIT(4)
56#define SPI_CMD_DEASSERT BIT(5)
Leilk Liu058fe492017-06-12 09:24:39 +080057#define SPI_CMD_SAMPLE_SEL BIT(6)
58#define SPI_CMD_CS_POL BIT(7)
Leilk Liua5682312015-08-07 15:19:50 +080059#define SPI_CMD_CPHA BIT(8)
60#define SPI_CMD_CPOL BIT(9)
61#define SPI_CMD_RX_DMA BIT(10)
62#define SPI_CMD_TX_DMA BIT(11)
63#define SPI_CMD_TXMSBF BIT(12)
64#define SPI_CMD_RXMSBF BIT(13)
65#define SPI_CMD_RX_ENDIAN BIT(14)
66#define SPI_CMD_TX_ENDIAN BIT(15)
67#define SPI_CMD_FINISH_IE BIT(16)
68#define SPI_CMD_PAUSE_IE BIT(17)
69
Leilk Liua5682312015-08-07 15:19:50 +080070#define MT8173_SPI_MAX_PAD_SEL 3
71
Leilk Liu50f8fec2015-08-24 11:45:16 +080072#define MTK_SPI_PAUSE_INT_STATUS 0x2
73
Leilk Liua5682312015-08-07 15:19:50 +080074#define MTK_SPI_IDLE 0
75#define MTK_SPI_PAUSED 1
76
Daniel Kurtz1ce24862017-01-27 00:21:54 +080077#define MTK_SPI_MAX_FIFO_SIZE 32U
Leilk Liua5682312015-08-07 15:19:50 +080078#define MTK_SPI_PACKET_SIZE 1024
luhua.xufdeae8f2019-09-11 05:55:31 -040079#define MTK_SPI_32BITS_MASK (0xffffffff)
80
81#define DMA_ADDR_EXT_BITS (36)
82#define DMA_ADDR_DEF_BITS (32)
Leilk Liua5682312015-08-07 15:19:50 +080083
84struct mtk_spi_compatible {
Leilk Liuaf579372015-08-20 17:19:07 +080085 bool need_pad_sel;
86 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
87 bool must_tx;
Leilk Liu058fe492017-06-12 09:24:39 +080088 /* some IC design adjust cfg register to enhance time accuracy */
89 bool enhance_timing;
luhua.xufdeae8f2019-09-11 05:55:31 -040090 /* some IC support DMA addr extension */
91 bool dma_ext;
Leilk Liua5682312015-08-07 15:19:50 +080092};
93
94struct mtk_spi {
95 void __iomem *base;
96 u32 state;
Leilk Liu37457602015-10-26 16:09:44 +080097 int pad_num;
98 u32 *pad_sel;
Leilk Liuadcbcfe2015-08-31 21:18:57 +080099 struct clk *parent_clk, *sel_clk, *spi_clk;
Leilk Liua5682312015-08-07 15:19:50 +0800100 struct spi_transfer *cur_transfer;
101 u32 xfer_len;
Peter Shih00bca732018-09-10 11:54:21 +0800102 u32 num_xfered;
Leilk Liua5682312015-08-07 15:19:50 +0800103 struct scatterlist *tx_sgl, *rx_sgl;
104 u32 tx_sgl_len, rx_sgl_len;
105 const struct mtk_spi_compatible *dev_comp;
106};
107
Leilk Liu4eaf6f72015-12-31 10:59:00 +0800108static const struct mtk_spi_compatible mtk_common_compat;
Leilk Liufc4f2262017-06-12 09:24:40 +0800109
leilk.liu@mediatek.comb6b1f2d2017-06-20 16:21:07 +0800110static const struct mtk_spi_compatible mt2712_compat = {
111 .must_tx = true,
112};
113
luhua.xu2c231e02019-09-11 05:55:30 -0400114static const struct mtk_spi_compatible mt6765_compat = {
115 .need_pad_sel = true,
116 .must_tx = true,
117 .enhance_timing = true,
luhua.xufdeae8f2019-09-11 05:55:31 -0400118 .dma_ext = true,
luhua.xu2c231e02019-09-11 05:55:30 -0400119};
120
Leilk Liufc4f2262017-06-12 09:24:40 +0800121static const struct mtk_spi_compatible mt7622_compat = {
122 .must_tx = true,
123 .enhance_timing = true,
124};
125
Leilk Liua5682312015-08-07 15:19:50 +0800126static const struct mtk_spi_compatible mt8173_compat = {
Leilk Liuaf579372015-08-20 17:19:07 +0800127 .need_pad_sel = true,
128 .must_tx = true,
Leilk Liua5682312015-08-07 15:19:50 +0800129};
130
Leilk Liub654aa62018-11-01 14:02:19 +0800131static const struct mtk_spi_compatible mt8183_compat = {
132 .need_pad_sel = true,
133 .must_tx = true,
134 .enhance_timing = true,
135};
136
Leilk Liua5682312015-08-07 15:19:50 +0800137/*
138 * A piece of default chip info unless the platform
139 * supplies it.
140 */
141static const struct mtk_chip_config mtk_default_chip_info = {
Leilk Liu058fe492017-06-12 09:24:39 +0800142 .cs_pol = 0,
143 .sample_sel = 0,
Leilk Liua5682312015-08-07 15:19:50 +0800144};
145
146static const struct of_device_id mtk_spi_of_match[] = {
Leilk Liu15bcdefd2015-12-31 10:59:01 +0800147 { .compatible = "mediatek,mt2701-spi",
148 .data = (void *)&mtk_common_compat,
149 },
leilk.liu@mediatek.comb6b1f2d2017-06-20 16:21:07 +0800150 { .compatible = "mediatek,mt2712-spi",
151 .data = (void *)&mt2712_compat,
152 },
Leilk Liu4eaf6f72015-12-31 10:59:00 +0800153 { .compatible = "mediatek,mt6589-spi",
154 .data = (void *)&mtk_common_compat,
155 },
luhua.xu2c231e02019-09-11 05:55:30 -0400156 { .compatible = "mediatek,mt6765-spi",
157 .data = (void *)&mt6765_compat,
158 },
Leilk Liufc4f2262017-06-12 09:24:40 +0800159 { .compatible = "mediatek,mt7622-spi",
160 .data = (void *)&mt7622_compat,
161 },
Leilk Liu942779c2018-11-20 16:41:08 +0800162 { .compatible = "mediatek,mt7629-spi",
163 .data = (void *)&mt7622_compat,
164 },
Leilk Liu4eaf6f72015-12-31 10:59:00 +0800165 { .compatible = "mediatek,mt8135-spi",
166 .data = (void *)&mtk_common_compat,
167 },
168 { .compatible = "mediatek,mt8173-spi",
169 .data = (void *)&mt8173_compat,
170 },
Leilk Liub654aa62018-11-01 14:02:19 +0800171 { .compatible = "mediatek,mt8183-spi",
172 .data = (void *)&mt8183_compat,
173 },
Leilk Liua5682312015-08-07 15:19:50 +0800174 {}
175};
176MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
177
178static void mtk_spi_reset(struct mtk_spi *mdata)
179{
180 u32 reg_val;
181
182 /* set the software reset bit in SPI_CMD_REG. */
183 reg_val = readl(mdata->base + SPI_CMD_REG);
184 reg_val |= SPI_CMD_RST;
185 writel(reg_val, mdata->base + SPI_CMD_REG);
186
187 reg_val = readl(mdata->base + SPI_CMD_REG);
188 reg_val &= ~SPI_CMD_RST;
189 writel(reg_val, mdata->base + SPI_CMD_REG);
190}
191
Leilk Liu79b5d3f2015-10-26 16:09:41 +0800192static int mtk_spi_prepare_message(struct spi_master *master,
193 struct spi_message *msg)
Leilk Liua5682312015-08-07 15:19:50 +0800194{
Leilk Liu79b5d3f2015-10-26 16:09:41 +0800195 u16 cpha, cpol;
Leilk Liua5682312015-08-07 15:19:50 +0800196 u32 reg_val;
Leilk Liu79b5d3f2015-10-26 16:09:41 +0800197 struct spi_device *spi = msg->spi;
Leilk Liu58a984c72015-10-26 16:09:43 +0800198 struct mtk_chip_config *chip_config = spi->controller_data;
Leilk Liu79b5d3f2015-10-26 16:09:41 +0800199 struct mtk_spi *mdata = spi_master_get_devdata(master);
200
201 cpha = spi->mode & SPI_CPHA ? 1 : 0;
202 cpol = spi->mode & SPI_CPOL ? 1 : 0;
203
Leilk Liu79b5d3f2015-10-26 16:09:41 +0800204 reg_val = readl(mdata->base + SPI_CMD_REG);
205 if (cpha)
206 reg_val |= SPI_CMD_CPHA;
207 else
208 reg_val &= ~SPI_CMD_CPHA;
209 if (cpol)
210 reg_val |= SPI_CMD_CPOL;
211 else
212 reg_val &= ~SPI_CMD_CPOL;
Leilk Liua5682312015-08-07 15:19:50 +0800213
214 /* set the mlsbx and mlsbtx */
Leilk Liu3e582c62019-06-05 11:07:04 +0800215 if (spi->mode & SPI_LSB_FIRST) {
Leilk Liua71d6ea2015-08-20 17:19:08 +0800216 reg_val &= ~SPI_CMD_TXMSBF;
Leilk Liua71d6ea2015-08-20 17:19:08 +0800217 reg_val &= ~SPI_CMD_RXMSBF;
Leilk Liu3e582c62019-06-05 11:07:04 +0800218 } else {
219 reg_val |= SPI_CMD_TXMSBF;
220 reg_val |= SPI_CMD_RXMSBF;
221 }
Leilk Liua5682312015-08-07 15:19:50 +0800222
223 /* set the tx/rx endian */
Leilk Liu44f636d2015-08-20 17:19:06 +0800224#ifdef __LITTLE_ENDIAN
225 reg_val &= ~SPI_CMD_TX_ENDIAN;
226 reg_val &= ~SPI_CMD_RX_ENDIAN;
227#else
228 reg_val |= SPI_CMD_TX_ENDIAN;
229 reg_val |= SPI_CMD_RX_ENDIAN;
230#endif
Leilk Liua5682312015-08-07 15:19:50 +0800231
Leilk Liu058fe492017-06-12 09:24:39 +0800232 if (mdata->dev_comp->enhance_timing) {
233 if (chip_config->cs_pol)
234 reg_val |= SPI_CMD_CS_POL;
235 else
236 reg_val &= ~SPI_CMD_CS_POL;
237 if (chip_config->sample_sel)
238 reg_val |= SPI_CMD_SAMPLE_SEL;
239 else
240 reg_val &= ~SPI_CMD_SAMPLE_SEL;
241 }
242
Leilk Liua5682312015-08-07 15:19:50 +0800243 /* set finish and pause interrupt always enable */
Leilk Liu15293322015-08-27 21:09:04 +0800244 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
Leilk Liua5682312015-08-07 15:19:50 +0800245
246 /* disable dma mode */
247 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
248
249 /* disable deassert mode */
250 reg_val &= ~SPI_CMD_DEASSERT;
251
252 writel(reg_val, mdata->base + SPI_CMD_REG);
253
254 /* pad select */
255 if (mdata->dev_comp->need_pad_sel)
Leilk Liu37457602015-10-26 16:09:44 +0800256 writel(mdata->pad_sel[spi->chip_select],
257 mdata->base + SPI_PAD_SEL_REG);
Leilk Liua5682312015-08-07 15:19:50 +0800258
259 return 0;
260}
261
262static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
263{
264 u32 reg_val;
265 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
266
267 reg_val = readl(mdata->base + SPI_CMD_REG);
Leilk Liu6583d202015-09-07 19:37:57 +0800268 if (!enable) {
Leilk Liua5682312015-08-07 15:19:50 +0800269 reg_val |= SPI_CMD_PAUSE_EN;
Leilk Liu6583d202015-09-07 19:37:57 +0800270 writel(reg_val, mdata->base + SPI_CMD_REG);
271 } else {
Leilk Liua5682312015-08-07 15:19:50 +0800272 reg_val &= ~SPI_CMD_PAUSE_EN;
Leilk Liu6583d202015-09-07 19:37:57 +0800273 writel(reg_val, mdata->base + SPI_CMD_REG);
274 mdata->state = MTK_SPI_IDLE;
275 mtk_spi_reset(mdata);
276 }
Leilk Liua5682312015-08-07 15:19:50 +0800277}
278
279static void mtk_spi_prepare_transfer(struct spi_master *master,
280 struct spi_transfer *xfer)
281{
Leilk Liu2ce0acf2015-08-24 11:45:18 +0800282 u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
Leilk Liua5682312015-08-07 15:19:50 +0800283 struct mtk_spi *mdata = spi_master_get_devdata(master);
284
285 spi_clk_hz = clk_get_rate(mdata->spi_clk);
286 if (xfer->speed_hz < spi_clk_hz / 2)
287 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
288 else
289 div = 1;
290
Leilk Liu2ce0acf2015-08-24 11:45:18 +0800291 sck_time = (div + 1) / 2;
292 cs_time = sck_time * 2;
Leilk Liua5682312015-08-07 15:19:50 +0800293
Leilk Liu058fe492017-06-12 09:24:39 +0800294 if (mdata->dev_comp->enhance_timing) {
295 reg_val |= (((sck_time - 1) & 0xffff)
296 << SPI_CFG0_SCK_HIGH_OFFSET);
297 reg_val |= (((sck_time - 1) & 0xffff)
298 << SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
299 writel(reg_val, mdata->base + SPI_CFG2_REG);
300 reg_val |= (((cs_time - 1) & 0xffff)
301 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
302 reg_val |= (((cs_time - 1) & 0xffff)
303 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
304 writel(reg_val, mdata->base + SPI_CFG0_REG);
305 } else {
306 reg_val |= (((sck_time - 1) & 0xff)
307 << SPI_CFG0_SCK_HIGH_OFFSET);
308 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
309 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
310 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
311 writel(reg_val, mdata->base + SPI_CFG0_REG);
312 }
Leilk Liua5682312015-08-07 15:19:50 +0800313
314 reg_val = readl(mdata->base + SPI_CFG1_REG);
315 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
Leilk Liu2ce0acf2015-08-24 11:45:18 +0800316 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
Leilk Liua5682312015-08-07 15:19:50 +0800317 writel(reg_val, mdata->base + SPI_CFG1_REG);
318}
319
320static void mtk_spi_setup_packet(struct spi_master *master)
321{
322 u32 packet_size, packet_loop, reg_val;
323 struct mtk_spi *mdata = spi_master_get_devdata(master);
324
Leilk Liu50f8fec2015-08-24 11:45:16 +0800325 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
Leilk Liua5682312015-08-07 15:19:50 +0800326 packet_loop = mdata->xfer_len / packet_size;
327
328 reg_val = readl(mdata->base + SPI_CFG1_REG);
Leilk Liu50f8fec2015-08-24 11:45:16 +0800329 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
Leilk Liua5682312015-08-07 15:19:50 +0800330 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
331 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
332 writel(reg_val, mdata->base + SPI_CFG1_REG);
333}
334
335static void mtk_spi_enable_transfer(struct spi_master *master)
336{
Leilk Liu50f8fec2015-08-24 11:45:16 +0800337 u32 cmd;
Leilk Liua5682312015-08-07 15:19:50 +0800338 struct mtk_spi *mdata = spi_master_get_devdata(master);
339
340 cmd = readl(mdata->base + SPI_CMD_REG);
341 if (mdata->state == MTK_SPI_IDLE)
Leilk Liua71d6ea2015-08-20 17:19:08 +0800342 cmd |= SPI_CMD_ACT;
Leilk Liua5682312015-08-07 15:19:50 +0800343 else
Leilk Liua71d6ea2015-08-20 17:19:08 +0800344 cmd |= SPI_CMD_RESUME;
Leilk Liua5682312015-08-07 15:19:50 +0800345 writel(cmd, mdata->base + SPI_CMD_REG);
346}
347
Leilk Liu50f8fec2015-08-24 11:45:16 +0800348static int mtk_spi_get_mult_delta(u32 xfer_len)
Leilk Liua5682312015-08-07 15:19:50 +0800349{
Leilk Liu50f8fec2015-08-24 11:45:16 +0800350 u32 mult_delta;
Leilk Liua5682312015-08-07 15:19:50 +0800351
352 if (xfer_len > MTK_SPI_PACKET_SIZE)
353 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
354 else
355 mult_delta = 0;
356
357 return mult_delta;
358}
359
360static void mtk_spi_update_mdata_len(struct spi_master *master)
361{
362 int mult_delta;
363 struct mtk_spi *mdata = spi_master_get_devdata(master);
364
365 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
366 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
367 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
368 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
369 mdata->rx_sgl_len = mult_delta;
370 mdata->tx_sgl_len -= mdata->xfer_len;
371 } else {
372 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
373 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
374 mdata->tx_sgl_len = mult_delta;
375 mdata->rx_sgl_len -= mdata->xfer_len;
376 }
377 } else if (mdata->tx_sgl_len) {
378 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
379 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
380 mdata->tx_sgl_len = mult_delta;
381 } else if (mdata->rx_sgl_len) {
382 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
383 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
384 mdata->rx_sgl_len = mult_delta;
385 }
386}
387
388static void mtk_spi_setup_dma_addr(struct spi_master *master,
389 struct spi_transfer *xfer)
390{
391 struct mtk_spi *mdata = spi_master_get_devdata(master);
392
luhua.xufdeae8f2019-09-11 05:55:31 -0400393 if (mdata->tx_sgl) {
394 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
395 mdata->base + SPI_TX_SRC_REG);
396#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
397 if (mdata->dev_comp->dma_ext)
398 writel((u32)(xfer->tx_dma >> 32),
399 mdata->base + SPI_TX_SRC_REG_64);
400#endif
401 }
402
403 if (mdata->rx_sgl) {
404 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
405 mdata->base + SPI_RX_DST_REG);
406#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
407 if (mdata->dev_comp->dma_ext)
408 writel((u32)(xfer->rx_dma >> 32),
409 mdata->base + SPI_RX_DST_REG_64);
410#endif
411 }
Leilk Liua5682312015-08-07 15:19:50 +0800412}
413
414static int mtk_spi_fifo_transfer(struct spi_master *master,
415 struct spi_device *spi,
416 struct spi_transfer *xfer)
417{
Nicolas Boichatde327e42015-12-27 18:17:06 +0800418 int cnt, remainder;
419 u32 reg_val;
Leilk Liua5682312015-08-07 15:19:50 +0800420 struct mtk_spi *mdata = spi_master_get_devdata(master);
421
422 mdata->cur_transfer = xfer;
Daniel Kurtz1ce24862017-01-27 00:21:54 +0800423 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
Peter Shih00bca732018-09-10 11:54:21 +0800424 mdata->num_xfered = 0;
Leilk Liua5682312015-08-07 15:19:50 +0800425 mtk_spi_prepare_transfer(master, xfer);
426 mtk_spi_setup_packet(master);
427
Nicolas Boichatde327e42015-12-27 18:17:06 +0800428 cnt = xfer->len / 4;
Leilk Liu44f636d2015-08-20 17:19:06 +0800429 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
Leilk Liua5682312015-08-07 15:19:50 +0800430
Nicolas Boichatde327e42015-12-27 18:17:06 +0800431 remainder = xfer->len % 4;
432 if (remainder > 0) {
433 reg_val = 0;
434 memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
435 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
436 }
437
Leilk Liua5682312015-08-07 15:19:50 +0800438 mtk_spi_enable_transfer(master);
439
440 return 1;
441}
442
443static int mtk_spi_dma_transfer(struct spi_master *master,
444 struct spi_device *spi,
445 struct spi_transfer *xfer)
446{
447 int cmd;
448 struct mtk_spi *mdata = spi_master_get_devdata(master);
449
450 mdata->tx_sgl = NULL;
451 mdata->rx_sgl = NULL;
452 mdata->tx_sgl_len = 0;
453 mdata->rx_sgl_len = 0;
454 mdata->cur_transfer = xfer;
Peter Shih00bca732018-09-10 11:54:21 +0800455 mdata->num_xfered = 0;
Leilk Liua5682312015-08-07 15:19:50 +0800456
457 mtk_spi_prepare_transfer(master, xfer);
458
459 cmd = readl(mdata->base + SPI_CMD_REG);
460 if (xfer->tx_buf)
461 cmd |= SPI_CMD_TX_DMA;
462 if (xfer->rx_buf)
463 cmd |= SPI_CMD_RX_DMA;
464 writel(cmd, mdata->base + SPI_CMD_REG);
465
466 if (xfer->tx_buf)
467 mdata->tx_sgl = xfer->tx_sg.sgl;
468 if (xfer->rx_buf)
469 mdata->rx_sgl = xfer->rx_sg.sgl;
470
471 if (mdata->tx_sgl) {
472 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
473 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
474 }
475 if (mdata->rx_sgl) {
476 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
477 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
478 }
479
480 mtk_spi_update_mdata_len(master);
481 mtk_spi_setup_packet(master);
482 mtk_spi_setup_dma_addr(master, xfer);
483 mtk_spi_enable_transfer(master);
484
485 return 1;
486}
487
488static int mtk_spi_transfer_one(struct spi_master *master,
489 struct spi_device *spi,
490 struct spi_transfer *xfer)
491{
492 if (master->can_dma(master, spi, xfer))
493 return mtk_spi_dma_transfer(master, spi, xfer);
494 else
495 return mtk_spi_fifo_transfer(master, spi, xfer);
496}
497
498static bool mtk_spi_can_dma(struct spi_master *master,
499 struct spi_device *spi,
500 struct spi_transfer *xfer)
501{
Daniel Kurtz1ce24862017-01-27 00:21:54 +0800502 /* Buffers for DMA transactions must be 4-byte aligned */
503 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
504 (unsigned long)xfer->tx_buf % 4 == 0 &&
505 (unsigned long)xfer->rx_buf % 4 == 0);
Leilk Liua5682312015-08-07 15:19:50 +0800506}
507
Leilk Liu58a984c72015-10-26 16:09:43 +0800508static int mtk_spi_setup(struct spi_device *spi)
509{
510 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
511
512 if (!spi->controller_data)
513 spi->controller_data = (void *)&mtk_default_chip_info;
514
Nicolas Boichat98c8dcc2015-11-09 12:14:51 +0800515 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
Leilk Liu37457602015-10-26 16:09:44 +0800516 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
517
Leilk Liu58a984c72015-10-26 16:09:43 +0800518 return 0;
519}
520
Leilk Liua5682312015-08-07 15:19:50 +0800521static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
522{
Peter Shih00bca732018-09-10 11:54:21 +0800523 u32 cmd, reg_val, cnt, remainder, len;
Leilk Liua5682312015-08-07 15:19:50 +0800524 struct spi_master *master = dev_id;
525 struct mtk_spi *mdata = spi_master_get_devdata(master);
526 struct spi_transfer *trans = mdata->cur_transfer;
527
528 reg_val = readl(mdata->base + SPI_STATUS0_REG);
Leilk Liu50f8fec2015-08-24 11:45:16 +0800529 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
Leilk Liua5682312015-08-07 15:19:50 +0800530 mdata->state = MTK_SPI_PAUSED;
531 else
532 mdata->state = MTK_SPI_IDLE;
533
534 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
Leilk Liua5682312015-08-07 15:19:50 +0800535 if (trans->rx_buf) {
Nicolas Boichatde327e42015-12-27 18:17:06 +0800536 cnt = mdata->xfer_len / 4;
Leilk Liu44f636d2015-08-20 17:19:06 +0800537 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
Peter Shih00bca732018-09-10 11:54:21 +0800538 trans->rx_buf + mdata->num_xfered, cnt);
Nicolas Boichatde327e42015-12-27 18:17:06 +0800539 remainder = mdata->xfer_len % 4;
540 if (remainder > 0) {
541 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
Peter Shih00bca732018-09-10 11:54:21 +0800542 memcpy(trans->rx_buf +
543 mdata->num_xfered +
544 (cnt * 4),
545 &reg_val,
546 remainder);
Nicolas Boichatde327e42015-12-27 18:17:06 +0800547 }
Leilk Liua5682312015-08-07 15:19:50 +0800548 }
Daniel Kurtz1ce24862017-01-27 00:21:54 +0800549
Peter Shih00bca732018-09-10 11:54:21 +0800550 mdata->num_xfered += mdata->xfer_len;
551 if (mdata->num_xfered == trans->len) {
Daniel Kurtz1ce24862017-01-27 00:21:54 +0800552 spi_finalize_current_transfer(master);
553 return IRQ_HANDLED;
554 }
555
Peter Shih00bca732018-09-10 11:54:21 +0800556 len = trans->len - mdata->num_xfered;
557 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
Daniel Kurtz1ce24862017-01-27 00:21:54 +0800558 mtk_spi_setup_packet(master);
559
Leilk Liua4d8f642018-10-31 16:49:16 +0800560 cnt = mdata->xfer_len / 4;
Peter Shih00bca732018-09-10 11:54:21 +0800561 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
562 trans->tx_buf + mdata->num_xfered, cnt);
Daniel Kurtz1ce24862017-01-27 00:21:54 +0800563
Leilk Liua4d8f642018-10-31 16:49:16 +0800564 remainder = mdata->xfer_len % 4;
Daniel Kurtz1ce24862017-01-27 00:21:54 +0800565 if (remainder > 0) {
566 reg_val = 0;
Peter Shih00bca732018-09-10 11:54:21 +0800567 memcpy(&reg_val,
568 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
569 remainder);
Daniel Kurtz1ce24862017-01-27 00:21:54 +0800570 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
571 }
572
573 mtk_spi_enable_transfer(master);
574
Leilk Liua5682312015-08-07 15:19:50 +0800575 return IRQ_HANDLED;
576 }
577
578 if (mdata->tx_sgl)
579 trans->tx_dma += mdata->xfer_len;
580 if (mdata->rx_sgl)
581 trans->rx_dma += mdata->xfer_len;
582
583 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
584 mdata->tx_sgl = sg_next(mdata->tx_sgl);
585 if (mdata->tx_sgl) {
586 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
587 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
588 }
589 }
590 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
591 mdata->rx_sgl = sg_next(mdata->rx_sgl);
592 if (mdata->rx_sgl) {
593 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
594 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
595 }
596 }
597
598 if (!mdata->tx_sgl && !mdata->rx_sgl) {
599 /* spi disable dma */
600 cmd = readl(mdata->base + SPI_CMD_REG);
601 cmd &= ~SPI_CMD_TX_DMA;
602 cmd &= ~SPI_CMD_RX_DMA;
603 writel(cmd, mdata->base + SPI_CMD_REG);
604
605 spi_finalize_current_transfer(master);
606 return IRQ_HANDLED;
607 }
608
609 mtk_spi_update_mdata_len(master);
610 mtk_spi_setup_packet(master);
611 mtk_spi_setup_dma_addr(master, trans);
612 mtk_spi_enable_transfer(master);
613
614 return IRQ_HANDLED;
615}
616
617static int mtk_spi_probe(struct platform_device *pdev)
618{
619 struct spi_master *master;
620 struct mtk_spi *mdata;
621 const struct of_device_id *of_id;
luhua.xufdeae8f2019-09-11 05:55:31 -0400622 int i, irq, ret, addr_bits;
Leilk Liua5682312015-08-07 15:19:50 +0800623
624 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
625 if (!master) {
626 dev_err(&pdev->dev, "failed to alloc spi master\n");
627 return -ENOMEM;
628 }
629
630 master->auto_runtime_pm = true;
631 master->dev.of_node = pdev->dev.of_node;
Leilk Liu3e582c62019-06-05 11:07:04 +0800632 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
Leilk Liua5682312015-08-07 15:19:50 +0800633
634 master->set_cs = mtk_spi_set_cs;
Leilk Liua5682312015-08-07 15:19:50 +0800635 master->prepare_message = mtk_spi_prepare_message;
636 master->transfer_one = mtk_spi_transfer_one;
637 master->can_dma = mtk_spi_can_dma;
Leilk Liu58a984c72015-10-26 16:09:43 +0800638 master->setup = mtk_spi_setup;
Leilk Liua5682312015-08-07 15:19:50 +0800639
640 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
641 if (!of_id) {
642 dev_err(&pdev->dev, "failed to probe of_node\n");
643 ret = -EINVAL;
644 goto err_put_master;
645 }
646
647 mdata = spi_master_get_devdata(master);
648 mdata->dev_comp = of_id->data;
649 if (mdata->dev_comp->must_tx)
650 master->flags = SPI_MASTER_MUST_TX;
651
652 if (mdata->dev_comp->need_pad_sel) {
Leilk Liu37457602015-10-26 16:09:44 +0800653 mdata->pad_num = of_property_count_u32_elems(
654 pdev->dev.of_node,
655 "mediatek,pad-select");
656 if (mdata->pad_num < 0) {
657 dev_err(&pdev->dev,
658 "No 'mediatek,pad-select' property\n");
659 ret = -EINVAL;
Leilk Liua5682312015-08-07 15:19:50 +0800660 goto err_put_master;
661 }
662
Leilk Liu37457602015-10-26 16:09:44 +0800663 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
664 sizeof(u32), GFP_KERNEL);
665 if (!mdata->pad_sel) {
666 ret = -ENOMEM;
Leilk Liua5682312015-08-07 15:19:50 +0800667 goto err_put_master;
668 }
Leilk Liu37457602015-10-26 16:09:44 +0800669
670 for (i = 0; i < mdata->pad_num; i++) {
671 of_property_read_u32_index(pdev->dev.of_node,
672 "mediatek,pad-select",
673 i, &mdata->pad_sel[i]);
674 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
675 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
676 i, mdata->pad_sel[i]);
677 ret = -EINVAL;
678 goto err_put_master;
679 }
680 }
Leilk Liua5682312015-08-07 15:19:50 +0800681 }
682
683 platform_set_drvdata(pdev, master);
Markus Elfring5dd381e72019-09-21 14:45:40 +0200684 mdata->base = devm_platform_ioremap_resource(pdev, 0);
Leilk Liua5682312015-08-07 15:19:50 +0800685 if (IS_ERR(mdata->base)) {
686 ret = PTR_ERR(mdata->base);
687 goto err_put_master;
688 }
689
690 irq = platform_get_irq(pdev, 0);
691 if (irq < 0) {
Leilk Liua5682312015-08-07 15:19:50 +0800692 ret = irq;
693 goto err_put_master;
694 }
695
696 if (!pdev->dev.dma_mask)
697 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
698
699 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
700 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
701 if (ret) {
702 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
703 goto err_put_master;
704 }
705
Leilk Liua5682312015-08-07 15:19:50 +0800706 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
707 if (IS_ERR(mdata->parent_clk)) {
708 ret = PTR_ERR(mdata->parent_clk);
709 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
710 goto err_put_master;
711 }
712
Leilk Liuadcbcfe2015-08-31 21:18:57 +0800713 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
714 if (IS_ERR(mdata->sel_clk)) {
Javier Martinez Canillase26d15f2015-09-15 14:46:45 +0200715 ret = PTR_ERR(mdata->sel_clk);
Leilk Liuadcbcfe2015-08-31 21:18:57 +0800716 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
717 goto err_put_master;
718 }
719
720 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
721 if (IS_ERR(mdata->spi_clk)) {
Javier Martinez Canillase26d15f2015-09-15 14:46:45 +0200722 ret = PTR_ERR(mdata->spi_clk);
Leilk Liuadcbcfe2015-08-31 21:18:57 +0800723 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
724 goto err_put_master;
725 }
726
Leilk Liua5682312015-08-07 15:19:50 +0800727 ret = clk_prepare_enable(mdata->spi_clk);
728 if (ret < 0) {
729 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
730 goto err_put_master;
731 }
732
Leilk Liuadcbcfe2015-08-31 21:18:57 +0800733 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
Leilk Liua5682312015-08-07 15:19:50 +0800734 if (ret < 0) {
735 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
Leilk Liue38da372015-11-25 17:50:38 +0800736 clk_disable_unprepare(mdata->spi_clk);
737 goto err_put_master;
Leilk Liua5682312015-08-07 15:19:50 +0800738 }
739
740 clk_disable_unprepare(mdata->spi_clk);
741
742 pm_runtime_enable(&pdev->dev);
743
744 ret = devm_spi_register_master(&pdev->dev, master);
745 if (ret) {
746 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
Leilk Liue38da372015-11-25 17:50:38 +0800747 goto err_disable_runtime_pm;
Leilk Liua5682312015-08-07 15:19:50 +0800748 }
749
Leilk Liu37457602015-10-26 16:09:44 +0800750 if (mdata->dev_comp->need_pad_sel) {
751 if (mdata->pad_num != master->num_chipselect) {
752 dev_err(&pdev->dev,
753 "pad_num does not match num_chipselect(%d != %d)\n",
754 mdata->pad_num, master->num_chipselect);
755 ret = -EINVAL;
Leilk Liue38da372015-11-25 17:50:38 +0800756 goto err_disable_runtime_pm;
Leilk Liu37457602015-10-26 16:09:44 +0800757 }
758
Nicolas Boichat98c8dcc2015-11-09 12:14:51 +0800759 if (!master->cs_gpios && master->num_chipselect > 1) {
760 dev_err(&pdev->dev,
761 "cs_gpios not specified and num_chipselect > 1\n");
762 ret = -EINVAL;
Leilk Liue38da372015-11-25 17:50:38 +0800763 goto err_disable_runtime_pm;
Nicolas Boichat98c8dcc2015-11-09 12:14:51 +0800764 }
765
766 if (master->cs_gpios) {
767 for (i = 0; i < master->num_chipselect; i++) {
768 ret = devm_gpio_request(&pdev->dev,
769 master->cs_gpios[i],
770 dev_name(&pdev->dev));
771 if (ret) {
772 dev_err(&pdev->dev,
773 "can't get CS GPIO %i\n", i);
Leilk Liue38da372015-11-25 17:50:38 +0800774 goto err_disable_runtime_pm;
Nicolas Boichat98c8dcc2015-11-09 12:14:51 +0800775 }
Leilk Liu37457602015-10-26 16:09:44 +0800776 }
777 }
778 }
779
luhua.xufdeae8f2019-09-11 05:55:31 -0400780 if (mdata->dev_comp->dma_ext)
781 addr_bits = DMA_ADDR_EXT_BITS;
782 else
783 addr_bits = DMA_ADDR_DEF_BITS;
784 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
785 if (ret)
786 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
787 addr_bits, ret);
788
Leilk Liua5682312015-08-07 15:19:50 +0800789 return 0;
790
Leilk Liue38da372015-11-25 17:50:38 +0800791err_disable_runtime_pm:
792 pm_runtime_disable(&pdev->dev);
Leilk Liua5682312015-08-07 15:19:50 +0800793err_put_master:
794 spi_master_put(master);
795
796 return ret;
797}
798
799static int mtk_spi_remove(struct platform_device *pdev)
800{
801 struct spi_master *master = platform_get_drvdata(pdev);
802 struct mtk_spi *mdata = spi_master_get_devdata(master);
803
804 pm_runtime_disable(&pdev->dev);
805
806 mtk_spi_reset(mdata);
Leilk Liua5682312015-08-07 15:19:50 +0800807
808 return 0;
809}
810
811#ifdef CONFIG_PM_SLEEP
812static int mtk_spi_suspend(struct device *dev)
813{
814 int ret;
815 struct spi_master *master = dev_get_drvdata(dev);
816 struct mtk_spi *mdata = spi_master_get_devdata(master);
817
818 ret = spi_master_suspend(master);
819 if (ret)
820 return ret;
821
822 if (!pm_runtime_suspended(dev))
823 clk_disable_unprepare(mdata->spi_clk);
824
825 return ret;
826}
827
828static int mtk_spi_resume(struct device *dev)
829{
830 int ret;
831 struct spi_master *master = dev_get_drvdata(dev);
832 struct mtk_spi *mdata = spi_master_get_devdata(master);
833
834 if (!pm_runtime_suspended(dev)) {
835 ret = clk_prepare_enable(mdata->spi_clk);
Leilk Liu13da5a02015-08-24 11:45:17 +0800836 if (ret < 0) {
837 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
Leilk Liua5682312015-08-07 15:19:50 +0800838 return ret;
Leilk Liu13da5a02015-08-24 11:45:17 +0800839 }
Leilk Liua5682312015-08-07 15:19:50 +0800840 }
841
842 ret = spi_master_resume(master);
843 if (ret < 0)
844 clk_disable_unprepare(mdata->spi_clk);
845
846 return ret;
847}
848#endif /* CONFIG_PM_SLEEP */
849
850#ifdef CONFIG_PM
851static int mtk_spi_runtime_suspend(struct device *dev)
852{
853 struct spi_master *master = dev_get_drvdata(dev);
854 struct mtk_spi *mdata = spi_master_get_devdata(master);
855
856 clk_disable_unprepare(mdata->spi_clk);
857
858 return 0;
859}
860
861static int mtk_spi_runtime_resume(struct device *dev)
862{
863 struct spi_master *master = dev_get_drvdata(dev);
864 struct mtk_spi *mdata = spi_master_get_devdata(master);
Leilk Liu13da5a02015-08-24 11:45:17 +0800865 int ret;
Leilk Liua5682312015-08-07 15:19:50 +0800866
Leilk Liu13da5a02015-08-24 11:45:17 +0800867 ret = clk_prepare_enable(mdata->spi_clk);
868 if (ret < 0) {
869 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
870 return ret;
871 }
872
873 return 0;
Leilk Liua5682312015-08-07 15:19:50 +0800874}
875#endif /* CONFIG_PM */
876
877static const struct dev_pm_ops mtk_spi_pm = {
878 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
879 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
880 mtk_spi_runtime_resume, NULL)
881};
882
kbuild test robot4299aaa2015-08-07 22:33:11 +0800883static struct platform_driver mtk_spi_driver = {
Leilk Liua5682312015-08-07 15:19:50 +0800884 .driver = {
885 .name = "mtk-spi",
886 .pm = &mtk_spi_pm,
887 .of_match_table = mtk_spi_of_match,
888 },
889 .probe = mtk_spi_probe,
890 .remove = mtk_spi_remove,
891};
892
893module_platform_driver(mtk_spi_driver);
894
895MODULE_DESCRIPTION("MTK SPI Controller driver");
896MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
897MODULE_LICENSE("GPL v2");
Axel Line4001885c2015-08-11 09:15:30 +0800898MODULE_ALIAS("platform:mtk-spi");