Thomas Gleixner | 2874c5f | 2019-05-27 08:55:01 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Synopsys DesignWare Multimedia Card Interface driver |
| 4 | * (Based on NXP driver for lpc 31xx) |
| 5 | * |
| 6 | * Copyright (C) 2009 NXP Semiconductors |
| 7 | * Copyright (C) 2009, 2010 Imagination Technologies Ltd. |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef _DW_MMC_H_ |
| 11 | #define _DW_MMC_H_ |
| 12 | |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 13 | #include <linux/scatterlist.h> |
| 14 | #include <linux/mmc/core.h> |
| 15 | #include <linux/dmaengine.h> |
| 16 | #include <linux/reset.h> |
Vincent Whitchurch | 2b8ac06 | 2021-07-01 10:05:34 +0200 | [diff] [blame] | 17 | #include <linux/fault-inject.h> |
| 18 | #include <linux/hrtimer.h> |
Ulf Hansson | b8789ec | 2016-12-30 13:47:23 +0100 | [diff] [blame] | 19 | #include <linux/interrupt.h> |
Allen Pais | 921c87b | 2024-07-01 03:07:33 -0700 | [diff] [blame] | 20 | #include <linux/workqueue.h> |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 21 | |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 22 | enum dw_mci_state { |
| 23 | STATE_IDLE = 0, |
| 24 | STATE_SENDING_CMD, |
| 25 | STATE_SENDING_DATA, |
| 26 | STATE_DATA_BUSY, |
| 27 | STATE_SENDING_STOP, |
| 28 | STATE_DATA_ERROR, |
| 29 | STATE_SENDING_CMD11, |
| 30 | STATE_WAITING_CMD11_DONE, |
| 31 | }; |
| 32 | |
| 33 | enum { |
| 34 | EVENT_CMD_COMPLETE = 0, |
| 35 | EVENT_XFER_COMPLETE, |
| 36 | EVENT_DATA_COMPLETE, |
| 37 | EVENT_DATA_ERROR, |
| 38 | }; |
| 39 | |
| 40 | enum dw_mci_cookie { |
| 41 | COOKIE_UNMAPPED, |
| 42 | COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */ |
| 43 | COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */ |
| 44 | }; |
| 45 | |
| 46 | struct mmc_data; |
| 47 | |
| 48 | enum { |
| 49 | TRANS_MODE_PIO = 0, |
| 50 | TRANS_MODE_IDMAC, |
| 51 | TRANS_MODE_EDMAC |
| 52 | }; |
| 53 | |
| 54 | struct dw_mci_dma_slave { |
| 55 | struct dma_chan *ch; |
| 56 | enum dma_transfer_direction direction; |
| 57 | }; |
| 58 | |
| 59 | /** |
| 60 | * struct dw_mci - MMC controller state shared between all slots |
| 61 | * @lock: Spinlock protecting the queue and associated data. |
| 62 | * @irq_lock: Spinlock protecting the INTMASK setting. |
| 63 | * @regs: Pointer to MMIO registers. |
| 64 | * @fifo_reg: Pointer to MMIO registers for data FIFO |
| 65 | * @sg: Scatterlist entry currently being processed by PIO code, if any. |
| 66 | * @sg_miter: PIO mapping scatterlist iterator. |
Alexey Roslyakov | 4b514fa | 2018-02-23 02:45:25 +0700 | [diff] [blame] | 67 | * @mrq: The request currently being processed on @slot, |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 68 | * or NULL if the controller is idle. |
| 69 | * @cmd: The command currently being sent to the card, or NULL. |
| 70 | * @data: The data currently being transferred, or NULL if no data |
| 71 | * transfer is in progress. |
| 72 | * @stop_abort: The command currently prepared for stoping transfer. |
| 73 | * @prev_blksz: The former transfer blksz record. |
| 74 | * @timing: Record of current ios timing. |
Ziyuan | 2afcbdb | 2017-08-30 10:58:21 +0800 | [diff] [blame] | 75 | * @use_dma: Which DMA channel is in use for the current transfer, zero |
| 76 | * denotes PIO mode. |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 77 | * @using_dma: Whether DMA is in use for the current transfer. |
| 78 | * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. |
| 79 | * @sg_dma: Bus address of DMA buffer. |
| 80 | * @sg_cpu: Virtual address of DMA buffer. |
| 81 | * @dma_ops: Pointer to platform-specific DMA callbacks. |
| 82 | * @cmd_status: Snapshot of SR taken upon completion of the current |
| 83 | * @ring_size: Buffer size for idma descriptors. |
| 84 | * command. Only valid when EVENT_CMD_COMPLETE is pending. |
| 85 | * @dms: structure of slave-dma private data. |
| 86 | * @phy_regs: physical address of controller's register map |
| 87 | * @data_status: Snapshot of SR taken upon completion of the current |
| 88 | * data transfer. Only valid when EVENT_DATA_COMPLETE or |
| 89 | * EVENT_DATA_ERROR is pending. |
| 90 | * @stop_cmdr: Value to be loaded into CMDR when the stop command is |
| 91 | * to be sent. |
| 92 | * @dir_status: Direction of current transfer. |
Allen Pais | 921c87b | 2024-07-01 03:07:33 -0700 | [diff] [blame] | 93 | * @bh_work: Work running the request state machine. |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 94 | * @pending_events: Bitmask of events flagged by the interrupt handler |
Allen Pais | 921c87b | 2024-07-01 03:07:33 -0700 | [diff] [blame] | 95 | * to be processed by bh work. |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 96 | * @completed_events: Bitmask of events which the state machine has |
| 97 | * processed. |
Allen Pais | 921c87b | 2024-07-01 03:07:33 -0700 | [diff] [blame] | 98 | * @state: BH work state. |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 99 | * @queue: List of slots waiting for access to the controller. |
| 100 | * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus |
| 101 | * rate and timeout calculations. |
| 102 | * @current_speed: Configured rate of the controller. |
Peter Geis | c4313e7 | 2022-03-05 16:58:34 -0500 | [diff] [blame] | 103 | * @minimum_speed: Stored minimum rate of the controller. |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 104 | * @fifoth_val: The value of FIFOTH register. |
| 105 | * @verid: Denote Version ID. |
| 106 | * @dev: Device associated with the MMC controller. |
| 107 | * @pdata: Platform data associated with the MMC controller. |
| 108 | * @drv_data: Driver specific data for identified variant of the controller |
| 109 | * @priv: Implementation defined private data. |
| 110 | * @biu_clk: Pointer to bus interface unit clock instance. |
| 111 | * @ciu_clk: Pointer to card interface unit clock instance. |
| 112 | * @slot: Slots sharing this MMC controller. |
| 113 | * @fifo_depth: depth of FIFO. |
Jun Nie | a0361c1 | 2017-01-11 15:35:35 +0900 | [diff] [blame] | 114 | * @data_addr_override: override fifo reg offset with this value. |
Jun Nie | d6fced8 | 2017-01-11 15:37:26 +0900 | [diff] [blame] | 115 | * @wm_aligned: force fifo watermark equal with data length in PIO mode. |
| 116 | * Set as true if alignment is needed. |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 117 | * @data_shift: log2 of FIFO item size. |
| 118 | * @part_buf_start: Start index in part_buf. |
| 119 | * @part_buf_count: Bytes of partial data in part_buf. |
| 120 | * @part_buf: Simple buffer for partial fifo reads/writes. |
| 121 | * @push_data: Pointer to FIFO push function. |
| 122 | * @pull_data: Pointer to FIFO pull function. |
Mårten Lindahl | 1a6fe7b | 2021-12-20 12:30:26 +0100 | [diff] [blame] | 123 | * @quirks: Set of quirks that apply to specific versions of the IP. |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 124 | * @vqmmc_enabled: Status of vqmmc, should be true or false. |
| 125 | * @irq_flags: The flags to be passed to request_irq. |
| 126 | * @irq: The irq value to be passed to request_irq. |
| 127 | * @sdio_id0: Number of slot0 in the SDIO interrupt registers. |
| 128 | * @cmd11_timer: Timer for SD3.0 voltage switch over scheme. |
Addy Ke | 03de192 | 2017-07-11 17:38:37 +0800 | [diff] [blame] | 129 | * @cto_timer: Timer for broken command transfer over scheme. |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 130 | * @dto_timer: Timer for broken data transfer over scheme. |
| 131 | * |
| 132 | * Locking |
| 133 | * ======= |
| 134 | * |
| 135 | * @lock is a softirq-safe spinlock protecting @queue as well as |
Alexey Roslyakov | 4b514fa | 2018-02-23 02:45:25 +0700 | [diff] [blame] | 136 | * @slot, @mrq and @state. These must always be updated |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 137 | * at the same time while holding @lock. |
Alexey Roslyakov | 4b514fa | 2018-02-23 02:45:25 +0700 | [diff] [blame] | 138 | * The @mrq field of struct dw_mci_slot is also protected by @lock, |
| 139 | * and must always be written at the same time as the slot is added to |
| 140 | * @queue. |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 141 | * |
| 142 | * @irq_lock is an irq-safe spinlock protecting the INTMASK register |
| 143 | * to allow the interrupt handler to modify it directly. Held for only long |
| 144 | * enough to read-modify-write INTMASK and no other locks are grabbed when |
| 145 | * holding this one. |
| 146 | * |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 147 | * @pending_events and @completed_events are accessed using atomic bit |
| 148 | * operations, so they don't need any locking. |
| 149 | * |
| 150 | * None of the fields touched by the interrupt handler need any |
| 151 | * locking. However, ordering is important: Before EVENT_DATA_ERROR or |
| 152 | * EVENT_DATA_COMPLETE is set in @pending_events, all data-related |
| 153 | * interrupts must be disabled and @data_status updated with a |
| 154 | * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the |
| 155 | * CMDRDY interrupt must be disabled and @cmd_status updated with a |
| 156 | * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the |
| 157 | * bytes_xfered field of @data must be written. This is ensured by |
| 158 | * using barriers. |
| 159 | */ |
| 160 | struct dw_mci { |
| 161 | spinlock_t lock; |
| 162 | spinlock_t irq_lock; |
| 163 | void __iomem *regs; |
| 164 | void __iomem *fifo_reg; |
Jun Nie | a0361c1 | 2017-01-11 15:35:35 +0900 | [diff] [blame] | 165 | u32 data_addr_override; |
Jun Nie | d6fced8 | 2017-01-11 15:37:26 +0900 | [diff] [blame] | 166 | bool wm_aligned; |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 167 | |
| 168 | struct scatterlist *sg; |
| 169 | struct sg_mapping_iter sg_miter; |
| 170 | |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 171 | struct mmc_request *mrq; |
| 172 | struct mmc_command *cmd; |
| 173 | struct mmc_data *data; |
| 174 | struct mmc_command stop_abort; |
| 175 | unsigned int prev_blksz; |
| 176 | unsigned char timing; |
| 177 | |
| 178 | /* DMA interface members*/ |
| 179 | int use_dma; |
| 180 | int using_dma; |
| 181 | int dma_64bit_address; |
| 182 | |
| 183 | dma_addr_t sg_dma; |
| 184 | void *sg_cpu; |
| 185 | const struct dw_mci_dma_ops *dma_ops; |
| 186 | /* For idmac */ |
| 187 | unsigned int ring_size; |
| 188 | |
| 189 | /* For edmac */ |
| 190 | struct dw_mci_dma_slave *dms; |
| 191 | /* Registers's physical base address */ |
| 192 | resource_size_t phy_regs; |
| 193 | |
| 194 | u32 cmd_status; |
| 195 | u32 data_status; |
| 196 | u32 stop_cmdr; |
| 197 | u32 dir_status; |
Allen Pais | 921c87b | 2024-07-01 03:07:33 -0700 | [diff] [blame] | 198 | struct work_struct bh_work; |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 199 | unsigned long pending_events; |
| 200 | unsigned long completed_events; |
| 201 | enum dw_mci_state state; |
| 202 | struct list_head queue; |
| 203 | |
| 204 | u32 bus_hz; |
| 205 | u32 current_speed; |
Peter Geis | c4313e7 | 2022-03-05 16:58:34 -0500 | [diff] [blame] | 206 | u32 minimum_speed; |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 207 | u32 fifoth_val; |
| 208 | u16 verid; |
| 209 | struct device *dev; |
| 210 | struct dw_mci_board *pdata; |
| 211 | const struct dw_mci_drv_data *drv_data; |
| 212 | void *priv; |
| 213 | struct clk *biu_clk; |
| 214 | struct clk *ciu_clk; |
Jaehoon Chung | b23475f | 2017-06-05 13:41:32 +0900 | [diff] [blame] | 215 | struct dw_mci_slot *slot; |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 216 | |
| 217 | /* FIFO push and pull */ |
| 218 | int fifo_depth; |
| 219 | int data_shift; |
| 220 | u8 part_buf_start; |
| 221 | u8 part_buf_count; |
| 222 | union { |
| 223 | u16 part_buf16; |
| 224 | u32 part_buf32; |
| 225 | u64 part_buf; |
| 226 | }; |
| 227 | void (*push_data)(struct dw_mci *host, void *buf, int cnt); |
| 228 | void (*pull_data)(struct dw_mci *host, void *buf, int cnt); |
| 229 | |
Mårten Lindahl | 1a6fe7b | 2021-12-20 12:30:26 +0100 | [diff] [blame] | 230 | u32 quirks; |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 231 | bool vqmmc_enabled; |
| 232 | unsigned long irq_flags; /* IRQ flags */ |
| 233 | int irq; |
| 234 | |
| 235 | int sdio_id0; |
| 236 | |
| 237 | struct timer_list cmd11_timer; |
Addy Ke | 03de192 | 2017-07-11 17:38:37 +0800 | [diff] [blame] | 238 | struct timer_list cto_timer; |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 239 | struct timer_list dto_timer; |
Vincent Whitchurch | 2b8ac06 | 2021-07-01 10:05:34 +0200 | [diff] [blame] | 240 | |
| 241 | #ifdef CONFIG_FAULT_INJECTION |
| 242 | struct fault_attr fail_data_crc; |
| 243 | struct hrtimer fault_timer; |
| 244 | #endif |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 245 | }; |
| 246 | |
| 247 | /* DMA ops for Internal/External DMAC interface */ |
| 248 | struct dw_mci_dma_ops { |
| 249 | /* DMA Ops */ |
| 250 | int (*init)(struct dw_mci *host); |
| 251 | int (*start)(struct dw_mci *host, unsigned int sg_len); |
| 252 | void (*complete)(void *host); |
| 253 | void (*stop)(struct dw_mci *host); |
| 254 | void (*cleanup)(struct dw_mci *host); |
| 255 | void (*exit)(struct dw_mci *host); |
| 256 | }; |
| 257 | |
| 258 | struct dma_pdata; |
| 259 | |
| 260 | /* Board platform data */ |
| 261 | struct dw_mci_board { |
Ulf Hansson | 0f21c58 | 2016-12-30 13:47:20 +0100 | [diff] [blame] | 262 | unsigned int bus_hz; /* Clock speed at the cclk_in pad */ |
| 263 | |
| 264 | u32 caps; /* Capabilities */ |
| 265 | u32 caps2; /* More capabilities */ |
| 266 | u32 pm_caps; /* PM capabilities */ |
| 267 | /* |
| 268 | * Override fifo depth. If 0, autodetect it from the FIFOTH register, |
| 269 | * but note that this may not be reliable after a bootloader has used |
| 270 | * it. |
| 271 | */ |
| 272 | unsigned int fifo_depth; |
| 273 | |
| 274 | /* delay in mS before detecting cards after interrupt */ |
| 275 | u32 detect_delay_ms; |
| 276 | |
| 277 | struct reset_control *rstc; |
| 278 | struct dw_mci_dma_ops *dma_ops; |
| 279 | struct dma_pdata *data; |
| 280 | }; |
| 281 | |
Mårten Lindahl | 1a6fe7b | 2021-12-20 12:30:26 +0100 | [diff] [blame] | 282 | /* Support for longer data read timeout */ |
| 283 | #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) |
| 284 | |
Jaehoon Chung | 4e0a5ad | 2011-10-17 19:36:23 +0900 | [diff] [blame] | 285 | #define DW_MMC_240A 0x240a |
Jaehoon Chung | 7e4bf1b | 2016-06-21 14:35:38 +0900 | [diff] [blame] | 286 | #define DW_MMC_280A 0x280a |
Jaehoon Chung | 4e0a5ad | 2011-10-17 19:36:23 +0900 | [diff] [blame] | 287 | |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 288 | #define SDMMC_CTRL 0x000 |
| 289 | #define SDMMC_PWREN 0x004 |
| 290 | #define SDMMC_CLKDIV 0x008 |
| 291 | #define SDMMC_CLKSRC 0x00c |
| 292 | #define SDMMC_CLKENA 0x010 |
| 293 | #define SDMMC_TMOUT 0x014 |
| 294 | #define SDMMC_CTYPE 0x018 |
| 295 | #define SDMMC_BLKSIZ 0x01c |
| 296 | #define SDMMC_BYTCNT 0x020 |
| 297 | #define SDMMC_INTMASK 0x024 |
| 298 | #define SDMMC_CMDARG 0x028 |
| 299 | #define SDMMC_CMD 0x02c |
| 300 | #define SDMMC_RESP0 0x030 |
| 301 | #define SDMMC_RESP1 0x034 |
| 302 | #define SDMMC_RESP2 0x038 |
| 303 | #define SDMMC_RESP3 0x03c |
| 304 | #define SDMMC_MINTSTS 0x040 |
| 305 | #define SDMMC_RINTSTS 0x044 |
| 306 | #define SDMMC_STATUS 0x048 |
| 307 | #define SDMMC_FIFOTH 0x04c |
| 308 | #define SDMMC_CDETECT 0x050 |
| 309 | #define SDMMC_WRTPRT 0x054 |
| 310 | #define SDMMC_GPIO 0x058 |
| 311 | #define SDMMC_TCBCNT 0x05c |
| 312 | #define SDMMC_TBBCNT 0x060 |
| 313 | #define SDMMC_DEBNCE 0x064 |
| 314 | #define SDMMC_USRID 0x068 |
| 315 | #define SDMMC_VERID 0x06c |
| 316 | #define SDMMC_HCON 0x070 |
Jaehoon Chung | 41babf7 | 2011-02-24 13:46:11 +0900 | [diff] [blame] | 317 | #define SDMMC_UHS_REG 0x074 |
Shawn Lin | 935a665 | 2016-01-14 09:08:02 +0800 | [diff] [blame] | 318 | #define SDMMC_RST_N 0x078 |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 319 | #define SDMMC_BMOD 0x080 |
| 320 | #define SDMMC_PLDMND 0x084 |
| 321 | #define SDMMC_DBADDR 0x088 |
| 322 | #define SDMMC_IDSTS 0x08c |
| 323 | #define SDMMC_IDINTEN 0x090 |
| 324 | #define SDMMC_DSCADDR 0x094 |
| 325 | #define SDMMC_BUFADDR 0x098 |
Seungwon Jeon | f1d2736 | 2013-08-31 00:13:55 +0900 | [diff] [blame] | 326 | #define SDMMC_CDTHRCTL 0x100 |
liwei | 361c7fe | 2017-08-11 16:06:24 +0800 | [diff] [blame] | 327 | #define SDMMC_UHS_REG_EXT 0x108 |
tianshuliang | e382ab7 | 2018-03-08 09:01:34 +0800 | [diff] [blame] | 328 | #define SDMMC_DDR_REG 0x10c |
liwei | 361c7fe | 2017-08-11 16:06:24 +0800 | [diff] [blame] | 329 | #define SDMMC_ENABLE_SHIFT 0x110 |
Jaehoon Chung | 4e0a5ad | 2011-10-17 19:36:23 +0900 | [diff] [blame] | 330 | #define SDMMC_DATA(x) (x) |
Prabu Thangamuthu | 69d99fd | 2014-10-20 07:12:33 +0000 | [diff] [blame] | 331 | /* |
Alexey Roslyakov | 4b514fa | 2018-02-23 02:45:25 +0700 | [diff] [blame] | 332 | * Registers to support idmac 64-bit address mode |
| 333 | */ |
Prabu Thangamuthu | 69d99fd | 2014-10-20 07:12:33 +0000 | [diff] [blame] | 334 | #define SDMMC_DBADDRL 0x088 |
| 335 | #define SDMMC_DBADDRU 0x08c |
| 336 | #define SDMMC_IDSTS64 0x090 |
| 337 | #define SDMMC_IDINTEN64 0x094 |
| 338 | #define SDMMC_DSCADDRL 0x098 |
| 339 | #define SDMMC_DSCADDRU 0x09c |
| 340 | #define SDMMC_BUFADDRL 0x0A0 |
| 341 | #define SDMMC_BUFADDRU 0x0A4 |
Jaehoon Chung | 4e0a5ad | 2011-10-17 19:36:23 +0900 | [diff] [blame] | 342 | |
| 343 | /* |
| 344 | * Data offset is difference according to Version |
| 345 | * Lower than 2.40a : data register offest is 0x100 |
| 346 | */ |
| 347 | #define DATA_OFFSET 0x100 |
| 348 | #define DATA_240A_OFFSET 0x200 |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 349 | |
| 350 | /* shift bit field */ |
| 351 | #define _SBF(f, v) ((v) << (f)) |
| 352 | |
| 353 | /* Control register defines */ |
| 354 | #define SDMMC_CTRL_USE_IDMAC BIT(25) |
| 355 | #define SDMMC_CTRL_CEATA_INT_EN BIT(11) |
| 356 | #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) |
| 357 | #define SDMMC_CTRL_SEND_CCSD BIT(9) |
| 358 | #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) |
| 359 | #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) |
| 360 | #define SDMMC_CTRL_READ_WAIT BIT(6) |
| 361 | #define SDMMC_CTRL_DMA_ENABLE BIT(5) |
| 362 | #define SDMMC_CTRL_INT_ENABLE BIT(4) |
| 363 | #define SDMMC_CTRL_DMA_RESET BIT(2) |
| 364 | #define SDMMC_CTRL_FIFO_RESET BIT(1) |
| 365 | #define SDMMC_CTRL_RESET BIT(0) |
| 366 | /* Clock Enable register defines */ |
| 367 | #define SDMMC_CLKEN_LOW_PWR BIT(16) |
| 368 | #define SDMMC_CLKEN_ENABLE BIT(0) |
| 369 | /* time-out register defines */ |
| 370 | #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) |
| 371 | #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 |
| 372 | #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) |
| 373 | #define SDMMC_TMOUT_RESP_MSK 0xFF |
| 374 | /* card-type register defines */ |
| 375 | #define SDMMC_CTYPE_8BIT BIT(16) |
| 376 | #define SDMMC_CTYPE_4BIT BIT(0) |
| 377 | #define SDMMC_CTYPE_1BIT 0 |
| 378 | /* Interrupt status & mask register defines */ |
Shashidhar Hiremath | 1a5c8e1 | 2011-08-29 13:11:46 +0530 | [diff] [blame] | 379 | #define SDMMC_INT_SDIO(n) BIT(16 + (n)) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 380 | #define SDMMC_INT_EBE BIT(15) |
| 381 | #define SDMMC_INT_ACD BIT(14) |
| 382 | #define SDMMC_INT_SBE BIT(13) |
| 383 | #define SDMMC_INT_HLE BIT(12) |
| 384 | #define SDMMC_INT_FRUN BIT(11) |
| 385 | #define SDMMC_INT_HTO BIT(10) |
Doug Anderson | 0173055 | 2014-08-22 19:17:51 +0530 | [diff] [blame] | 386 | #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ |
Jaehoon Chung | 3f7eec6 | 2013-05-27 13:47:57 +0900 | [diff] [blame] | 387 | #define SDMMC_INT_DRTO BIT(9) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 388 | #define SDMMC_INT_RTO BIT(8) |
| 389 | #define SDMMC_INT_DCRC BIT(7) |
| 390 | #define SDMMC_INT_RCRC BIT(6) |
| 391 | #define SDMMC_INT_RXDR BIT(5) |
| 392 | #define SDMMC_INT_TXDR BIT(4) |
| 393 | #define SDMMC_INT_DATA_OVER BIT(3) |
| 394 | #define SDMMC_INT_CMD_DONE BIT(2) |
| 395 | #define SDMMC_INT_RESP_ERR BIT(1) |
| 396 | #define SDMMC_INT_CD BIT(0) |
| 397 | #define SDMMC_INT_ERROR 0xbfc2 |
| 398 | /* Command register defines */ |
| 399 | #define SDMMC_CMD_START BIT(31) |
Dinh Nguyen | eede211 | 2013-06-12 10:18:51 -0500 | [diff] [blame] | 400 | #define SDMMC_CMD_USE_HOLD_REG BIT(29) |
Doug Anderson | 0173055 | 2014-08-22 19:17:51 +0530 | [diff] [blame] | 401 | #define SDMMC_CMD_VOLT_SWITCH BIT(28) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 402 | #define SDMMC_CMD_CCS_EXP BIT(23) |
| 403 | #define SDMMC_CMD_CEATA_RD BIT(22) |
| 404 | #define SDMMC_CMD_UPD_CLK BIT(21) |
| 405 | #define SDMMC_CMD_INIT BIT(15) |
| 406 | #define SDMMC_CMD_STOP BIT(14) |
| 407 | #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) |
| 408 | #define SDMMC_CMD_SEND_STOP BIT(12) |
| 409 | #define SDMMC_CMD_STRM_MODE BIT(11) |
| 410 | #define SDMMC_CMD_DAT_WR BIT(10) |
| 411 | #define SDMMC_CMD_DAT_EXP BIT(9) |
| 412 | #define SDMMC_CMD_RESP_CRC BIT(8) |
| 413 | #define SDMMC_CMD_RESP_LONG BIT(7) |
| 414 | #define SDMMC_CMD_RESP_EXP BIT(6) |
| 415 | #define SDMMC_CMD_INDX(n) ((n) & 0x1F) |
| 416 | /* Status register defines */ |
Jaehoon Chung | ee5d19b | 2012-01-05 19:12:57 +0900 | [diff] [blame] | 417 | #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) |
Sonny Rao | 3a33a94 | 2014-08-04 18:19:50 -0700 | [diff] [blame] | 418 | #define SDMMC_STATUS_DMA_REQ BIT(31) |
Doug Anderson | 0173055 | 2014-08-22 19:17:51 +0530 | [diff] [blame] | 419 | #define SDMMC_STATUS_BUSY BIT(9) |
Seungwon Jeon | 5242689 | 2013-08-31 00:13:42 +0900 | [diff] [blame] | 420 | /* FIFOTH register defines */ |
| 421 | #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ |
| 422 | ((r) & 0xFFF) << 16 | \ |
| 423 | ((t) & 0xFFF)) |
Shawn Lin | 3fc7eae | 2015-09-16 14:41:23 +0800 | [diff] [blame] | 424 | /* HCON register defines */ |
| 425 | #define DMA_INTERFACE_IDMA (0x0) |
| 426 | #define DMA_INTERFACE_DWDMA (0x1) |
| 427 | #define DMA_INTERFACE_GDMA (0x2) |
| 428 | #define DMA_INTERFACE_NODMA (0x3) |
| 429 | #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) |
Shawn Lin | 7069275 | 2015-09-16 14:41:37 +0800 | [diff] [blame] | 430 | #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1) |
| 431 | #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7) |
| 432 | #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 433 | /* Internal DMAC interrupt defines */ |
| 434 | #define SDMMC_IDMAC_INT_AI BIT(9) |
| 435 | #define SDMMC_IDMAC_INT_NI BIT(8) |
| 436 | #define SDMMC_IDMAC_INT_CES BIT(5) |
| 437 | #define SDMMC_IDMAC_INT_DU BIT(4) |
| 438 | #define SDMMC_IDMAC_INT_FBE BIT(2) |
| 439 | #define SDMMC_IDMAC_INT_RI BIT(1) |
| 440 | #define SDMMC_IDMAC_INT_TI BIT(0) |
| 441 | /* Internal DMAC bus mode bits */ |
| 442 | #define SDMMC_IDMAC_ENABLE BIT(7) |
| 443 | #define SDMMC_IDMAC_FB BIT(1) |
| 444 | #define SDMMC_IDMAC_SWRESET BIT(0) |
Shawn Lin | 935a665 | 2016-01-14 09:08:02 +0800 | [diff] [blame] | 445 | /* H/W reset */ |
| 446 | #define SDMMC_RST_HWACTIVE 0x1 |
Jaehoon Chung | 4e0a5ad | 2011-10-17 19:36:23 +0900 | [diff] [blame] | 447 | /* Version ID register define */ |
| 448 | #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) |
Seungwon Jeon | f1d2736 | 2013-08-31 00:13:55 +0900 | [diff] [blame] | 449 | /* Card read threshold */ |
Jaehoon Chung | 7e4bf1b | 2016-06-21 14:35:38 +0900 | [diff] [blame] | 450 | #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) |
| 451 | #define SDMMC_CARD_WR_THR_EN BIT(2) |
| 452 | #define SDMMC_CARD_RD_THR_EN BIT(0) |
| 453 | /* UHS-1 register defines */ |
tianshuliang | e382ab7 | 2018-03-08 09:01:34 +0800 | [diff] [blame] | 454 | #define SDMMC_UHS_DDR BIT(16) |
Doug Anderson | 0173055 | 2014-08-22 19:17:51 +0530 | [diff] [blame] | 455 | #define SDMMC_UHS_18V BIT(0) |
tianshuliang | e382ab7 | 2018-03-08 09:01:34 +0800 | [diff] [blame] | 456 | /* DDR register defines */ |
| 457 | #define SDMMC_DDR_HS400 BIT(31) |
| 458 | /* Enable shift register defines */ |
| 459 | #define SDMMC_ENABLE_PHASE BIT(0) |
Sonny Rao | 3a33a94 | 2014-08-04 18:19:50 -0700 | [diff] [blame] | 460 | /* All ctrl reset bits */ |
| 461 | #define SDMMC_CTRL_ALL_RESET_FLAGS \ |
| 462 | (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) |
| 463 | |
Ben Dooks | 76184ac | 2015-03-25 11:27:52 +0000 | [diff] [blame] | 464 | /* FIFO register access macros. These should not change the data endian-ness |
Alexey Roslyakov | 4b514fa | 2018-02-23 02:45:25 +0700 | [diff] [blame] | 465 | * as they are written to memory to be dealt with by the upper layers |
| 466 | */ |
Ben Dooks | 76184ac | 2015-03-25 11:27:52 +0000 | [diff] [blame] | 467 | #define mci_fifo_readw(__reg) __raw_readw(__reg) |
| 468 | #define mci_fifo_readl(__reg) __raw_readl(__reg) |
| 469 | #define mci_fifo_readq(__reg) __raw_readq(__reg) |
| 470 | |
| 471 | #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) |
| 472 | #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) |
| 473 | #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) |
| 474 | |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 475 | /* Register access macros */ |
| 476 | #define mci_readl(dev, reg) \ |
Ben Dooks | a2f1768 | 2015-03-25 11:27:50 +0000 | [diff] [blame] | 477 | readl_relaxed((dev)->regs + SDMMC_##reg) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 478 | #define mci_writel(dev, reg, value) \ |
Ben Dooks | a2f1768 | 2015-03-25 11:27:50 +0000 | [diff] [blame] | 479 | writel_relaxed((value), (dev)->regs + SDMMC_##reg) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 480 | |
| 481 | /* 16-bit FIFO access macros */ |
| 482 | #define mci_readw(dev, reg) \ |
Ben Dooks | a2f1768 | 2015-03-25 11:27:50 +0000 | [diff] [blame] | 483 | readw_relaxed((dev)->regs + SDMMC_##reg) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 484 | #define mci_writew(dev, reg, value) \ |
Ben Dooks | a2f1768 | 2015-03-25 11:27:50 +0000 | [diff] [blame] | 485 | writew_relaxed((value), (dev)->regs + SDMMC_##reg) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 486 | |
| 487 | /* 64-bit FIFO access macros */ |
| 488 | #ifdef readq |
| 489 | #define mci_readq(dev, reg) \ |
Ben Dooks | a2f1768 | 2015-03-25 11:27:50 +0000 | [diff] [blame] | 490 | readq_relaxed((dev)->regs + SDMMC_##reg) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 491 | #define mci_writeq(dev, reg, value) \ |
Ben Dooks | a2f1768 | 2015-03-25 11:27:50 +0000 | [diff] [blame] | 492 | writeq_relaxed((value), (dev)->regs + SDMMC_##reg) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 493 | #else |
| 494 | /* |
| 495 | * Dummy readq implementation for architectures that don't define it. |
| 496 | * |
| 497 | * We would assume that none of these architectures would configure |
| 498 | * the IP block with a 64bit FIFO width, so this code will never be |
| 499 | * executed on those machines. Defining these macros here keeps the |
| 500 | * rest of the code free from ifdefs. |
| 501 | */ |
| 502 | #define mci_readq(dev, reg) \ |
James Hogan | 892b1e3 | 2011-06-24 13:56:38 +0100 | [diff] [blame] | 503 | (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 504 | #define mci_writeq(dev, reg, value) \ |
James Hogan | 892b1e3 | 2011-06-24 13:56:38 +0100 | [diff] [blame] | 505 | (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) |
Ben Dooks | 76184ac | 2015-03-25 11:27:52 +0000 | [diff] [blame] | 506 | |
| 507 | #define __raw_writeq(__value, __reg) \ |
| 508 | (*(volatile u64 __force *)(__reg) = (__value)) |
| 509 | #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 510 | #endif |
| 511 | |
Shashidhar Hiremath | 62ca803 | 2012-01-13 16:04:57 +0530 | [diff] [blame] | 512 | extern int dw_mci_probe(struct dw_mci *host); |
| 513 | extern void dw_mci_remove(struct dw_mci *host); |
Shawn Lin | e9ed883 | 2016-10-12 10:50:35 +0800 | [diff] [blame] | 514 | #ifdef CONFIG_PM |
Shawn Lin | e9ed883 | 2016-10-12 10:50:35 +0800 | [diff] [blame] | 515 | extern int dw_mci_runtime_suspend(struct device *device); |
| 516 | extern int dw_mci_runtime_resume(struct device *device); |
Shashidhar Hiremath | 62ca803 | 2012-01-13 16:04:57 +0530 | [diff] [blame] | 517 | #endif |
| 518 | |
Thomas Abraham | 800d78b | 2012-09-17 18:16:42 +0000 | [diff] [blame] | 519 | /** |
Seungwon Jeon | 0976f16 | 2013-08-31 00:12:42 +0900 | [diff] [blame] | 520 | * struct dw_mci_slot - MMC slot state |
| 521 | * @mmc: The mmc_host representing this slot. |
| 522 | * @host: The MMC controller this slot is using. |
Seungwon Jeon | 0976f16 | 2013-08-31 00:12:42 +0900 | [diff] [blame] | 523 | * @ctype: Card type for this slot. |
| 524 | * @mrq: mmc_request currently being processed or waiting to be |
| 525 | * processed, or NULL when the slot is idle. |
| 526 | * @queue_node: List node for placing this node in the @queue list of |
| 527 | * &struct dw_mci. |
| 528 | * @clock: Clock rate configured by set_ios(). Protected by host->lock. |
Jaehoon Chung | 005d675 | 2016-09-22 14:12:00 +0900 | [diff] [blame] | 529 | * @__clk_old: The last clock value that was requested from core. |
| 530 | * Keeping track of this helps us to avoid spamming the console. |
Seungwon Jeon | 0976f16 | 2013-08-31 00:12:42 +0900 | [diff] [blame] | 531 | * @flags: Random state bits associated with the slot. |
| 532 | * @id: Number of this slot. |
Addy Ke | 7675623 | 2014-11-04 22:03:09 +0800 | [diff] [blame] | 533 | * @sdio_id: Number of this slot in the SDIO interrupt registers. |
Seungwon Jeon | 0976f16 | 2013-08-31 00:12:42 +0900 | [diff] [blame] | 534 | */ |
| 535 | struct dw_mci_slot { |
| 536 | struct mmc_host *mmc; |
| 537 | struct dw_mci *host; |
| 538 | |
Seungwon Jeon | 0976f16 | 2013-08-31 00:12:42 +0900 | [diff] [blame] | 539 | u32 ctype; |
| 540 | |
| 541 | struct mmc_request *mrq; |
| 542 | struct list_head queue_node; |
| 543 | |
| 544 | unsigned int clock; |
Jaehoon Chung | 005d675 | 2016-09-22 14:12:00 +0900 | [diff] [blame] | 545 | unsigned int __clk_old; |
Seungwon Jeon | 0976f16 | 2013-08-31 00:12:42 +0900 | [diff] [blame] | 546 | |
| 547 | unsigned long flags; |
| 548 | #define DW_MMC_CARD_PRESENT 0 |
| 549 | #define DW_MMC_CARD_NEED_INIT 1 |
Doug Anderson | b24c8b2 | 2014-12-02 15:42:46 -0800 | [diff] [blame] | 550 | #define DW_MMC_CARD_NO_LOW_PWR 2 |
Jaehoon Chung | aaaaeb7 | 2016-01-21 11:01:06 +0900 | [diff] [blame] | 551 | #define DW_MMC_CARD_NO_USE_HOLD 3 |
Jaehoon Chung | e6cd7a8 | 2016-11-24 20:04:42 +0900 | [diff] [blame] | 552 | #define DW_MMC_CARD_NEEDS_POLL 4 |
Seungwon Jeon | 0976f16 | 2013-08-31 00:12:42 +0900 | [diff] [blame] | 553 | int id; |
Addy Ke | 7675623 | 2014-11-04 22:03:09 +0800 | [diff] [blame] | 554 | int sdio_id; |
Seungwon Jeon | 0976f16 | 2013-08-31 00:12:42 +0900 | [diff] [blame] | 555 | }; |
| 556 | |
Seungwon Jeon | 0976f16 | 2013-08-31 00:12:42 +0900 | [diff] [blame] | 557 | /** |
Thomas Abraham | 800d78b | 2012-09-17 18:16:42 +0000 | [diff] [blame] | 558 | * dw_mci driver data - dw-mshc implementation specific driver data. |
| 559 | * @caps: mmc subsystem specified capabilities of the controller(s). |
Shawn Lin | 0d84b9e | 2018-02-24 14:17:23 +0800 | [diff] [blame] | 560 | * @num_caps: number of capabilities specified by @caps. |
John Keeping | 0dc7a3e | 2021-11-24 18:45:59 +0000 | [diff] [blame] | 561 | * @common_caps: mmc subsystem specified capabilities applicable to all of |
| 562 | * the controllers |
Thomas Abraham | 800d78b | 2012-09-17 18:16:42 +0000 | [diff] [blame] | 563 | * @init: early implementation specific initialization. |
Thomas Abraham | 800d78b | 2012-09-17 18:16:42 +0000 | [diff] [blame] | 564 | * @set_ios: handle bus specific extensions. |
| 565 | * @parse_dt: parse implementation specific device tree properties. |
Sachin Kamat | 5532ec5 | 2014-02-25 15:18:25 +0530 | [diff] [blame] | 566 | * @execute_tuning: implementation specific tuning procedure. |
Mårten Lindahl | 25d5417 | 2021-12-20 12:30:25 +0100 | [diff] [blame] | 567 | * @set_data_timeout: implementation specific timeout. |
| 568 | * @get_drto_clks: implementation specific cycle count for data read timeout. |
Liming Sun | f21adcb | 2024-06-12 18:52:37 -0400 | [diff] [blame] | 569 | * @hw_reset: implementation specific HW reset. |
Thomas Abraham | 800d78b | 2012-09-17 18:16:42 +0000 | [diff] [blame] | 570 | * |
| 571 | * Provide controller implementation specific extensions. The usage of this |
| 572 | * data structure is fully optional and usage of each member in this structure |
| 573 | * is optional as well. |
| 574 | */ |
| 575 | struct dw_mci_drv_data { |
| 576 | unsigned long *caps; |
Shawn Lin | 0d84b9e | 2018-02-24 14:17:23 +0800 | [diff] [blame] | 577 | u32 num_caps; |
John Keeping | 0dc7a3e | 2021-11-24 18:45:59 +0000 | [diff] [blame] | 578 | u32 common_caps; |
Thomas Abraham | 800d78b | 2012-09-17 18:16:42 +0000 | [diff] [blame] | 579 | int (*init)(struct dw_mci *host); |
Thomas Abraham | 800d78b | 2012-09-17 18:16:42 +0000 | [diff] [blame] | 580 | void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); |
| 581 | int (*parse_dt)(struct dw_mci *host); |
Chaotian Jing | 9979dbe | 2015-10-27 14:24:28 +0800 | [diff] [blame] | 582 | int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode); |
Seungwon Jeon | 8011313 | 2015-01-29 08:11:57 +0530 | [diff] [blame] | 583 | int (*prepare_hs400_tuning)(struct dw_mci *host, |
| 584 | struct mmc_ios *ios); |
Zhangfei Gao | 8f7849c | 2015-05-14 16:45:18 +0800 | [diff] [blame] | 585 | int (*switch_voltage)(struct mmc_host *mmc, |
| 586 | struct mmc_ios *ios); |
Mårten Lindahl | 25d5417 | 2021-12-20 12:30:25 +0100 | [diff] [blame] | 587 | void (*set_data_timeout)(struct dw_mci *host, |
| 588 | unsigned int timeout_ns); |
| 589 | u32 (*get_drto_clks)(struct dw_mci *host); |
Liming Sun | f21adcb | 2024-06-12 18:52:37 -0400 | [diff] [blame] | 590 | void (*hw_reset)(struct dw_mci *host); |
Thomas Abraham | 800d78b | 2012-09-17 18:16:42 +0000 | [diff] [blame] | 591 | }; |
Will Newton | f95f385 | 2011-01-02 01:11:59 -0500 | [diff] [blame] | 592 | #endif /* _DW_MMC_H_ */ |