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Thomas Gleixner0fdebc52022-06-07 16:11:14 +02001// SPDX-License-Identifier: GPL-2.0-only
Viresh Kumare3978dc2012-04-19 22:23:13 +05302/*
3 * arch/arm/mach-spear13xx/spear13xx.c
4 *
5 * SPEAr13XX machines common source file
6 *
7 * Copyright (C) 2012 ST Microelectronics
Viresh Kumarda899472015-07-17 16:23:50 -07008 * Viresh Kumar <vireshk@kernel.org>
Viresh Kumare3978dc2012-04-19 22:23:13 +05309 */
10
11#define pr_fmt(fmt) "SPEAr13xx: " fmt
12
13#include <linux/amba/pl022.h>
14#include <linux/clk.h>
Lee Jonesf2ad9372021-01-26 12:45:38 +000015#include <linux/clk/spear.h>
Rob Herringda4a6862013-02-06 21:17:47 -060016#include <linux/clocksource.h>
Viresh Kumare3978dc2012-04-19 22:23:13 +053017#include <linux/err.h>
Rob Herring0529e3152012-11-05 16:18:28 -060018#include <linux/of.h>
Viresh Kumare3978dc2012-04-19 22:23:13 +053019#include <asm/hardware/cache-l2x0.h>
Viresh Kumare3978dc2012-04-19 22:23:13 +053020#include <asm/mach/map.h>
Arnd Bergmannc1646202022-04-28 09:44:23 +020021#include "spear.h"
Arnd Bergmann442a33e2013-05-06 23:43:45 +020022#include "generic.h"
Viresh Kumare3978dc2012-04-19 22:23:13 +053023
Viresh Kumare3978dc2012-04-19 22:23:13 +053024void __init spear13xx_l2x0_init(void)
25{
26 /*
27 * 512KB (64KB/way), 8-way associativity, parity supported
28 *
Julia Lawall339ac712022-03-18 11:37:16 +010029 * FIXME: 9th bit, of Auxiliary Controller register must be set
Viresh Kumare3978dc2012-04-19 22:23:13 +053030 * for some spear13xx devices for stable L2 operation.
31 *
32 * Enable Early BRESP, L2 prefetch for Instruction and Data,
33 * write alloc and 'Full line of zero' options
34 *
35 */
Olof Johansson5497e7b2013-05-09 13:05:00 -070036 if (!IS_ENABLED(CONFIG_CACHE_L2X0))
37 return;
Viresh Kumare3978dc2012-04-19 22:23:13 +053038
Russell King1a5a9542014-03-16 20:52:25 +000039 writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL);
Viresh Kumare3978dc2012-04-19 22:23:13 +053040
41 /*
42 * Program following latencies in order to make
43 * SPEAr1340 work at 600 MHz
44 */
Russell King1a5a9542014-03-16 20:52:25 +000045 writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL);
46 writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL);
Russell Kingadf4b002014-03-19 12:18:02 +000047 l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff);
Viresh Kumare3978dc2012-04-19 22:23:13 +053048}
49
50/*
51 * Following will create 16MB static virtual/physical mappings
52 * PHYSICAL VIRTUAL
Pratyush Anand36c5c902013-11-29 15:57:35 +053053 * 0xB3000000 0xF9000000
Viresh Kumare3978dc2012-04-19 22:23:13 +053054 * 0xE0000000 0xFD000000
55 * 0xEC000000 0xFC000000
56 * 0xED000000 0xFB000000
57 */
Sachin Kamat3da1d7b2014-06-24 17:13:53 +053058static struct map_desc spear13xx_io_desc[] __initdata = {
Viresh Kumare3978dc2012-04-19 22:23:13 +053059 {
Arnd Bergmann009a01e2012-09-14 20:22:00 +000060 .virtual = (unsigned long)VA_PERIP_GRP2_BASE,
Viresh Kumare3978dc2012-04-19 22:23:13 +053061 .pfn = __phys_to_pfn(PERIP_GRP2_BASE),
62 .length = SZ_16M,
63 .type = MT_DEVICE
64 }, {
Arnd Bergmann009a01e2012-09-14 20:22:00 +000065 .virtual = (unsigned long)VA_PERIP_GRP1_BASE,
Viresh Kumare3978dc2012-04-19 22:23:13 +053066 .pfn = __phys_to_pfn(PERIP_GRP1_BASE),
67 .length = SZ_16M,
68 .type = MT_DEVICE
69 }, {
Arnd Bergmann009a01e2012-09-14 20:22:00 +000070 .virtual = (unsigned long)VA_A9SM_AND_MPMC_BASE,
Viresh Kumare3978dc2012-04-19 22:23:13 +053071 .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE),
72 .length = SZ_16M,
73 .type = MT_DEVICE
74 }, {
75 .virtual = (unsigned long)VA_L2CC_BASE,
76 .pfn = __phys_to_pfn(L2CC_BASE),
77 .length = SZ_4K,
78 .type = MT_DEVICE
79 },
80};
81
82/* This will create static memory mapping for selected devices */
83void __init spear13xx_map_io(void)
84{
85 iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
86}
87
88static void __init spear13xx_clk_init(void)
89{
90 if (of_machine_is_compatible("st,spear1310"))
Arnd Bergmannd9909eb2012-12-02 17:59:57 +010091 spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE);
Viresh Kumare3978dc2012-04-19 22:23:13 +053092 else if (of_machine_is_compatible("st,spear1340"))
Arnd Bergmannd9909eb2012-12-02 17:59:57 +010093 spear1340_clk_init(VA_MISC_BASE);
Viresh Kumare3978dc2012-04-19 22:23:13 +053094 else
95 pr_err("%s: Unknown machine\n", __func__);
96}
97
Stephen Warren6bb27d72012-11-08 12:40:59 -070098void __init spear13xx_timer_init(void)
Viresh Kumare3978dc2012-04-19 22:23:13 +053099{
100 char pclk_name[] = "osc_24m_clk";
101 struct clk *gpt_clk, *pclk;
102
103 spear13xx_clk_init();
104
105 /* get the system timer clock */
106 gpt_clk = clk_get_sys("gpt0", NULL);
107 if (IS_ERR(gpt_clk)) {
108 pr_err("%s:couldn't get clk for gpt\n", __func__);
109 BUG();
110 }
111
112 /* get the suitable parent clock for timer*/
113 pclk = clk_get(NULL, pclk_name);
114 if (IS_ERR(pclk)) {
115 pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
116 pclk_name);
117 BUG();
118 }
119
120 clk_set_parent(gpt_clk, pclk);
121 clk_put(gpt_clk);
122 clk_put(pclk);
123
124 spear_setup_of_timer();
Daniel Lezcanoba5d08c2017-05-26 17:40:46 +0200125 timer_probe();
Viresh Kumare3978dc2012-04-19 22:23:13 +0530126}