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Dan Murphy827ed8a2020-10-07 10:53:41 -05001/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * tas2764.h - ALSA SoC Texas Instruments TAS2764 Mono Audio Amplifier
4 *
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Author: Dan Murphy <dmurphy@ti.com>
8 */
9
10#ifndef __TAS2764__
11#define __TAS2764__
12
13/* Book Control Register */
14#define TAS2764_BOOKCTL_PAGE 0
15#define TAS2764_BOOKCTL_REG 127
16#define TAS2764_REG(page, reg) ((page * 128) + reg)
17
18/* Page */
19#define TAS2764_PAGE TAS2764_REG(0X0, 0x00)
20#define TAS2764_PAGE_PAGE_MASK 255
21
22/* Software Reset */
23#define TAS2764_SW_RST TAS2764_REG(0X0, 0x01)
24#define TAS2764_RST BIT(0)
25
26/* Power Control */
27#define TAS2764_PWR_CTRL TAS2764_REG(0X0, 0x02)
28#define TAS2764_PWR_CTRL_MASK GENMASK(1, 0)
29#define TAS2764_PWR_CTRL_ACTIVE 0x0
30#define TAS2764_PWR_CTRL_MUTE BIT(0)
31#define TAS2764_PWR_CTRL_SHUTDOWN BIT(1)
32
33#define TAS2764_VSENSE_POWER_EN 3
34#define TAS2764_ISENSE_POWER_EN 4
35
Martin Povišeraca86ec2022-08-25 16:02:41 +020036/* DC Blocker Control */
37#define TAS2764_DC_BLK0 TAS2764_REG(0x0, 0x04)
38#define TAS2764_DC_BLK0_HPF_FREQ_PB_SHIFT 0
39
Dan Murphy827ed8a2020-10-07 10:53:41 -050040/* Digital Volume Control */
41#define TAS2764_DVC TAS2764_REG(0X0, 0x1a)
42#define TAS2764_DVC_MAX 0xc9
43
44#define TAS2764_CHNL_0 TAS2764_REG(0X0, 0x03)
45
46/* TDM Configuration Reg0 */
47#define TAS2764_TDM_CFG0 TAS2764_REG(0X0, 0x08)
48#define TAS2764_TDM_CFG0_SMP_MASK BIT(5)
49#define TAS2764_TDM_CFG0_SMP_48KHZ 0x0
50#define TAS2764_TDM_CFG0_SMP_44_1KHZ BIT(5)
51#define TAS2764_TDM_CFG0_MASK GENMASK(3, 1)
52#define TAS2764_TDM_CFG0_44_1_48KHZ BIT(3)
53#define TAS2764_TDM_CFG0_88_2_96KHZ (BIT(3) | BIT(1))
Martin Povišerd1a10f12022-06-30 09:51:33 +020054#define TAS2764_TDM_CFG0_FRAME_START BIT(0)
Dan Murphy827ed8a2020-10-07 10:53:41 -050055
56/* TDM Configuration Reg1 */
57#define TAS2764_TDM_CFG1 TAS2764_REG(0X0, 0x09)
58#define TAS2764_TDM_CFG1_MASK GENMASK(5, 1)
59#define TAS2764_TDM_CFG1_51_SHIFT 1
60#define TAS2764_TDM_CFG1_RX_MASK BIT(0)
61#define TAS2764_TDM_CFG1_RX_RISING 0x0
62#define TAS2764_TDM_CFG1_RX_FALLING BIT(0)
63
64/* TDM Configuration Reg2 */
65#define TAS2764_TDM_CFG2 TAS2764_REG(0X0, 0x0a)
66#define TAS2764_TDM_CFG2_RXW_MASK GENMASK(3, 2)
67#define TAS2764_TDM_CFG2_RXW_16BITS 0x0
68#define TAS2764_TDM_CFG2_RXW_24BITS BIT(3)
69#define TAS2764_TDM_CFG2_RXW_32BITS (BIT(3) | BIT(2))
70#define TAS2764_TDM_CFG2_RXS_MASK GENMASK(1, 0)
71#define TAS2764_TDM_CFG2_RXS_16BITS 0x0
72#define TAS2764_TDM_CFG2_RXS_24BITS BIT(0)
73#define TAS2764_TDM_CFG2_RXS_32BITS BIT(1)
Martin Povišerd1a10f12022-06-30 09:51:33 +020074#define TAS2764_TDM_CFG2_SCFG_SHIFT 4
Dan Murphy827ed8a2020-10-07 10:53:41 -050075
76/* TDM Configuration Reg3 */
77#define TAS2764_TDM_CFG3 TAS2764_REG(0X0, 0x0c)
78#define TAS2764_TDM_CFG3_RXS_MASK GENMASK(7, 4)
79#define TAS2764_TDM_CFG3_RXS_SHIFT 0x4
80#define TAS2764_TDM_CFG3_MASK GENMASK(3, 0)
81
82/* TDM Configuration Reg5 */
83#define TAS2764_TDM_CFG5 TAS2764_REG(0X0, 0x0e)
84#define TAS2764_TDM_CFG5_VSNS_MASK BIT(6)
85#define TAS2764_TDM_CFG5_VSNS_ENABLE BIT(6)
86#define TAS2764_TDM_CFG5_50_MASK GENMASK(5, 0)
87
88/* TDM Configuration Reg6 */
89#define TAS2764_TDM_CFG6 TAS2764_REG(0X0, 0x0f)
90#define TAS2764_TDM_CFG6_ISNS_MASK BIT(6)
91#define TAS2764_TDM_CFG6_ISNS_ENABLE BIT(6)
92#define TAS2764_TDM_CFG6_50_MASK GENMASK(5, 0)
93
Martin Povišerdae191f2022-08-25 16:02:40 +020094/* Interrupt Masks */
95#define TAS2764_INT_MASK0 TAS2764_REG(0x0, 0x3b)
96#define TAS2764_INT_MASK1 TAS2764_REG(0x0, 0x3c)
97#define TAS2764_INT_MASK2 TAS2764_REG(0x0, 0x40)
98#define TAS2764_INT_MASK3 TAS2764_REG(0x0, 0x41)
99#define TAS2764_INT_MASK4 TAS2764_REG(0x0, 0x3d)
100
101/* Latched Fault Registers */
102#define TAS2764_INT_LTCH0 TAS2764_REG(0x0, 0x49)
103#define TAS2764_INT_LTCH1 TAS2764_REG(0x0, 0x4a)
104#define TAS2764_INT_LTCH1_0 TAS2764_REG(0x0, 0x4b)
105#define TAS2764_INT_LTCH2 TAS2764_REG(0x0, 0x4f)
106#define TAS2764_INT_LTCH3 TAS2764_REG(0x0, 0x50)
107#define TAS2764_INT_LTCH4 TAS2764_REG(0x0, 0x51)
108
109/* Clock/IRQ Settings */
110#define TAS2764_INT_CLK_CFG TAS2764_REG(0x0, 0x5c)
111#define TAS2764_INT_CLK_CFG_IRQZ_CLR BIT(2)
112
Dan Murphy827ed8a2020-10-07 10:53:41 -0500113#endif /* __TAS2764__ */