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android-kvm / linux / 1284ded7d05952f2657f5abeeda5a3f74ca9cffc / drivers / clk / sunxi-ng / ccu-sun6i-a31.c
  1. 7ec03b5 clk: sunxi-ng: Convert early providers to platform drivers by Samuel Holland · 3 years, 4 months ago
  2. 9bec2b9 clk: sunxi-ng: Unregister clocks/resets when unbinding by Samuel Holland · 3 years, 6 months ago
  3. 916f562 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux by Linus Torvalds · 6 years ago
  4. 8b1dd56 clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR by Chen-Yu Tsai · 6 years ago
  5. 9c92ab6 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 by Thomas Gleixner · 6 years ago
  6. 62e59c4 clk: Remove io.h from clk-provider.h by Stephen Boyd · 6 years ago
  7. ee0b27a clk: sunxi: A31: Fix wrong AHB gate number by Andre Przywara · 6 years ago
  8. 5682e26 clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops by Chen-Yu Tsai · 7 years ago
  9. ee6501d clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLL by Chen-Yu Tsai · 7 years ago
  10. 7f3ed79 clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision by Chen-Yu Tsai · 7 years ago
  11. 1667393 clk: Convert to using %pOF instead of full_name by Rob Herring · 8 years ago
  12. 13e0dde clk: sunxi-ng: Support multiple variable pre-dividers by Chen-Yu Tsai · 8 years ago
  13. 38b8f82 clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset by Chen-Yu Tsai · 8 years ago
  14. 9ad0bb3 clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock by Chen-Yu Tsai · 8 years ago
  15. 7042125 clk: sunxi-ng: A31: Fix spdif clock register by Marcus Cooper · 8 years ago
  16. 95881a5 clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it by Chen-Yu Tsai · 8 years ago
  17. a17b9e4 clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent by Chen-Yu Tsai · 8 years ago
  18. 5254223 clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk by Chen-Yu Tsai · 8 years ago
  19. d613782 clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs by Chen-Yu Tsai · 8 years ago
  20. d832fdd clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks by Chen-Yu Tsai · 8 years ago
  21. c6e6c96 clk: sunxi-ng: Add A31/A31s clocks by Chen-Yu Tsai · 9 years ago