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<h4 class="subsection">9.5.4 Pseudo Instructions</h4>

<p>The only available pseudo-instruction <code>__gcc_isr</code> can be activated by
option <samp><span class="option">-mgcc-isr</span></samp>.

     <dl>
<dt><code>__gcc_isr 1</code><dd>Emit code chunk to be used in avr-gcc ISR prologue. 
It will expand to at most six 1-word instructions, all optional:
push of <code>tmp_reg</code>, push of <code>SREG</code>,
push and clear of <code>zero_reg</code>, push of <var>Reg</var>.

     <br><dt><code>__gcc_isr 2</code><dd>Emit code chunk to be used in an avr-gcc ISR epilogue. 
It will expand to at most five 1-word instructions, all optional:
pop of <var>Reg</var>, pop of <code>zero_reg</code>,
pop of <code>SREG</code>, pop of <code>tmp_reg</code>.

     <br><dt><code>__gcc_isr 0, </code><var>Reg</var><dd>Finish avr-gcc ISR function.  Scan code since the last prologue
for usage of: <code>SREG</code>, <code>tmp_reg</code>, <code>zero_reg</code>. 
Prologue chunk and epilogue chunks will be replaced by appropriate code
to save / restore <code>SREG</code>, <code>tmp_reg</code>, <code>zero_reg</code> and <var>Reg</var>.

   </dl>

   <p>Example input:

<pre class="example">     __vector1:
         __gcc_isr 1
         lds r24, var
         inc r24
         sts var, r24
         __gcc_isr 2
         reti
         __gcc_isr 0, r24
</pre>
   <p>Example output:

<pre class="example">     00000000 &lt;__vector1&gt;:
        0:   8f 93           push    r24
        2:   8f b7           in      r24, 0x3f
        4:   8f 93           push    r24
        6:   80 91 60 00     lds     r24, 0x0060     ; 0x800060 &lt;var&gt;
        a:   83 95           inc     r24
        c:   80 93 60 00     sts     0x0060, r24     ; 0x800060 &lt;var&gt;
       10:   8f 91           pop     r24
       12:   8f bf           out     0x3f, r24
       14:   8f 91           pop     r24
       16:   18 95           reti
</pre>
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