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<h4 class="subsection">9.23.1 M68HC11 and M68HC12 Options</h4>

<p><a name="index-options_002c-M68HC11-1459"></a><a name="index-M68HC11-options-1460"></a>The Motorola 68HC11 and 68HC12 version of <code>as</code> have a few machine
dependent options.

     
<a name="index-g_t_0040samp_007b_002dm68hc11_007d-1461"></a>
<dl><dt><code>-m68hc11</code><dd>This option switches the assembler into the M68HC11 mode. In this mode,
the assembler only accepts 68HC11 operands and mnemonics. It produces
code for the 68HC11.

     <p><a name="index-g_t_0040samp_007b_002dm68hc12_007d-1462"></a><br><dt><code>-m68hc12</code><dd>This option switches the assembler into the M68HC12 mode. In this mode,
the assembler also accepts 68HC12 operands and mnemonics. It produces
code for the 68HC12. A few 68HC11 instructions are replaced by
some 68HC12 instructions as recommended by Motorola specifications.

     <p><a name="index-g_t_0040samp_007b_002dm68hcs12_007d-1463"></a><br><dt><code>-m68hcs12</code><dd>This option switches the assembler into the M68HCS12 mode.  This mode is
similar to &lsquo;<samp><span class="samp">-m68hc12</span></samp>&rsquo; but specifies to assemble for the 68HCS12
series.  The only difference is on the assembling of the &lsquo;<samp><span class="samp">movb</span></samp>&rsquo;
and &lsquo;<samp><span class="samp">movw</span></samp>&rsquo; instruction when a PC-relative operand is used.

     <p><a name="index-g_t_0040samp_007b_002dmm9s12x_007d-1464"></a><br><dt><code>-mm9s12x</code><dd>This option switches the assembler into the M9S12X mode.  This mode is
similar to &lsquo;<samp><span class="samp">-m68hc12</span></samp>&rsquo; but specifies to assemble for the S12X
series which is a superset of the HCS12.

     <p><a name="index-g_t_0040samp_007b_002dmm9s12xg_007d-1465"></a><br><dt><code>-mm9s12xg</code><dd>This option switches the assembler into the XGATE mode for the RISC
co-processor featured on some S12X-family chips.

     <p><a name="index-g_t_0040samp_007b_002d_002dxgate_002dramoffset_007d-1466"></a><br><dt><code>--xgate-ramoffset</code><dd>This option instructs the linker to offset RAM addresses from S12X address
space into XGATE address space.

     <p><a name="index-g_t_0040samp_007b_002dmshort_007d-1467"></a><br><dt><code>-mshort</code><dd>This option controls the ABI and indicates to use a 16-bit integer ABI. 
It has no effect on the assembled instructions. 
This is the default.

     <p><a name="index-g_t_0040samp_007b_002dmlong_007d-1468"></a><br><dt><code>-mlong</code><dd>This option controls the ABI and indicates to use a 32-bit integer ABI.

     <p><a name="index-g_t_0040samp_007b_002dmshort_002ddouble_007d-1469"></a><br><dt><code>-mshort-double</code><dd>This option controls the ABI and indicates to use a 32-bit float ABI. 
This is the default.

     <p><a name="index-g_t_0040samp_007b_002dmlong_002ddouble_007d-1470"></a><br><dt><code>-mlong-double</code><dd>This option controls the ABI and indicates to use a 64-bit float ABI.

     <p><a name="index-g_t_0040samp_007b_002d_002dstrict_002ddirect_002dmode_007d-1471"></a><br><dt><code>--strict-direct-mode</code><dd>You can use the &lsquo;<samp><span class="samp">--strict-direct-mode</span></samp>&rsquo; option to disable
the automatic translation of direct page mode addressing into
extended mode when the instruction does not support direct mode. 
For example, the &lsquo;<samp><span class="samp">clr</span></samp>&rsquo; instruction does not support direct page
mode addressing. When it is used with the direct page mode,
<code>as</code> will ignore it and generate an absolute addressing. 
This option prevents <code>as</code> from doing this, and the wrong
usage of the direct page mode will raise an error.

     <p><a name="index-g_t_0040samp_007b_002d_002dshort_002dbranches_007d-1472"></a><br><dt><code>--short-branches</code><dd>The &lsquo;<samp><span class="samp">--short-branches</span></samp>&rsquo; option turns off the translation of
relative branches into absolute branches when the branch offset is
out of range. By default <code>as</code> transforms the relative
branch (&lsquo;<samp><span class="samp">bsr</span></samp>&rsquo;, &lsquo;<samp><span class="samp">bgt</span></samp>&rsquo;, &lsquo;<samp><span class="samp">bge</span></samp>&rsquo;, &lsquo;<samp><span class="samp">beq</span></samp>&rsquo;, &lsquo;<samp><span class="samp">bne</span></samp>&rsquo;,
&lsquo;<samp><span class="samp">ble</span></samp>&rsquo;, &lsquo;<samp><span class="samp">blt</span></samp>&rsquo;, &lsquo;<samp><span class="samp">bhi</span></samp>&rsquo;, &lsquo;<samp><span class="samp">bcc</span></samp>&rsquo;, &lsquo;<samp><span class="samp">bls</span></samp>&rsquo;,
&lsquo;<samp><span class="samp">bcs</span></samp>&rsquo;, &lsquo;<samp><span class="samp">bmi</span></samp>&rsquo;, &lsquo;<samp><span class="samp">bvs</span></samp>&rsquo;, &lsquo;<samp><span class="samp">bvs</span></samp>&rsquo;, &lsquo;<samp><span class="samp">bra</span></samp>&rsquo;) into
an absolute branch when the offset is out of the -128 .. 127 range. 
In that case, the &lsquo;<samp><span class="samp">bsr</span></samp>&rsquo; instruction is translated into a
&lsquo;<samp><span class="samp">jsr</span></samp>&rsquo;, the &lsquo;<samp><span class="samp">bra</span></samp>&rsquo; instruction is translated into a
&lsquo;<samp><span class="samp">jmp</span></samp>&rsquo; and the conditional branches instructions are inverted and
followed by a &lsquo;<samp><span class="samp">jmp</span></samp>&rsquo;. This option disables these translations
and <code>as</code> will generate an error if a relative branch
is out of range. This option does not affect the optimization
associated to the &lsquo;<samp><span class="samp">jbra</span></samp>&rsquo;, &lsquo;<samp><span class="samp">jbsr</span></samp>&rsquo; and &lsquo;<samp><span class="samp">jbXX</span></samp>&rsquo; pseudo opcodes.

     <p><a name="index-g_t_0040samp_007b_002d_002dforce_002dlong_002dbranches_007d-1473"></a><br><dt><code>--force-long-branches</code><dd>The &lsquo;<samp><span class="samp">--force-long-branches</span></samp>&rsquo; option forces the translation of
relative branches into absolute branches. This option does not affect
the optimization associated to the &lsquo;<samp><span class="samp">jbra</span></samp>&rsquo;, &lsquo;<samp><span class="samp">jbsr</span></samp>&rsquo; and
&lsquo;<samp><span class="samp">jbXX</span></samp>&rsquo; pseudo opcodes.

     <p><a name="index-g_t_0040samp_007b_002d_002dprint_002dinsn_002dsyntax_007d-1474"></a><br><dt><code>--print-insn-syntax</code><dd>You can use the &lsquo;<samp><span class="samp">--print-insn-syntax</span></samp>&rsquo; option to obtain the
syntax description of the instruction when an error is detected.

     <p><a name="index-g_t_0040samp_007b_002d_002dprint_002dopcodes_007d-1475"></a><br><dt><code>--print-opcodes</code><dd>The &lsquo;<samp><span class="samp">--print-opcodes</span></samp>&rsquo; option prints the list of all the
instructions with their syntax. The first item of each line
represents the instruction name and the rest of the line indicates
the possible operands for that instruction. The list is printed
in alphabetical order. Once the list is printed <code>as</code>
exits.

     <p><a name="index-g_t_0040samp_007b_002d_002dgenerate_002dexample_007d-1476"></a><br><dt><code>--generate-example</code><dd>The &lsquo;<samp><span class="samp">--generate-example</span></samp>&rsquo; option is similar to &lsquo;<samp><span class="samp">--print-opcodes</span></samp>&rsquo;
but it generates an example for each instruction instead. 
</dl>

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