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<h5 class="subsubsection">9.24.2.2 Addressing Modes</h5>

<p><a name="index-S12Z-addressing-modes-1528"></a><a name="index-addressing-modes_002c-S12Z-1529"></a>
The following addressing modes are understood for the S12Z.
     <dl>
<dt><dfn>Immediate</dfn><dd>&lsquo;<samp><span class="samp">#</span><var>number</var></samp>&rsquo;

     <br><dt><dfn>Immediate Bit Field</dfn><dd>&lsquo;<samp><span class="samp">#</span><var>width</var><span class="samp">:</span><var>offset</var></samp>&rsquo;

     <p>Bit field instructions in the immediate mode require the width and offset to
be specified. 
The <var>width</var> parameter specifies the number of bits in the field. 
It should be a number in the range [1,32]. 
<var>Offset</var> determines the position within the field where the operation
should start. 
It should be a number in the range [0,31].

     <br><dt><dfn>Relative</dfn><dd>&lsquo;<samp><span class="samp">*</span><var>symbol</var></samp>&rsquo;, or &lsquo;<samp><span class="samp">*[+-]</span><var>digits</var></samp>&rsquo;

     <p>Program counter relative addresses have a width of 15 bits. 
Thus, they must be within the range [-32768, 32767].

     <br><dt><dfn>Register</dfn><dd>&lsquo;<samp><var>reg</var></samp>&rsquo;

     <p><a name="index-register-names_002c-S12Z-1530"></a>Some instructions accept a register as an operand. 
In general, <var>reg</var> may be a
data register (&lsquo;<samp><span class="samp">D0</span></samp>&rsquo;, &lsquo;<samp><span class="samp">D1</span></samp>&rsquo; <small class="dots">...</small> &lsquo;<samp><span class="samp">D7</span></samp>&rsquo;),
the &lsquo;<samp><span class="samp">X</span></samp>&rsquo; register or the &lsquo;<samp><span class="samp">Y</span></samp>&rsquo; register.

     <p>A few instructions accept as an argument the stack pointer
register (&lsquo;<samp><span class="samp">S</span></samp>&rsquo;), and/or the program counter (&lsquo;<samp><span class="samp">P</span></samp>&rsquo;).

     <p>Some very special instructions accept arguments which refer to the
condition code register.  For these arguments the  syntax is
&lsquo;<samp><span class="samp">CCR</span></samp>&rsquo;, &lsquo;<samp><span class="samp">CCH</span></samp>&rsquo; or &lsquo;<samp><span class="samp">CCL</span></samp>&rsquo; which refer to the complete
condition code register, the condition code register high byte
and the condition code register low byte respectively.

     <br><dt><dfn>Absolute Direct</dfn><dd>&lsquo;<samp><var>symbol</var></samp>&rsquo;, or &lsquo;<samp><var>digits</var></samp>&rsquo;

     <br><dt><dfn>Absolute Indirect</dfn><dd>&lsquo;<samp><span class="samp">[</span><var>symbol</var></samp>&rsquo;, or &lsquo;<samp><var>digits</var><span class="samp">]</span></samp>&rsquo;

     <br><dt><dfn>Constant Offset Indexed</dfn><dd>&lsquo;<samp><span class="samp">(</span><var>number</var><span class="samp">,</span><var>reg</var><span class="samp">)</span></samp>&rsquo;

     <p><var>Reg</var> may be either &lsquo;<samp><span class="samp">X</span></samp>&rsquo;, &lsquo;<samp><span class="samp">Y</span></samp>&rsquo;, &lsquo;<samp><span class="samp">S</span></samp>&rsquo; or
&lsquo;<samp><span class="samp">P</span></samp>&rsquo; or one of the data registers &lsquo;<samp><span class="samp">D0</span></samp>&rsquo;, &lsquo;<samp><span class="samp">D1</span></samp>&rsquo; <small class="dots">...</small>
&lsquo;<samp><span class="samp">D7</span></samp>&rsquo;. 
If any of the registers &lsquo;<samp><span class="samp">D2</span></samp>&rsquo; <small class="dots">...</small> &lsquo;<samp><span class="samp">D5</span></samp>&rsquo; are specified, then the
register value is treated as a signed value. 
Otherwise it is treated as unsigned. 
<var>Number</var> may be any integer in the range [-8388608,8388607].

     <br><dt><dfn>Offset Indexed Indirect</dfn><dd>&lsquo;<samp><span class="samp">[</span><var>number</var><span class="samp">,</span><var>reg</var><span class="samp">]</span></samp>&rsquo;

     <p><var>Reg</var> may be either &lsquo;<samp><span class="samp">X</span></samp>&rsquo;, &lsquo;<samp><span class="samp">Y</span></samp>&rsquo;, &lsquo;<samp><span class="samp">S</span></samp>&rsquo; or
&lsquo;<samp><span class="samp">P</span></samp>&rsquo;. 
<var>Number</var> may be any integer in the range [-8388608,8388607].

     <br><dt><dfn>Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement</dfn><dd>&lsquo;<samp><span class="samp">-</span><var>reg</var></samp>&rsquo;,
&lsquo;<samp><span class="samp">+</span><var>reg</var></samp>&rsquo;,
&lsquo;<samp><var>reg</var><span class="samp">-</span></samp>&rsquo; or
&lsquo;<samp><var>reg</var><span class="samp">+</span></samp>&rsquo;

     <p>This addressing mode is typically used to access a value at an address,
and simultaneously to increment/decrement the register pointing to that
address. 
Thus <var>reg</var> may be any of the 24 bit registers &lsquo;<samp><span class="samp">X</span></samp>&rsquo;, &lsquo;<samp><span class="samp">Y</span></samp>&rsquo;, or
&lsquo;<samp><span class="samp">S</span></samp>&rsquo;. 
Pre-increment and post-decrement are not available for
register &lsquo;<samp><span class="samp">S</span></samp>&rsquo; (only post-increment and pre-decrement are available).

     <br><dt><dfn>Register Offset Direct</dfn><dd>&lsquo;<samp><span class="samp">(</span><var>data-reg</var><span class="samp">,</span><var>reg</var><span class="samp">)</span></samp>&rsquo;

     <p><var>Reg</var> can be either &lsquo;<samp><span class="samp">X</span></samp>&rsquo;, &lsquo;<samp><span class="samp">Y</span></samp>&rsquo;, or &lsquo;<samp><span class="samp">S</span></samp>&rsquo;. 
<var>Data-reg</var>
must be one of the data registers &lsquo;<samp><span class="samp">D0</span></samp>&rsquo;, &lsquo;<samp><span class="samp">D1</span></samp>&rsquo; <small class="dots">...</small> &lsquo;<samp><span class="samp">D7</span></samp>&rsquo;. 
If any of the registers &lsquo;<samp><span class="samp">D2</span></samp>&rsquo; <small class="dots">...</small> &lsquo;<samp><span class="samp">D5</span></samp>&rsquo; are specified, then
the register value is treated as a signed value. 
Otherwise it is treated as unsigned.

     <br><dt><dfn>Register Offset Indirect</dfn><dd>&lsquo;<samp><span class="samp">[</span><var>data-reg</var><span class="samp">,</span><var>reg</var><span class="samp">]</span></samp>&rsquo;

     <p><var>Reg</var> can be either &lsquo;<samp><span class="samp">X</span></samp>&rsquo; or &lsquo;<samp><span class="samp">Y</span></samp>&rsquo;. 
<var>Data-reg</var>
must be one of the data registers &lsquo;<samp><span class="samp">D0</span></samp>&rsquo;, &lsquo;<samp><span class="samp">D1</span></samp>&rsquo; <small class="dots">...</small> &lsquo;<samp><span class="samp">D7</span></samp>&rsquo;. 
If any of the registers &lsquo;<samp><span class="samp">D2</span></samp>&rsquo; <small class="dots">...</small> &lsquo;<samp><span class="samp">D5</span></samp>&rsquo; are specified, then
the register value is treated as a signed value. 
Otherwise it is treated as unsigned. 
</dl>

   <p>For example:

<pre class="smallexample">     	trap    #197        ;; Immediate mode
     	bra     *+49        ;; Relative mode
     	bra     .L0         ;;     ditto
     	jmp     0xFE0034    ;; Absolute direct mode
     	jmp     [0xFD0012]  ;; Absolute indirect mode
     	inc.b   (4,x)       ;; Constant offset indexed mode
     	jsr     (45, d0)    ;;     ditto
     	dec.w   [4,y]       ;; Constant offset indexed indirect mode
     	clr.p   (-s)        ;; Pre-decrement mode
     	neg.l   (d0, s)     ;; Register offset direct mode
     	com.b   [d1, x]     ;; Register offset indirect mode
     	psh     cch         ;; Register mode
</pre>
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