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<h5 class="subsubsection">9.16.3.1 AT&amp;T Syntax versus Intel Syntax</h5>

<p><a name="index-i386-intel_005fsyntax-pseudo-op-1142"></a><a name="index-intel_005fsyntax-pseudo-op_002c-i386-1143"></a><a name="index-i386-att_005fsyntax-pseudo-op-1144"></a><a name="index-att_005fsyntax-pseudo-op_002c-i386-1145"></a><a name="index-i386-syntax-compatibility-1146"></a><a name="index-syntax-compatibility_002c-i386-1147"></a><a name="index-x86_002d64-intel_005fsyntax-pseudo-op-1148"></a><a name="index-intel_005fsyntax-pseudo-op_002c-x86_002d64-1149"></a><a name="index-x86_002d64-att_005fsyntax-pseudo-op-1150"></a><a name="index-att_005fsyntax-pseudo-op_002c-x86_002d64-1151"></a><a name="index-x86_002d64-syntax-compatibility-1152"></a><a name="index-syntax-compatibility_002c-x86_002d64-1153"></a>
<code>as</code> now supports assembly using Intel assembler syntax. 
<code>.intel_syntax</code> selects Intel mode, and <code>.att_syntax</code> switches
back to the usual AT&amp;T mode for compatibility with the output of
<code>gcc</code>.  Either of these directives may have an optional
argument, <code>prefix</code>, or <code>noprefix</code> specifying whether registers
require a &lsquo;<samp><span class="samp">%</span></samp>&rsquo; prefix.  AT&amp;T System V/386 assembler syntax is quite
different from Intel syntax.  We mention these differences because
almost all 80386 documents use Intel syntax.  Notable differences
between the two syntaxes are:

   <p><a name="index-immediate-operands_002c-i386-1154"></a><a name="index-i386-immediate-operands-1155"></a><a name="index-register-operands_002c-i386-1156"></a><a name="index-i386-register-operands-1157"></a><a name="index-jump_002fcall-operands_002c-i386-1158"></a><a name="index-i386-jump_002fcall-operands-1159"></a><a name="index-operand-delimiters_002c-i386-1160"></a>
<a name="index-immediate-operands_002c-x86_002d64-1161"></a><a name="index-x86_002d64-immediate-operands-1162"></a><a name="index-register-operands_002c-x86_002d64-1163"></a><a name="index-x86_002d64-register-operands-1164"></a><a name="index-jump_002fcall-operands_002c-x86_002d64-1165"></a><a name="index-x86_002d64-jump_002fcall-operands-1166"></a><a name="index-operand-delimiters_002c-x86_002d64-1167"></a>
     <ul>
<li>AT&amp;T immediate operands are preceded by &lsquo;<samp><span class="samp">$</span></samp>&rsquo;; Intel immediate
operands are undelimited (Intel &lsquo;<samp><span class="samp">push 4</span></samp>&rsquo; is AT&amp;T &lsquo;<samp><span class="samp">pushl $4</span></samp>&rsquo;). 
AT&amp;T register operands are preceded by &lsquo;<samp><span class="samp">%</span></samp>&rsquo;; Intel register operands
are undelimited.  AT&amp;T absolute (as opposed to PC relative) jump/call
operands are prefixed by &lsquo;<samp><span class="samp">*</span></samp>&rsquo;; they are undelimited in Intel syntax.

     <p><a name="index-i386-source_002c-destination-operands-1168"></a><a name="index-source_002c-destination-operands_003b-i386-1169"></a><a name="index-x86_002d64-source_002c-destination-operands-1170"></a><a name="index-source_002c-destination-operands_003b-x86_002d64-1171"></a><li>AT&amp;T and Intel syntax use the opposite order for source and destination
operands.  Intel &lsquo;<samp><span class="samp">add eax, 4</span></samp>&rsquo; is &lsquo;<samp><span class="samp">addl $4, %eax</span></samp>&rsquo;.  The
&lsquo;<samp><span class="samp">source, dest</span></samp>&rsquo; convention is maintained for compatibility with
previous Unix assemblers.  Note that &lsquo;<samp><span class="samp">bound</span></samp>&rsquo;, &lsquo;<samp><span class="samp">invlpga</span></samp>&rsquo;, and
instructions with 2 immediate operands, such as the &lsquo;<samp><span class="samp">enter</span></samp>&rsquo;
instruction, do <em>not</em> have reversed order.  <a href="i386_002dBugs.html#i386_002dBugs">i386-Bugs</a>.

     <p><a name="index-mnemonic-suffixes_002c-i386-1172"></a><a name="index-sizes-operands_002c-i386-1173"></a><a name="index-i386-size-suffixes-1174"></a><a name="index-mnemonic-suffixes_002c-x86_002d64-1175"></a><a name="index-sizes-operands_002c-x86_002d64-1176"></a><a name="index-x86_002d64-size-suffixes-1177"></a><li>In AT&amp;T syntax the size of memory operands is determined from the last
character of the instruction mnemonic.  Mnemonic suffixes of &lsquo;<samp><span class="samp">b</span></samp>&rsquo;,
&lsquo;<samp><span class="samp">w</span></samp>&rsquo;, &lsquo;<samp><span class="samp">l</span></samp>&rsquo; and &lsquo;<samp><span class="samp">q</span></samp>&rsquo; specify byte (8-bit), word (16-bit), long
(32-bit) and quadruple word (64-bit) memory references.  Mnemonic suffixes
of &lsquo;<samp><span class="samp">x</span></samp>&rsquo;, &lsquo;<samp><span class="samp">y</span></samp>&rsquo; and &lsquo;<samp><span class="samp">z</span></samp>&rsquo; specify xmm (128-bit vector), ymm
(256-bit vector) and zmm (512-bit vector) memory references, only when there's
no other way to disambiguate an instruction.  Intel syntax accomplishes this by
prefixing memory operands (<em>not</em> the instruction mnemonics) with
&lsquo;<samp><span class="samp">byte ptr</span></samp>&rsquo;, &lsquo;<samp><span class="samp">word ptr</span></samp>&rsquo;, &lsquo;<samp><span class="samp">dword ptr</span></samp>&rsquo;, &lsquo;<samp><span class="samp">qword ptr</span></samp>&rsquo;,
&lsquo;<samp><span class="samp">xmmword ptr</span></samp>&rsquo;, &lsquo;<samp><span class="samp">ymmword ptr</span></samp>&rsquo; and &lsquo;<samp><span class="samp">zmmword ptr</span></samp>&rsquo;.  Thus, Intel
syntax &lsquo;<samp><span class="samp">mov al, byte ptr </span><var>foo</var></samp>&rsquo; is &lsquo;<samp><span class="samp">movb </span><var>foo</var><span class="samp">, %al</span></samp>&rsquo; in AT&amp;T
syntax.  In Intel syntax, &lsquo;<samp><span class="samp">fword ptr</span></samp>&rsquo;, &lsquo;<samp><span class="samp">tbyte ptr</span></samp>&rsquo; and
&lsquo;<samp><span class="samp">oword ptr</span></samp>&rsquo; specify 48-bit, 80-bit and 128-bit memory references.

     <p>In 64-bit code, &lsquo;<samp><span class="samp">movabs</span></samp>&rsquo; can be used to encode the &lsquo;<samp><span class="samp">mov</span></samp>&rsquo;
instruction with the 64-bit displacement or immediate operand.

     <p><a name="index-return-instructions_002c-i386-1178"></a><a name="index-i386-jump_002c-call_002c-return-1179"></a><a name="index-return-instructions_002c-x86_002d64-1180"></a><a name="index-x86_002d64-jump_002c-call_002c-return-1181"></a><li>Immediate form long jumps and calls are
&lsquo;<samp><span class="samp">lcall/ljmp $</span><var>section</var><span class="samp">, $</span><var>offset</var></samp>&rsquo; in AT&amp;T syntax; the
Intel syntax is
&lsquo;<samp><span class="samp">call/jmp far </span><var>section</var><span class="samp">:</span><var>offset</var></samp>&rsquo;.  Also, the far return
instruction
is &lsquo;<samp><span class="samp">lret $</span><var>stack-adjust</var></samp>&rsquo; in AT&amp;T syntax; Intel syntax is
&lsquo;<samp><span class="samp">ret far </span><var>stack-adjust</var></samp>&rsquo;.

     <p><a name="index-sections_002c-i386-1182"></a><a name="index-i386-sections-1183"></a><a name="index-sections_002c-x86_002d64-1184"></a><a name="index-x86_002d64-sections-1185"></a><li>The AT&amp;T assembler does not provide support for multiple section
programs.  Unix style systems expect all programs to be single sections. 
</ul>

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