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<h4 class="subsection">G.5.8 NDS32 Features</h4>

<p><a name="index-target-descriptions_002c-NDS32-features-3665"></a>
The &lsquo;<samp><span class="samp">org.gnu.gdb.nds32.core</span></samp>&rsquo; feature is required for NDS32
targets.  It should contain at least registers &lsquo;<samp><span class="samp">r0</span></samp>&rsquo; through
&lsquo;<samp><span class="samp">r10</span></samp>&rsquo;, &lsquo;<samp><span class="samp">r15</span></samp>&rsquo;, &lsquo;<samp><span class="samp">fp</span></samp>&rsquo;, &lsquo;<samp><span class="samp">gp</span></samp>&rsquo;, &lsquo;<samp><span class="samp">lp</span></samp>&rsquo;, &lsquo;<samp><span class="samp">sp</span></samp>&rsquo;,
and &lsquo;<samp><span class="samp">pc</span></samp>&rsquo;.

   <p>The &lsquo;<samp><span class="samp">org.gnu.gdb.nds32.fpu</span></samp>&rsquo; feature is optional.  If present,
it should contain 64-bit double-precision floating-point registers
&lsquo;<samp><span class="samp">fd0</span></samp>&rsquo; through <em>fdN</em>, which should be &lsquo;<samp><span class="samp">fd3</span></samp>&rsquo;, &lsquo;<samp><span class="samp">fd7</span></samp>&rsquo;,
&lsquo;<samp><span class="samp">fd15</span></samp>&rsquo;, or &lsquo;<samp><span class="samp">fd31</span></samp>&rsquo; based on the FPU configuration implemented.

   <p><em>Note:</em> The first sixteen 64-bit double-precision floating-point
registers are overlapped with the thirty-two 32-bit single-precision
floating-point registers.  The 32-bit single-precision registers, if
not being listed explicitly, will be synthesized from halves of the
overlapping 64-bit double-precision registers.  Listing 32-bit
single-precision registers explicitly is deprecated, and the
support to it could be totally removed some day.

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