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<h4 class="subsection">G.5.15 TMS320C6x Features</h4>

<p><a name="index-target-descriptions_002c-TIC6x-features-3674"></a><a name="index-target-descriptions_002c-TMS320C6x-features-3675"></a>The &lsquo;<samp><span class="samp">org.gnu.gdb.tic6x.core</span></samp>&rsquo; feature is required for TMS320C6x
targets.  It should contain registers &lsquo;<samp><span class="samp">A0</span></samp>&rsquo; through &lsquo;<samp><span class="samp">A15</span></samp>&rsquo;,
registers &lsquo;<samp><span class="samp">B0</span></samp>&rsquo; through &lsquo;<samp><span class="samp">B15</span></samp>&rsquo;, &lsquo;<samp><span class="samp">CSR</span></samp>&rsquo; and &lsquo;<samp><span class="samp">PC</span></samp>&rsquo;.

   <p>The &lsquo;<samp><span class="samp">org.gnu.gdb.tic6x.gp</span></samp>&rsquo; feature is optional.  It should
contain registers &lsquo;<samp><span class="samp">A16</span></samp>&rsquo; through &lsquo;<samp><span class="samp">A31</span></samp>&rsquo; and &lsquo;<samp><span class="samp">B16</span></samp>&rsquo;
through &lsquo;<samp><span class="samp">B31</span></samp>&rsquo;.

   <p>The &lsquo;<samp><span class="samp">org.gnu.gdb.tic6x.c6xp</span></samp>&rsquo; feature is optional.  It should
contain registers &lsquo;<samp><span class="samp">TSR</span></samp>&rsquo;, &lsquo;<samp><span class="samp">ILC</span></samp>&rsquo; and &lsquo;<samp><span class="samp">RILC</span></samp>&rsquo;.

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