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<a name="define_005fpeephole2"></a>
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<p>
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<hr>
<a name="RTL-to-RTL-Peephole-Optimizers"></a>
<h4 class="subsection">16.18.2 RTL to RTL Peephole Optimizers</h4>
<a name="index-define_005fpeephole2"></a>

<p>The <code>define_peephole2</code> definition tells the compiler how to
substitute one sequence of instructions for another sequence,
what additional scratch registers may be needed and what their
lifetimes must be.
</p>
<div class="smallexample">
<pre class="smallexample">(define_peephole2
  [<var>insn-pattern-1</var>
   <var>insn-pattern-2</var>
   &hellip;]
  &quot;<var>condition</var>&quot;
  [<var>new-insn-pattern-1</var>
   <var>new-insn-pattern-2</var>
   &hellip;]
  &quot;<var>preparation-statements</var>&quot;)
</pre></div>

<p>The definition is almost identical to <code>define_split</code>
(see <a href="Insn-Splitting.html#Insn-Splitting">Insn Splitting</a>) except that the pattern to match is not a
single instruction, but a sequence of instructions.
</p>
<p>It is possible to request additional scratch registers for use in the
output template.  If appropriate registers are not free, the pattern
will simply not match.
</p>
<a name="index-match_005fscratch-1"></a>
<a name="index-match_005fdup-1"></a>
<p>Scratch registers are requested with a <code>match_scratch</code> pattern at
the top level of the input pattern.  The allocated register (initially) will
be dead at the point requested within the original sequence.  If the scratch
is used at more than a single point, a <code>match_dup</code> pattern at the
top level of the input pattern marks the last position in the input sequence
at which the register must be available.
</p>
<p>Here is an example from the IA-32 machine description:
</p>
<div class="smallexample">
<pre class="smallexample">(define_peephole2
  [(match_scratch:SI 2 &quot;r&quot;)
   (parallel [(set (match_operand:SI 0 &quot;register_operand&quot; &quot;&quot;)
                   (match_operator:SI 3 &quot;arith_or_logical_operator&quot;
                     [(match_dup 0)
                      (match_operand:SI 1 &quot;memory_operand&quot; &quot;&quot;)]))
              (clobber (reg:CC 17))])]
  &quot;! optimize_size &amp;&amp; ! TARGET_READ_MODIFY&quot;
  [(set (match_dup 2) (match_dup 1))
   (parallel [(set (match_dup 0)
                   (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
              (clobber (reg:CC 17))])]
  &quot;&quot;)
</pre></div>

<p>This pattern tries to split a load from its use in the hopes that we&rsquo;ll be
able to schedule around the memory load latency.  It allocates a single
<code>SImode</code> register of class <code>GENERAL_REGS</code> (<code>&quot;r&quot;</code>) that needs
to be live only at the point just before the arithmetic.
</p>
<p>A real example requiring extended scratch lifetimes is harder to come by,
so here&rsquo;s a silly made-up example:
</p>
<div class="smallexample">
<pre class="smallexample">(define_peephole2
  [(match_scratch:SI 4 &quot;r&quot;)
   (set (match_operand:SI 0 &quot;&quot; &quot;&quot;) (match_operand:SI 1 &quot;&quot; &quot;&quot;))
   (set (match_operand:SI 2 &quot;&quot; &quot;&quot;) (match_dup 1))
   (match_dup 4)
   (set (match_operand:SI 3 &quot;&quot; &quot;&quot;) (match_dup 1))]
  &quot;/* <span class="roman">determine 1 does not overlap 0 and 2</span> */&quot;
  [(set (match_dup 4) (match_dup 1))
   (set (match_dup 0) (match_dup 4))
   (set (match_dup 2) (match_dup 4))
   (set (match_dup 3) (match_dup 4))]
  &quot;&quot;)
</pre></div>

<p>If we had not added the <code>(match_dup 4)</code> in the middle of the input
sequence, it might have been the case that the register we chose at the
beginning of the sequence is killed by the first or second <code>set</code>.
</p>
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