fix(arm_fpga): Change PL011 UART IRQ
About a year ago there was a change in the underlying Arm platform design
framework, which lead to a reorganisation of the interrupt map (to make
room for multi-chip designs).
This lead to the PL011 debug UART interrupt to move from SPI 115 to SPI
415. Unfortunately there is not a good or easy way to auto-detect this
change: Flooding the TX FIFO and checking GICD_ISPENDR registers might
be possible, but sounds a bit over the top for BL31.
So we would need to break one group of images: newer ones, as we do right
now, or older ones.
By now every interesting FPGA image seems to use the newer IRQ, so in
the interest of having a smooth experience for most users, lets switch
to this IRQ.
When people are interested in older images, they can either change the
number back in the .dts file, or provide a patched DTB on the FPGA
command line.
Change-Id: I3c7e7b711f5142813bd94eecde3095a4fc555bb3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/fdts/arm_fpga.dts b/fdts/arm_fpga.dts
index b7b4f0e..0fca30c 100644
--- a/fdts/arm_fpga.dts
+++ b/fdts/arm_fpga.dts
@@ -82,7 +82,7 @@
dbg_uart: serial@7ff80000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x7ff80000 0x0 0x00001000>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uartclk>, <&bus_refclk>;
clock-names = "uartclk", "apb_pclk";
};
