Merge "fix: remove "experimental" tag for stable features" into integration
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index 795c586..7d77f47 100644
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S
@@ -100,11 +100,27 @@
* sections. This is done to safeguard against
* possible corruption of this memory by dirty
* cache lines in a system cache as a result of
- * use by an earlier boot loader stage.
+ * use by an earlier boot loader stage. If PIE
+ * is enabled however, RO sections including the
+ * GOT may be modified during pie fixup.
+ * Therefore, to be on the safe side, invalidate
+ * the entire image region if PIE is enabled.
* ---------------------------------------------
*/
- adr x0, __RW_START__
- adr x1, __RW_END__
+#if ENABLE_PIE
+#if SEPARATE_CODE_AND_RODATA
+ adrp x0, __TEXT_START__
+ add x0, x0, :lo12:__TEXT_START__
+#else
+ adrp x0, __RO_START__
+ add x0, x0, :lo12:__RO_START__
+#endif /* SEPARATE_CODE_AND_RODATA */
+#else
+ adrp x0, __RW_START__
+ add x0, x0, :lo12:__RW_START__
+#endif /* ENABLE_PIE */
+ adrp x1, __RW_END__
+ add x1, x1, :lo12:__RW_END__
sub x1, x1, x0
bl inv_dcache_range
diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst
index 17f7a86..af302c6 100644
--- a/docs/plat/stm32mp1.rst
+++ b/docs/plat/stm32mp1.rst
@@ -181,6 +181,7 @@
.. code:: bash
make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
+ AARCH32_SP=optee \
DTB_FILE_NAME=stm32mp157c-ev1.dtb \
BL33=<u-boot_directory>/u-boot-nodtb.bin \
BL33_CFG=<u-boot_directory>/u-boot.dtb \
diff --git a/drivers/arm/css/scp/css_pm_scmi.c b/drivers/arm/css/scp/css_pm_scmi.c
index aeb7eda..5de2604 100644
--- a/drivers/arm/css/scp/css_pm_scmi.c
+++ b/drivers/arm/css/scp/css_pm_scmi.c
@@ -357,7 +357,7 @@
unsigned int composite_id, idx;
for (idx = 0; idx < PLAT_ARM_SCMI_CHANNEL_COUNT; idx++) {
- INFO("Initializing driver on Channel %d\n", idx);
+ INFO("Initializing SCMI driver on channel %d\n", idx);
scmi_channels[idx].info = plat_css_get_scmi_info(idx);
scmi_channels[idx].lock = ARM_SCMI_LOCK_GET_INSTANCE;
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S
index 65f9a8e..ad2a039 100644
--- a/include/arch/aarch32/el3_common_macros.S
+++ b/include/arch/aarch32/el3_common_macros.S
@@ -380,10 +380,21 @@
* includes the data and NOBITS sections. This is done to
* safeguard against possible corruption of this memory by
* dirty cache lines in a system cache as a result of use by
- * an earlier boot loader stage.
+ * an earlier boot loader stage. If PIE is enabled however,
+ * RO sections including the GOT may be modified during
+ * pie fixup. Therefore, to be on the safe side, invalidate
+ * the entire image region if PIE is enabled.
* -----------------------------------------------------------------
*/
+#if ENABLE_PIE
+#if SEPARATE_CODE_AND_RODATA
+ ldr r0, =__TEXT_START__
+#else
+ ldr r0, =__RO_START__
+#endif /* SEPARATE_CODE_AND_RODATA */
+#else
ldr r0, =__RW_START__
+#endif /* ENABLE_PIE */
ldr r1, =__RW_END__
sub r1, r1, r0
bl inv_dcache_range
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 7d6a963..8e8d334 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -430,11 +430,24 @@
* includes the data and NOBITS sections. This is done to
* safeguard against possible corruption of this memory by
* dirty cache lines in a system cache as a result of use by
- * an earlier boot loader stage.
+ * an earlier boot loader stage. If PIE is enabled however,
+ * RO sections including the GOT may be modified during
+ * pie fixup. Therefore, to be on the safe side, invalidate
+ * the entire image region if PIE is enabled.
* -------------------------------------------------------------
*/
+#if ENABLE_PIE
+#if SEPARATE_CODE_AND_RODATA
+ adrp x0, __TEXT_START__
+ add x0, x0, :lo12:__TEXT_START__
+#else
+ adrp x0, __RO_START__
+ add x0, x0, :lo12:__RO_START__
+#endif /* SEPARATE_CODE_AND_RODATA */
+#else
adrp x0, __RW_START__
add x0, x0, :lo12:__RW_START__
+#endif /* ENABLE_PIE */
adrp x1, __RW_END__
add x1, x1, :lo12:__RW_END__
sub x1, x1, x0
diff --git a/include/lib/cpus/aarch64/cortex_demeter.h b/include/lib/cpus/aarch64/cortex_hunter.h
similarity index 65%
rename from include/lib/cpus/aarch64/cortex_demeter.h
rename to include/lib/cpus/aarch64/cortex_hunter.h
index 9dd0987..8b59fd9 100644
--- a/include/lib/cpus/aarch64/cortex_demeter.h
+++ b/include/lib/cpus/aarch64/cortex_hunter.h
@@ -4,20 +4,20 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef CORTEX_DEMETER_H
-#define CORTEX_DEMETER_H
+#ifndef CORTEX_HUNTER_H
+#define CORTEX_HUNTER_H
-#define CORTEX_DEMETER_MIDR U(0x410FD4F0)
+#define CORTEX_HUNTER_MIDR U(0x410FD810)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
-#define CORTEX_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_HUNTER_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
-#define CORTEX_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+#define CORTEX_HUNTER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-#endif /* CORTEX_DEMETER_H */
+#endif /* CORTEX_HUNTER_H */
diff --git a/include/lib/cpus/aarch64/cortex_demeter.h b/include/lib/cpus/aarch64/neoverse_demeter.h
similarity index 64%
copy from include/lib/cpus/aarch64/cortex_demeter.h
copy to include/lib/cpus/aarch64/neoverse_demeter.h
index 9dd0987..230ed66 100644
--- a/include/lib/cpus/aarch64/cortex_demeter.h
+++ b/include/lib/cpus/aarch64/neoverse_demeter.h
@@ -4,20 +4,20 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef CORTEX_DEMETER_H
-#define CORTEX_DEMETER_H
+#ifndef NEOVERSE_DEMETER_H
+#define NEOVERSE_DEMETER_H
-#define CORTEX_DEMETER_MIDR U(0x410FD4F0)
+#define NEOVERSE_DEMETER_MIDR U(0x410FD4F0)
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
-#define CORTEX_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4
+#define NEOVERSE_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
-#define CORTEX_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-#endif /* CORTEX_DEMETER_H */
+#endif /* NEOVERSE_DEMETER_H */
diff --git a/lib/cpus/aarch64/cortex_demeter.S b/lib/cpus/aarch64/cortex_demeter.S
deleted file mode 100644
index 9ad8b86..0000000
--- a/lib/cpus/aarch64/cortex_demeter.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_demeter.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Demeter must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Demeter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func cortex_demeter_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_DEMETER_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_DEMETER_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc cortex_demeter_core_pwr_dwn
-
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex Demeter. Must follow AAPCS.
- */
-func cortex_demeter_errata_report
- ret
-endfunc cortex_demeter_errata_report
-#endif
-
-func cortex_demeter_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
- isb
- ret
-endfunc cortex_demeter_reset_func
-
- /* ---------------------------------------------
- * This function provides Cortex Demeter-
- * specific register information for crash
- * reporting. It needs to return with x6
- * pointing to a list of register names in ascii
- * and x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.cortex_demeter_regs, "aS"
-cortex_demeter_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func cortex_demeter_cpu_reg_dump
- adr x6, cortex_demeter_regs
- mrs x8, CORTEX_DEMETER_CPUECTLR_EL1
- ret
-endfunc cortex_demeter_cpu_reg_dump
-
-declare_cpu_ops cortex_demeter, CORTEX_DEMETER_MIDR, \
- cortex_demeter_reset_func, \
- cortex_demeter_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_hunter.S b/lib/cpus/aarch64/cortex_hunter.S
new file mode 100644
index 0000000..2ab4296
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_hunter.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_hunter.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex Hunter must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex Hunter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+func cortex_hunter_reset_func
+ /* Disable speculative loads */
+ msr SSBS, xzr
+ isb
+ ret
+endfunc cortex_hunter_reset_func
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_hunter_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, CORTEX_HUNTER_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_HUNTER_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_hunter_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex Hunter. Must follow AAPCS.
+ */
+func cortex_hunter_errata_report
+ ret
+endfunc cortex_hunter_errata_report
+#endif
+
+ /* ---------------------------------------------
+ * This function provides Cortex Hunter-specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_hunter_regs, "aS"
+cortex_hunter_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_hunter_cpu_reg_dump
+ adr x6, cortex_hunter_regs
+ mrs x8, CORTEX_HUNTER_CPUECTLR_EL1
+ ret
+endfunc cortex_hunter_cpu_reg_dump
+
+declare_cpu_ops cortex_hunter, CORTEX_HUNTER_MIDR, \
+ cortex_hunter_reset_func, \
+ cortex_hunter_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_demeter.S b/lib/cpus/aarch64/neoverse_demeter.S
new file mode 100644
index 0000000..f43c18b
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_demeter.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <neoverse_demeter.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse Demeter must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Neoverse Demeter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func neoverse_demeter_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, NEOVERSE_DEMETER_CPUPWRCTLR_EL1
+ orr x0, x0, #NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr NEOVERSE_DEMETER_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc neoverse_demeter_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Neoverse Demeter. Must follow AAPCS.
+ */
+func neoverse_demeter_errata_report
+ ret
+endfunc neoverse_demeter_errata_report
+#endif
+
+func neoverse_demeter_reset_func
+ /* Disable speculative loads */
+ msr SSBS, xzr
+ isb
+ ret
+endfunc neoverse_demeter_reset_func
+
+ /* ---------------------------------------------
+ * This function provides Neoverse Demeter-
+ * specific register information for crash
+ * reporting. It needs to return with x6
+ * pointing to a list of register names in ascii
+ * and x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.neoverse_demeter_regs, "aS"
+neoverse_demeter_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func neoverse_demeter_cpu_reg_dump
+ adr x6, neoverse_demeter_regs
+ mrs x8, NEOVERSE_DEMETER_CPUECTLR_EL1
+ ret
+endfunc neoverse_demeter_cpu_reg_dump
+
+declare_cpu_ops neoverse_demeter, NEOVERSE_DEMETER_MIDR, \
+ neoverse_demeter_reset_func, \
+ neoverse_demeter_core_pwr_dwn
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index cad888f..c26b519 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -45,12 +45,10 @@
};
#endif
-#if !defined(SPD_spmd)
nt_fw-config {
load-address = <0x0 0x80000000>;
max-size = <0x200>;
id = <NT_FW_CONFIG_ID>;
};
-#endif
};
};
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 70b1051..fd27acb 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -130,16 +130,17 @@
lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
+ lib/cpus/aarch64/neoverse_demeter.S \
lib/cpus/aarch64/cortex_a78_ae.S \
lib/cpus/aarch64/cortex_a510.S \
lib/cpus/aarch64/cortex_a710.S \
lib/cpus/aarch64/cortex_makalu.S \
lib/cpus/aarch64/cortex_makalu_elp_arm.S \
- lib/cpus/aarch64/cortex_demeter.S \
lib/cpus/aarch64/cortex_a65.S \
lib/cpus/aarch64/cortex_a65ae.S \
lib/cpus/aarch64/cortex_a78c.S \
- lib/cpus/aarch64/cortex_hayes.S
+ lib/cpus/aarch64/cortex_hayes.S \
+ lib/cpus/aarch64/cortex_hunter.S
endif
# AArch64/AArch32 cores
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 6472590..a6f7df5 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -218,6 +218,10 @@
* Linux kernel tree, Linux expects the physical address of the device
* tree blob (DTB) in x0, while x1-x3 are reserved for future use and
* must be 0.
+ * Repurpose the option to load Hafnium hypervisor in the normal world.
+ * It expects its manifest address in x0. This is essentially the linux
+ * dts (passed to the primary VM) by adding 'hypervisor' and chosen
+ * nodes specifying the Hypervisor configuration.
*/
#if RESET_TO_BL31
bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
@@ -228,14 +232,6 @@
bl33_image_ep_info.args.arg2 = 0U;
bl33_image_ep_info.args.arg3 = 0U;
# endif
-
-#if defined(SPD_spmd)
- /*
- * Hafnium in normal world expects its manifest address in x0, In CI
- * configuration manifest is preloaded at 0x80000000(start of DRAM).
- */
- bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE;
-#endif
}
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
diff --git a/services/std_svc/sdei/sdei_intr_mgmt.c b/services/std_svc/sdei/sdei_intr_mgmt.c
index 5d176c2..399c2ec 100644
--- a/services/std_svc/sdei/sdei_intr_mgmt.c
+++ b/services/std_svc/sdei/sdei_intr_mgmt.c
@@ -531,7 +531,7 @@
if (is_event_shared(map))
sdei_map_unlock(map);
- SDEI_LOG("ACK %llx, ev:%d ss:%d spsr:%lx ELR:%lx\n", mpidr, map->ev_num,
+ SDEI_LOG("ACK %llx, ev:0x%x ss:%d spsr:%lx ELR:%lx\n", mpidr, map->ev_num,
sec_state, read_spsr_el3(), read_elr_el3());
ctx = handle;
@@ -568,7 +568,7 @@
* interrupt.
*/
if ((map->ev_num != SDEI_EVENT_0) && !is_map_bound(map)) {
- ERROR("Invalid SDEI mapping: ev=%u\n", map->ev_num);
+ ERROR("Invalid SDEI mapping: ev=0x%x\n", map->ev_num);
panic();
}
plat_ic_end_of_interrupt(intr_raw);
@@ -703,7 +703,7 @@
/* Having done sanity checks, pop dispatch */
(void) pop_dispatch();
- SDEI_LOG("EOI:%lx, %d spsr:%lx elr:%lx\n", read_mpidr_el1(),
+ SDEI_LOG("EOI:%lx, 0x%x spsr:%lx elr:%lx\n", read_mpidr_el1(),
map->ev_num, read_spsr_el3(), read_elr_el3());
/*
diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c
index 5371df1..4ceaae8 100644
--- a/services/std_svc/sdei/sdei_main.c
+++ b/services/std_svc/sdei/sdei_main.c
@@ -966,7 +966,7 @@
case SDEI_EVENT_REGISTER:
x5 = SMC_GET_GP(ctx, CTX_GPREG_X5);
- SDEI_LOG("> REG(n:%d e:%llx a:%llx f:%x m:%llx)\n", ev_num,
+ SDEI_LOG("> REG(n:0x%x e:%llx a:%llx f:%x m:%llx)\n", ev_num,
x2, x3, (int) x4, x5);
ret = sdei_event_register(ev_num, x2, x3, x4, x5);
SDEI_LOG("< REG:%lld\n", ret);
@@ -979,7 +979,7 @@
SMC_RET1(ctx, ret);
case SDEI_EVENT_DISABLE:
- SDEI_LOG("> DISABLE(n:%d)\n", ev_num);
+ SDEI_LOG("> DISABLE(n:0x%x)\n", ev_num);
ret = sdei_event_disable(ev_num);
SDEI_LOG("< DISABLE:%lld\n", ret);
SMC_RET1(ctx, ret);
@@ -1013,19 +1013,19 @@
SMC_RET0(ctx);
case SDEI_EVENT_STATUS:
- SDEI_LOG("> STAT(n:%d)\n", ev_num);
+ SDEI_LOG("> STAT(n:0x%x)\n", ev_num);
ret = sdei_event_status(ev_num);
SDEI_LOG("< STAT:%lld\n", ret);
SMC_RET1(ctx, ret);
case SDEI_EVENT_GET_INFO:
- SDEI_LOG("> INFO(n:%d, %d)\n", ev_num, (int) x2);
+ SDEI_LOG("> INFO(n:0x%x, %d)\n", ev_num, (int) x2);
ret = sdei_event_get_info(ev_num, (int) x2);
SDEI_LOG("< INFO:%lld\n", ret);
SMC_RET1(ctx, ret);
case SDEI_EVENT_UNREGISTER:
- SDEI_LOG("> UNREG(n:%d)\n", ev_num);
+ SDEI_LOG("> UNREG(n:0x%x)\n", ev_num);
ret = sdei_event_unregister(ev_num);
SDEI_LOG("< UNREG:%lld\n", ret);
SMC_RET1(ctx, ret);
@@ -1049,7 +1049,7 @@
SMC_RET1(ctx, ret);
case SDEI_INTERRUPT_RELEASE:
- SDEI_LOG("> REL(%d)\n", ev_num);
+ SDEI_LOG("> REL(0x%x)\n", ev_num);
ret = sdei_interrupt_release(ev_num);
SDEI_LOG("< REL:%lld\n", ret);
SMC_RET1(ctx, ret);
@@ -1067,7 +1067,7 @@
SMC_RET1(ctx, ret);
case SDEI_EVENT_ROUTING_SET:
- SDEI_LOG("> ROUTE_SET(n:%d f:%llx aff:%llx)\n", ev_num, x2, x3);
+ SDEI_LOG("> ROUTE_SET(n:0x%x f:%llx aff:%llx)\n", ev_num, x2, x3);
ret = sdei_event_routing_set(ev_num, x2, x3);
SDEI_LOG("< ROUTE_SET:%lld\n", ret);
SMC_RET1(ctx, ret);
@@ -1079,7 +1079,7 @@
SMC_RET1(ctx, ret);
case SDEI_EVENT_SIGNAL:
- SDEI_LOG("> SIGNAL(e:%d t:%llx)\n", ev_num, x2);
+ SDEI_LOG("> SIGNAL(e:0x%x t:%llx)\n", ev_num, x2);
ret = sdei_signal(ev_num, x2);
SDEI_LOG("< SIGNAL:%lld\n", ret);
SMC_RET1(ctx, ret);
