commit 3e881a8834a955f1e552300bdbf1dafd02ea8f1c
author Yann Gautier <yann.gautier@foss.st.com> Mon May 17 11:25:37 2021 +0200
committer Yann Gautier <yann.gautier@st.com> Thu Oct 28 11:36:54 2021 +0200
tree 41464431deefbfca14d53e4cabdb846b02162ede
parent 4357db5b17ce6ba7357dd99276f34ab497ce60ef

fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards

Set Ethernet source clock on PLL4P. This is required to enable PTP.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ia64fbb681d3f04f2b90f373c5eb044f5daa2836c

fdts/stm32mp157c-ed1.dts

diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index d471096..47b2b1a 100644
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -232,7 +232,7 @@
 		CLK_CKPER_HSE
 		CLK_FMC_ACLK
 		CLK_QSPI_ACLK
-		CLK_ETH_DISABLED
+		CLK_ETH_PLL4P
 		CLK_SDMMC12_PLL4P
 		CLK_DSI_DSIPLL
 		CLK_STGEN_HSE

fdts/stm32mp15xx-dkx.dtsi

diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi
index d6458a8..69b4828 100644
--- a/fdts/stm32mp15xx-dkx.dtsi
+++ b/fdts/stm32mp15xx-dkx.dtsi
@@ -222,7 +222,7 @@
 		CLK_CKPER_HSE
 		CLK_FMC_ACLK
 		CLK_QSPI_ACLK
-		CLK_ETH_DISABLED
+		CLK_ETH_PLL4P
 		CLK_SDMMC12_PLL4P
 		CLK_DSI_DSIPLL
 		CLK_STGEN_HSE