tree 535f69845871c33790f7aa032f609d24b59c74fc
parent 9cf75647235ad243acc7a585696ccb7b5ff54b36
author Chris Kay <chris.kay@arm.com> 1629368512 +0100
committer Chris Kay <chris.kay@arm.com> 1635246933 +0100

feat(amu): enable per-core AMU auxiliary counters

This change makes AMU auxiliary counters configurable on a per-core
basis, controlled by `ENABLE_AMU_AUXILIARY_COUNTERS`.

Auxiliary counters can be described via the `HW_CONFIG` device tree if
the `ENABLE_AMU_FCONF` build option is enabled, or the platform must
otherwise implement the `plat_amu_topology` function.

A new phandle property for `cpu` nodes (`amu`) has been introduced to
the `HW_CONFIG` specification to allow CPUs to describe the view of
their own AMU:

```
cpu0: cpu@0 {
    ...

    amu = <&cpu0_amu>;
};
```

Multiple cores may share an `amu` handle if they implement the
same set of auxiliary counters.

AMU counters are described for one or more AMUs through the use of a new
`amus` node:

```
amus {
    cpu0_amu: amu-0 {
        #address-cells = <1>;
        #size-cells = <0>;

        counter@0 {
            reg = <0>;

            enable-at-el3;
        };

        counter@n {
            reg = <n>;

            ...
        };
    };
};
```

This structure describes the **auxiliary** (group 1) AMU counters.
Architected counters have architecturally-defined behaviour, and as
such do not require DTB entries.

These `counter` nodes support two properties:

- The `reg` property represents the counter register index.
- The presence of the `enable-at-el3` property determines whether
  the firmware should enable the counter prior to exiting EL3.

Change-Id: Ie43aee010518c5725a3b338a4899b0857caf4c28
Signed-off-by: Chris Kay <chris.kay@arm.com>