Merge changes I2af839ae,Ifd0c7b4e,I56763cb4,I93aec580,Icbd43503, ... into integration
* changes:
docs(fvp): add GICv5 build instructions and limitations
feat(fvp): add GICv5 support
feat(gicv5): probe components
feat(gicv5): initialise the IWB
feat(gicv5): initialise the IRS
feat(gicv5): assign interrupt sources to appropriate security states
feat(gicv5): add a barebones GICv5 driver
feat(gicv5): add support for building with gicv5
diff --git a/.commitlintrc.js b/.commitlintrc.js
index 53e3a63..51493ea 100644
--- a/.commitlintrc.js
+++ b/.commitlintrc.js
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -67,6 +67,6 @@
"type-enum": [2, "always", types], /* Error */
"scope-case": [2, "always", "lower-case"], /* Error */
- "scope-enum": [1, "always", scopes] /* Warning */
+ "scope-enum": [2, "always", scopes] /* Error */
},
};
diff --git a/include/lib/psci/psci_lib.h b/include/lib/psci/psci_lib.h
index 8c9296b..1e1d5fc 100644
--- a/include/lib/psci/psci_lib.h
+++ b/include/lib/psci/psci_lib.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -98,6 +98,7 @@
void __dead2 psci_pwrdown_cpu_end_terminal(void);
void psci_pwrdown_cpu_end_wakeup(unsigned int power_level);
void psci_do_manage_extensions(void);
+unsigned int psci_num_cpus_running_on_safe(unsigned int this_core);
#endif /* __ASSEMBLER__ */
diff --git a/include/services/drtm_svc.h b/include/services/drtm_svc.h
index 56ae129..8e27b18 100644
--- a/include/services/drtm_svc.h
+++ b/include/services/drtm_svc.h
@@ -102,7 +102,7 @@
#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK ULL(0xFFFFFFFF)
#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT U(8)
-#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xF)
+#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xFFFF)
#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT U(0)
#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK ULL(0xFF)
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index d04e02f..7795fcf 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -191,6 +191,15 @@
scr_el3 |= SCR_SCTLR2En_BIT;
}
+ if (is_feat_d128_supported()) {
+ /*
+ * Set the D128En bit in SCR_EL3 to enable access to 128-bit
+ * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1,
+ * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers.
+ */
+ scr_el3 |= SCR_D128En_BIT;
+ }
+
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
if (is_feat_fgt2_supported()) {
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 1c634e3..1021ef6 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -215,7 +215,7 @@
******************************************************************************/
bool psci_is_last_on_cpu(unsigned int my_idx)
{
- for (unsigned int cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
+ for (unsigned int cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
if (cpu_idx == my_idx) {
assert(psci_get_aff_info_state() == AFF_STATE_ON);
continue;
@@ -239,7 +239,7 @@
{
unsigned int cpu_idx;
- for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
+ for (cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
if (psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_OFF) {
return false;
}
@@ -249,6 +249,33 @@
}
/*******************************************************************************
+ * Counts the number of CPUs in the system that are currently in the ON or
+ * ON_PENDING state.
+ *
+ * @note This function does not acquire any power domain locks. It must only be
+ * called in contexts where it is guaranteed that PSCI state transitions
+ * are not concurrently happening, or where locks are already held.
+ *
+ * @return The number of CPUs currently in AFF_STATE_ON or AFF_STATE_ON_PENDING.
+ ******************************************************************************/
+static unsigned int psci_num_cpus_running(void)
+{
+ unsigned int cpu_idx;
+ unsigned int no_of_cpus = 0U;
+ aff_info_state_t aff_state;
+
+ for (cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
+ aff_state = psci_get_aff_info_state_by_idx(cpu_idx);
+ if (aff_state == AFF_STATE_ON ||
+ aff_state == AFF_STATE_ON_PENDING) {
+ no_of_cpus++;
+ }
+ }
+
+ return no_of_cpus;
+}
+
+/*******************************************************************************
* Routine to return the maximum power level to traverse to after a cpu has
* been physically powered up. It is expected to be called immediately after
* reset from assembler code.
@@ -1371,3 +1398,30 @@
return true;
}
+
+/*******************************************************************************
+ * Safely counts the number of CPUs in the system that are currently in the ON
+ * or ON_PENDING state.
+ *
+ * This function acquires and releases the necessary power domain locks to
+ * ensure consistency of the CPU state information.
+ *
+ * @param this_core The index of the current core making the query.
+ *
+ * @return The number of CPUs currently in AFF_STATE_ON or AFF_STATE_ON_PENDING.
+ ******************************************************************************/
+unsigned int psci_num_cpus_running_on_safe(unsigned int this_core)
+{
+ unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
+ unsigned int no_of_cpus;
+
+ psci_get_parent_pwr_domain_nodes(this_core, PLAT_MAX_PWR_LVL, parent_nodes);
+
+ psci_acquire_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
+
+ no_of_cpus = psci_num_cpus_running();
+
+ psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
+
+ return no_of_cpus;
+}
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 95dff53..9c80283 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -783,8 +783,8 @@
/* Set number of consoles */
num_consoles = FVP_RMM_CONSOLE_COUNT;
- /* Set number of device non-coherent address ranges based on DT */
- num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+ /* Set number of device non-coherent address ranges for FVP RevC */
+ num_ncoh_regions = 2;
/* Set number of SMMUs */
num_smmus = FVP_RMM_SMMU_COUNT;
@@ -917,6 +917,11 @@
(void)memset((void *)ncoh_region_ptr, 0,
sizeof(struct memory_bank) * num_ncoh_regions);
+ /* Set number of device non-coherent address ranges based on DT */
+ num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+ /* At least 1 PCIe region need to be described in DT */
+ assert((num_ncoh_regions > 0) && (num_ncoh_regions <= 2));
+
for (unsigned long i = 0UL; i < num_ncoh_regions; i++) {
ncoh_region_ptr[i].base =
FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].base);
@@ -924,6 +929,17 @@
FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].size);
}
+ /*
+ * Workaround if the DT does not specify the 2nd PCIe region. This code can be
+ * removed when upstream DT is updated to have 2nd PCIe region.
+ */
+ if (num_ncoh_regions == 1) {
+ num_ncoh_regions++;
+ /* Add 3GB of 2nd PCIe region */
+ ncoh_region_ptr[1].base = 0x4000000000;
+ ncoh_region_ptr[1].size = 0xc0000000;
+ }
+
/* Update checksum */
checksum += checksum_calc((uint64_t *)ncoh_region_ptr,
sizeof(struct memory_bank) * num_ncoh_regions);
diff --git a/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c b/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c
new file mode 100644
index 0000000..6c0eb9c
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <drivers/pmic/pmic_psc.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#include "registers.h"
+
+static const struct pmic_psc_reg mt6359p_psc_regs[] = {
+ PMIC_PSC_REG(RG_PWRHOLD, MT6359P_PPCCTL0, 0),
+ PMIC_PSC_REG(RG_CRST, MT6359P_PPCCTL1, 0),
+ PMIC_PSC_REG(RG_SMART_RST_SDN_EN, MT6359P_STRUP_CON12, 9),
+ PMIC_PSC_REG(RG_SMART_RST_MODE, MT6359P_STRUP_CON12, 10),
+};
+
+static const struct pmic_psc_config mt6359p_psc_config = {
+ .read_field = pwrap_read_field,
+ .write_field = pwrap_write_field,
+ .regs = mt6359p_psc_regs,
+ .reg_size = ARRAY_SIZE(mt6359p_psc_regs),
+};
+
+static int mt6359p_psc_init(void)
+{
+ return pmic_psc_register(&mt6359p_psc_config);
+}
+
+MTK_PLAT_SETUP_0_INIT(mt6359p_psc_init);
diff --git a/plat/mediatek/drivers/pmic/mt6359p/registers.h b/plat/mediatek/drivers/pmic/mt6359p/registers.h
new file mode 100644
index 0000000..f1b2a6d
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/registers.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef REGISTER_H
+#define REGISTER_H
+
+/* PMIC Registers for PSC */
+#define MT6359P_PPCCTL0 0xa08
+#define MT6359P_PPCCTL1 0xa0a
+#define MT6359P_STRUP_CON12 0xa12
+
+#endif /* REGISTER_H */
diff --git a/plat/mediatek/drivers/pmic/mt6359p/rules.mk b/plat/mediatek/drivers/pmic/mt6359p/rules.mk
new file mode 100644
index 0000000..39908f8
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/rules.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := mt6359p
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/${PMIC_CHIP}_psc.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c b/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c
new file mode 100644
index 0000000..aa90b86
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+
+#include <drivers/pmic/mt6319_lowpower_reg.h>
+#include <drivers/pmic/mt6359p_set_lowpower.h>
+#include <drivers/pmic/pmic_swap_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#define PMIC_SLVID_BUCK_SET_LP(_chip, _slvid, _name, _user, _en, _mode, _cfg) \
+{ \
+ struct spmi_device *sdev = lowpower_sdev[_slvid]; \
+ if (sdev) {\
+ pmic_spmi_update_bits(sdev, \
+ _chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
+ 1 << _user, \
+ _cfg ? 1 << _user : 0); \
+ pmic_spmi_update_bits(sdev, \
+ _chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
+ 1 << _user, \
+ _mode ? 1 << _user : 0); \
+ pmic_spmi_update_bits(sdev, \
+ _chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
+ 1 << _user, \
+ _en ? 1 << _user : 0); \
+ } \
+}
+
+struct spmi_device *lowpower_sdev[SPMI_MAX_SLAVE_ID];
+
+static const uint8_t lowpower_slvid_arr[] = {
+ SPMI_SLAVE_7,
+};
+
+static int pmic_spmi_update_bits(struct spmi_device *sdev, uint16_t reg,
+ uint8_t mask, uint8_t val)
+{
+ uint8_t orig = 0;
+ int ret = 0;
+
+ ret = spmi_ext_register_readl(sdev, reg, &orig, 1);
+ if (ret < 0)
+ return ret;
+ orig &= ~mask;
+ orig |= val & mask;
+ ret = spmi_ext_register_writel(sdev, reg, &orig, 1);
+ return ret;
+}
+
+static int pmic_lowpower_init(void)
+{
+ uint8_t i, slvid;
+
+ for (i = 0; i < ARRAY_SIZE(lowpower_slvid_arr); i++) {
+ slvid = lowpower_slvid_arr[i];
+ lowpower_sdev[slvid] = get_spmi_device(SPMI_MASTER_P_1, slvid);
+ if (!lowpower_sdev[slvid])
+ return -ENODEV;
+ }
+
+ PMIC_SLVID_BUCK_SET_LP(MT6319, SPMI_SLAVE_7, VBUCK3, HW0, true, OP_MODE_LP, HW_LP);
+
+ PMIC_BUCK_SET_LP(MT6359P, VPROC2, HW0, true, OP_MODE_LP, HW_OFF);
+ PMIC_BUCK_SET_LP(MT6359P, VPROC2, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VGPU11, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VGPU11, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VS1, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VS1, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VS2, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_BUCK_SET_LP(MT6359P, VS2, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VRF12, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VRF12, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VA12, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VA12, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VA09, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VA09, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VAUX18, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VAUX18, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VXO22, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VXO22, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VUSB, HW0, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VUSB, HW2, true, OP_MODE_LP, HW_LP);
+ PMIC_LDO_SET_LP(MT6359P, VUFS, HW0, true, OP_MODE_LP, HW_LP);
+
+ return 0;
+}
+
+MTK_PLAT_SETUP_0_INIT(pmic_lowpower_init);
diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c b/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c
new file mode 100644
index 0000000..dbb5852
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "../mt6359p/registers.h"
+#include <drivers/pmic/pmic_shutdown_cfg.h>
+#include <drivers/spmi/spmi_common.h>
+#include <drivers/spmi_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#define MT6319_RG_SEQ_OFF 0x2d
+#define MT6319_TOP_RST_MISC_CLR 0x128
+#define MT6319_TOP_DIG_WPK_H 0x3a9
+#define MT6319_TOP_DIG_WPK_H_MASK 0xFF
+#define MT6319_TOP_DIG_WPK_H_SHIFT 0
+#define MT6319_TOP_DIG_WPK 0x3a8
+#define MT6319_TOP_DIG_WPK_MASK 0xFF
+#define MT6319_TOP_DIG_WPK_SHIFT 0
+
+
+int pmic_shutdown_cfg(void)
+{
+/*
+ * In mt8189, the pmic_shutdown_cfg() api does not need to read and write the
+ * pmic register to determine the return value and in order not to modify the
+ * common code to affect other ICs, the pmic_shutdown_cfg() will directly
+ * return 1.
+ */
+ return 1;
+}
+
+static void shutdown_slave_dev(struct spmi_device *dev)
+{
+ spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK_H, 0x63,
+ MT6319_TOP_DIG_WPK_H_MASK,
+ MT6319_TOP_DIG_WPK_H_SHIFT);
+ spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK, 0x15,
+ MT6319_TOP_DIG_WPK_MASK,
+ MT6319_TOP_DIG_WPK_SHIFT);
+
+ /* Disable WDTRSTB_EN */
+ spmi_ext_register_writel_field(dev, MT6319_TOP_RST_MISC_CLR, 1, 0x1, 0);
+ /* Normal sequence power off when PAD_EN falling */
+ spmi_ext_register_writel_field(dev, MT6319_RG_SEQ_OFF, 1, 0x1, 0);
+
+ spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK_H, 0,
+ MT6319_TOP_DIG_WPK_H_MASK,
+ MT6319_TOP_DIG_WPK_H_SHIFT);
+ spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK, 0,
+ MT6319_TOP_DIG_WPK_MASK,
+ MT6319_TOP_DIG_WPK_SHIFT);
+
+}
+
+int spmi_shutdown(void)
+{
+ struct spmi_device *mt6319_sdev;
+
+ mt6319_sdev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_7);
+ if (!mt6319_sdev)
+ return -ENODEV;
+ shutdown_slave_dev(mt6319_sdev);
+
+ if (mmio_read_32((uintptr_t)CHIP_ID_REG) == MTK_CPU_ID_MT8189 &&
+ mmio_read_32((uintptr_t)CPU_SEG_ID_REG) == MTK_CPU_SEG_ID_MT8189H) {
+ mt6319_sdev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_8);
+ if (!mt6319_sdev)
+ return -ENODEV;
+ shutdown_slave_dev(mt6319_sdev);
+ }
+
+ /* clear main pmic power hold */
+ pwrap_write_field(MT6359P_PPCCTL0, 0, 0x1, 0);
+
+ return 0;
+}
diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c b/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c
new file mode 100644
index 0000000..0310389
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+
+#include <drivers/pmic/pmic_swap_api.h>
+
+/* No need to check second pmic mt6369 */
+bool is_second_pmic_pp_swap(void)
+{
+ return false;
+}
diff --git a/plat/mediatek/drivers/pmic/rules.mk b/plat/mediatek/drivers/pmic/rules.mk
index 0280df8..dc228ee 100644
--- a/plat/mediatek/drivers/pmic/rules.mk
+++ b/plat/mediatek/drivers/pmic/rules.mk
@@ -8,15 +8,15 @@
MODULE := pmic
-ifneq (${PMIC_CHIP}, mt6363)
-LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c
-PLAT_INCLUDES += -I${LOCAL_DIR}/
-else
-LOCAL_SRCS-y := ${LOCAL_DIR}/pmic_psc.c
+ifeq (${CONFIG_MTK_PMIC_SHUTDOWN_V2}, y)
LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_common_swap_api.c
+LOCAL_SRCS-y := ${LOCAL_DIR}/pmic_psc.c
LOCAL_SRCS-${CONFIG_MTK_PMIC_LOWPOWER} += ${LOCAL_DIR}/${MTK_SOC}/pmic_lowpower_init.c
LOCAL_SRCS-${CONFIG_MTK_PMIC_LOWPOWER} += ${LOCAL_DIR}/${MTK_SOC}/pmic_swap_api.c
LOCAL_SRCS-${CONFIG_MTK_PMIC_SHUTDOWN_CFG} += ${LOCAL_DIR}/${MTK_SOC}/pmic_shutdown_cfg.c
+else
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c
+PLAT_INCLUDES += -I${LOCAL_DIR}/
endif
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h b/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h
new file mode 100644
index 0000000..9647326
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_H
+#define PMIC_WRAP_INIT_H
+
+#include <platform_def.h>
+#include <pmic_wrap_init_common.h>
+
+#define PWRAP_DEBUG 0
+
+/* PMIC_WRAP registers */
+struct mt8189_pmic_wrap_regs {
+ uint32_t init_done;
+ uint32_t reserved[511];
+ struct {
+ uint32_t cmd;
+ uint32_t wdata;
+ uint32_t reserved1[3];
+ uint32_t rdata;
+ uint32_t reserved2[3];
+ uint32_t vldclr;
+ uint32_t sta;
+ uint32_t reserved3[5];
+ } wacs[4];
+};
+
+static struct mt8189_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
+
+#define PMIF_SPI_SWINF_NO 2
+
+#endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
index 4ba1f5c..3a30435 100644
--- a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
@@ -12,10 +12,14 @@
#include "platform_def.h"
/* external API */
+int32_t pmic_wrap_test(void);
int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
+int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift);
int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift);
-#define GET_WACS_FSM(x) ((x >> 1) & 0x7)
+#define GET_SWINF_INIT_DONE(x) ((x>>15) & 0x00000001)
+#define GET_WACS_FSM(x) ((x >> 1) & 0x7)
/* macro for SWINF_FSM */
#define SWINF_FSM_IDLE (0x00)
@@ -43,6 +47,11 @@
E_PWR_INIT_SIDLY_FAIL = 11,
E_PWR_RESET_TIMEOUT = 12,
E_PWR_TIMEOUT = 13,
+ E_PWR_INVALID_SWINF = 14,
+ E_PWR_INVALID_CMD = 15,
+ E_PWR_INVALID_PMIFID = 16,
+ E_PWR_INVALID_SLVID = 17,
+ E_PWR_INVALID_BYTECNT = 18,
E_PWR_INIT_RESET_SPI = 20,
E_PWR_INIT_SIDLY = 21,
E_PWR_INIT_REG_CLOCK = 22,
diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c
new file mode 100644
index 0000000..4e9c321
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/spinlock.h>
+
+#include <mtk_mmap_pool.h>
+#include "pmic_wrap_init.h"
+#include "pmic_wrap_v3.h"
+
+static spinlock_t wrp_lock;
+
+static uint32_t pwrap_check_idle(uintptr_t wacs_register, uintptr_t wacs_vldclr_register,
+ uint32_t timeout_us)
+{
+ uint32_t reg_rdata = 0U, retry;
+
+ retry = (timeout_us + PWRAP_POLL_STEP_US) / PWRAP_POLL_STEP_US;
+ while (retry != 0) {
+ udelay(PWRAP_POLL_STEP_US);
+ reg_rdata = mmio_read_32(wacs_register);
+ /* if last read command timeout,clear vldclr bit
+ * read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
+ * write:FSM_REQ-->idle
+ */
+ switch (GET_WACS_FSM(reg_rdata)) {
+ case SWINF_FSM_WFVLDCLR:
+ mmio_write_32(wacs_vldclr_register, 0x1);
+ INFO("WACS_FSM = SWINF_FSM_WFVLDCLR\n");
+ break;
+ case SWINF_FSM_WFDLE:
+ INFO("WACS_FSM = SWINF_FSM_WFDLE\n");
+ break;
+ case SWINF_FSM_REQ:
+ INFO("WACS_FSM = SWINF_FSM_REQ\n");
+ break;
+ case SWINF_FSM_IDLE:
+ goto done;
+ default:
+ break;
+ }
+ retry--;
+ }
+
+done:
+ if (retry == 0) {
+ /* timeout */
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+
+ return 0U;
+}
+
+static uint32_t pwrap_check_vldclr(uintptr_t wacs_register, uint32_t timeout_us)
+{
+ uint32_t reg_rdata = 0U, retry;
+
+ retry = (timeout_us + PWRAP_POLL_STEP_US) / PWRAP_POLL_STEP_US;
+ while (retry != 0) {
+ udelay(PWRAP_POLL_STEP_US);
+ reg_rdata = mmio_read_32(wacs_register);
+ if (GET_WACS_FSM(reg_rdata) == SWINF_FSM_WFVLDCLR) {
+ break;
+ }
+ retry--;
+ }
+
+ if (retry == 0) {
+ /* timeout */
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+
+ return 0U;
+}
+
+static int32_t pwrap_swinf_acc(uint32_t swinf_no, uint32_t cmd, uint32_t write,
+ uint32_t pmifid, uint32_t slvid, uint32_t addr,
+ uint32_t bytecnt, uint32_t wdata, uint32_t *rdata)
+{
+ uint32_t reg_rdata = 0x0;
+ int32_t ret = 0x0;
+
+ /* Check argument validation */
+ if ((swinf_no & ~(0x3)) != 0)
+ return -E_PWR_INVALID_SWINF;
+ if ((cmd & ~(0x3)) != 0)
+ return -E_PWR_INVALID_CMD;
+ if ((write & ~(0x1)) != 0)
+ return -E_PWR_INVALID_RW;
+ if ((pmifid & ~(0x1)) != 0)
+ return -E_PWR_INVALID_PMIFID;
+ if ((slvid & ~(0xf)) != 0)
+ return -E_PWR_INVALID_SLVID;
+ if ((addr & ~(0xffff)) != 0)
+ return -E_PWR_INVALID_ADDR;
+ if ((bytecnt & ~(0x1)) != 0)
+ return -E_PWR_INVALID_BYTECNT;
+ if ((wdata & ~(0xffff)) != 0)
+ return -E_PWR_INVALID_WDAT;
+
+ spin_lock(&wrp_lock);
+ /* Check whether INIT_DONE is set */
+ if (pmifid == 0)
+ reg_rdata = mmio_read_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta));
+
+ if (GET_SWINF_INIT_DONE(reg_rdata) != 0x1) {
+ ERROR("[PWRAP] init not finish\n");
+ ret = -E_PWR_NOT_INIT_DONE;
+ goto end;
+ }
+
+ /* Wait for Software Interface FSM state to be IDLE */
+ ret = pwrap_check_idle((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta),
+ (uintptr_t)(&mtk_pwrap->wacs[swinf_no].vldclr), TIMEOUT_WAIT_IDLE);
+ if (ret != 0) {
+ ERROR("[PWRAP] fsm_idle fail\n");
+ goto end;
+ }
+
+ /* Set the write data */
+ if (write == 1) {
+ if (pmifid == 0)
+ mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].wdata), wdata);
+ }
+
+ /* Send the command */
+ if (pmifid == 0)
+ mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].cmd),
+ (cmd << 30) | (write << 29) | (slvid << 24) | (bytecnt << 16) | addr);
+
+ if (write == 0) {
+ if (rdata == NULL) {
+ ERROR("[PWRAP] rdata null\n");
+ ret = -E_PWR_INVALID_ARG;
+ goto end;
+ }
+
+ /* Wait for Software Interface FSM to be WFVLDCLR */
+ /* read the data and clear the valid flag */
+ ret = pwrap_check_vldclr((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta), TIMEOUT_READ);
+ if (ret != 0) {
+ ERROR("[PWRAP] fsm_vldclr fail\n");
+ goto end;
+ }
+
+ if (pmifid == 0) {
+ *rdata = mmio_read_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].rdata));
+ mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].vldclr), 0x1);
+ }
+ }
+
+end:
+ spin_unlock(&wrp_lock);
+ if (ret < 0)
+ ERROR("%s fail, ret=%d\n", __func__, ret);
+ return ret;
+}
+
+/* external API for pmic_wrap user */
+
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata)
+{
+ return pwrap_swinf_acc(PMIF_SPI_SWINF_NO, DEFAULT_CMD, 0, PMIF_SPI_PMIFID,
+ DEFAULT_SLVID, adr, DEFAULT_BYTECNT, 0x0, rdata);
+}
+
+int32_t pwrap_write(uint32_t adr, uint32_t wdata)
+{
+ return pwrap_swinf_acc(PMIF_SPI_SWINF_NO, DEFAULT_CMD, 1, PMIF_SPI_PMIFID,
+ DEFAULT_SLVID, adr, DEFAULT_BYTECNT, wdata, 0x0);
+}
+
+int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift)
+{
+ uint32_t rdata;
+ int32_t ret;
+
+ if (!val)
+ return -E_PWR_INVALID_ARG;
+ ret = pwrap_read(reg, &rdata);
+ if (ret == 0x0)
+ *val = (rdata >> shift) & mask;
+
+ return ret;
+}
+
+int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift)
+{
+ uint32_t data;
+ int32_t ret;
+
+ ret = pwrap_read(reg, &data);
+ if (ret != 0)
+ return ret;
+
+ data = data & ~(mask << shift);
+ data |= (val << shift);
+ ret = pwrap_write(reg, data);
+
+ return ret;
+}
+
+#if PWRAP_DEBUG
+static int32_t pwrap_read_test(void)
+{
+ uint32_t rdata = 0;
+ int32_t ret;
+
+ ret = pwrap_read(DEW_READ_TEST, &rdata);
+ if (rdata != DEFAULT_VALUE_READ_TEST) {
+ ERROR("[PWRAP] Read fail,rdata=0x%x,exp=0x5aa5,ret=0x%x\n", rdata, ret);
+ return -E_PWR_READ_TEST_FAIL;
+ }
+ INFO("[PWRAP] Read Test pass,ret=%x\n", ret);
+ return 0;
+}
+
+static int32_t pwrap_write_test(void)
+{
+ uint32_t rdata = 0;
+ int32_t ret;
+ int32_t ret1;
+
+ ret = pwrap_write(DEW_WRITE_TEST, PWRAP_WRITE_TEST_VALUE);
+ ret1 = pwrap_read(DEW_WRITE_TEST, &rdata);
+ if ((rdata != PWRAP_WRITE_TEST_VALUE) || (ret != 0) || (ret1 != 0)) {
+ ERROR("[PWRAP] Write fail,rdata=0x%x,exp=0xa55a,ret=0x%x,ret1=0x%x\n",
+ rdata, ret, ret1);
+ return -E_PWR_WRITE_TEST_FAIL;
+ }
+ INFO("[PWRAP] Write Test pass\n");
+ return 0;
+}
+
+int32_t pmic_wrap_test(void)
+{
+ int32_t ret;
+
+ INFO("[PWRAP] Read/Write Test start\n");
+
+ ret = pwrap_read_test();
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = pwrap_write_test();
+ if (ret != 0) {
+ return ret;
+ }
+ INFO("[PWRAP] Read/Write Test done\n");
+
+ return 0;
+}
+#endif
diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h
new file mode 100644
index 0000000..075c2d5
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_V3_H
+#define PMIC_WRAP_V3_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <drivers/console.h>
+
+#define PMIF_REG_RANGE (0x774)
+#define PMICSPI_MST_REG_RANGE (0x80)
+#define DEFAULT_CMD 0
+#define DEFAULT_SLVID 0
+#define DEFAULT_BYTECNT 0
+#define PMIF_SPI_PMIFID 0
+/* #define PWRAP_DEBUG 1 */
+
+#if PWRAP_DEBUG
+#define PWRAP_LOG(fmts, args...) do {\
+ console_init(gteearg.atf_log_port, UART_CLOCK, UART_BAUDRATE);\
+ INFO("[%s:%d] -" fmts, __func__, __LINE__, ##args);\
+ console_uninit();\
+ } while (0)
+#endif
+
+/**********************************************************/
+#define DEFAULT_VALUE_READ_TEST (0x5aa5)
+#define PWRAP_WRITE_TEST_VALUE (0xa55a)
+#define PWRAP_POLL_STEP_US (10)
+
+/* timeout setting */
+enum {
+ TIMEOUT_RESET = 50, /* us */
+ TIMEOUT_READ = 50, /* us */
+ TIMEOUT_WAIT_IDLE = 50 /* us */
+};
+
+#endif /* PMIC_WRAP_V3_H */
diff --git a/plat/mediatek/drivers/pmic_wrap/rules.mk b/plat/mediatek/drivers/pmic_wrap/rules.mk
index 9ba44a6..662c7e4 100644
--- a/plat/mediatek/drivers/pmic_wrap/rules.mk
+++ b/plat/mediatek/drivers/pmic_wrap/rules.mk
@@ -10,6 +10,8 @@
ifeq (${USE_PMIC_WRAP_INIT_V2}, 1)
LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init_v2.c
+else ifeq (${USE_PMIC_WRAP_INIT_V3}, 1)
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init_v3.c
else
LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init.c
endif
diff --git a/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c b/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c
new file mode 100644
index 0000000..417f779
--- /dev/null
+++ b/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include <drivers/spmi/pmif_common.h>
+#include <drivers/spmi/pmif_v1/pmif.h>
+#include <drivers/spmi/spmi_common.h>
+#include <drivers/spmi/spmi_sw.h>
+#include <drivers/spmi_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <mtk_mmap_pool.h>
+
+#define SPMI_GROUP_ID 0xB
+#define SPMI_DEBUG 0
+
+static uint16_t mt6xxx_regs[] = {
+ [PMIF_INIT_DONE] = 0x0000,
+ [PMIF_INF_EN] = 0x0024,
+ [PMIF_ARB_EN] = 0x0150,
+ [PMIF_IRQ_EVENT_EN_0] = 0x0420,
+ [PMIF_IRQ_FLAG_0] = 0x0428,
+ [PMIF_IRQ_CLR_0] = 0x042C,
+ [PMIF_IRQ_EVENT_EN_2] = 0x0440,
+ [PMIF_IRQ_FLAG_2] = 0x0448,
+ [PMIF_IRQ_CLR_2] = 0x044C,
+ [PMIF_WDT_CTRL] = 0x0470,
+ [PMIF_WDT_EVENT_EN_1] = 0x047C,
+ [PMIF_WDT_FLAG_1] = 0x0480,
+ [PMIF_SWINF_2_ACC] = 0x0880,
+ [PMIF_SWINF_2_WDATA_31_0] = 0x0884,
+ [PMIF_SWINF_2_WDATA_63_32] = 0x0888,
+ [PMIF_SWINF_2_RDATA_31_0] = 0x0894,
+ [PMIF_SWINF_2_RDATA_63_32] = 0x0898,
+ [PMIF_SWINF_2_VLD_CLR] = 0x08A4,
+ [PMIF_SWINF_2_STA] = 0x08A8,
+ [PMIF_SWINF_3_ACC] = 0x08C0,
+ [PMIF_SWINF_3_WDATA_31_0] = 0x08C4,
+ [PMIF_SWINF_3_WDATA_63_32] = 0x08C8,
+ [PMIF_SWINF_3_RDATA_31_0] = 0x08D4,
+ [PMIF_SWINF_3_RDATA_63_32] = 0x08D8,
+ [PMIF_SWINF_3_VLD_CLR] = 0x08E4,
+ [PMIF_SWINF_3_STA] = 0x08E8,
+ /* hw mpu */
+ [PMIF_PMIC_ALL_RGN_EN_1] = 0x09B0,
+ [PMIF_PMIC_ALL_RGN_EN_2] = 0x0D30,
+ [PMIF_PMIC_ALL_RGN_0_START] = 0x09B4,
+ [PMIF_PMIC_ALL_RGN_0_END] = 0x09B8,
+ [PMIF_PMIC_ALL_RGN_1_START] = 0x09BC,
+ [PMIF_PMIC_ALL_RGN_1_END] = 0x09C0,
+ [PMIF_PMIC_ALL_RGN_2_START] = 0x09C4,
+ [PMIF_PMIC_ALL_RGN_2_END] = 0x09C8,
+ [PMIF_PMIC_ALL_RGN_3_START] = 0x09CC,
+ [PMIF_PMIC_ALL_RGN_3_END] = 0x09D0,
+ [PMIF_PMIC_ALL_RGN_31_START] = 0x0D34,
+ [PMIF_PMIC_ALL_RGN_31_END] = 0x0D38,
+ [PMIF_PMIC_ALL_INVLD_SLVID] = 0x0AAC,
+ [PMIF_PMIC_ALL_RGN_0_PER0] = 0x0AB0,
+ [PMIF_PMIC_ALL_RGN_0_PER1] = 0x0AB4,
+ [PMIF_PMIC_ALL_RGN_1_PER0] = 0x0AB8,
+ [PMIF_PMIC_ALL_RGN_2_PER0] = 0x0AC0,
+ [PMIF_PMIC_ALL_RGN_3_PER0] = 0x0AC8,
+ [PMIF_PMIC_ALL_RGN_31_PER0] = 0x0E34,
+ [PMIF_PMIC_ALL_RGN_31_PER1] = 0x0E38,
+ [PMIF_PMIC_ALL_RGN_OTHERS_PER0] = 0x0BA8,
+ [PMIF_PMIC_ALL_RGN_OTHERS_PER1] = 0x0BAC,
+};
+
+static uint16_t mt6xxx_spmi_regs[] = {
+ [SPMI_OP_ST_CTRL] = 0x0000,
+ [SPMI_GRP_ID_EN] = 0x0004,
+ [SPMI_OP_ST_STA] = 0x0008,
+ [SPMI_MST_SAMPL] = 0x000c,
+ [SPMI_MST_REQ_EN] = 0x0010,
+ [SPMI_RCS_CTRL] = 0x0014,
+ [SPMI_SLV_3_0_EINT] = 0x0020,
+ [SPMI_SLV_7_4_EINT] = 0x0024,
+ [SPMI_SLV_B_8_EINT] = 0x0028,
+ [SPMI_SLV_F_C_EINT] = 0x002c,
+ [SPMI_REC_CTRL] = 0x0040,
+ [SPMI_REC0] = 0x0044,
+ [SPMI_REC1] = 0x0048,
+ [SPMI_REC2] = 0x004c,
+ [SPMI_REC3] = 0x0050,
+ [SPMI_REC4] = 0x0054,
+ [SPMI_REC_CMD_DEC] = 0x005c,
+ [SPMI_DEC_DBG] = 0x00f8,
+ [SPMI_MST_DBG] = 0x00fc,
+};
+
+struct pmif pmif_spmi_arb[] = {
+ {
+ .regs = mt6xxx_regs,
+ .spmimst_regs = mt6xxx_spmi_regs,
+ .mstid = SPMI_MASTER_0,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ },
+ {
+ .regs = mt6xxx_regs,
+ .spmimst_regs = mt6xxx_spmi_regs,
+ .mstid = SPMI_MASTER_1,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ },
+ {
+ .base = (unsigned int *)PMIF_SPMI_P_BASE,
+ .regs = mt6xxx_regs,
+ .spmimst_base = (unsigned int *)SPMI_MST_P_BASE,
+ .spmimst_regs = mt6xxx_spmi_regs,
+ .mstid = SPMI_MASTER_P_1,
+ .read_cmd = pmif_spmi_read_cmd,
+ .write_cmd = pmif_spmi_write_cmd,
+ },
+};
+
+static struct spmi_device spmi_dev[] = {
+ {
+ .slvid = SPMI_SLAVE_7, /* MT6319 */
+ .grpiden = 0x800,
+ .type = BUCK_CPU,
+ .type_id = BUCK_CPU_ID,
+ .mstid = SPMI_MASTER_P_1,/* spmi-p */
+ .hwcid_addr = 0x09,
+ .hwcid_val = 0x15,
+ .swcid_addr = 0x0B,
+ .swcid_val = 0x15,
+ .wpk_key_addr = 0x3A8,
+ .wpk_key_val = 0x6315,
+ .tma_key_addr = 0x39F,
+ .tma_key_val = 0x9CEA,
+ .pmif_arb = &pmif_spmi_arb[SPMI_MASTER_P_1],
+ },
+ {
+ .slvid = SPMI_SLAVE_8, /* MT6319 */
+ .grpiden = 0x800,
+ .type = BUCK_CPU,
+ .type_id = BUCK_CPU_ID,
+ .mstid = SPMI_MASTER_P_1,/* spmi-p */
+ .hwcid_addr = 0x09,
+ .hwcid_val = 0x15,
+ .swcid_addr = 0x0B,
+ .swcid_val = 0x15,
+ .wpk_key_addr = 0x3A8,
+ .wpk_key_val = 0x6315,
+ .tma_key_addr = 0x39F,
+ .tma_key_val = 0x9CEA,
+ .pmif_arb = &pmif_spmi_arb[SPMI_MASTER_P_1],
+ },
+};
+
+int platform_pmif_spmi_init(void)
+{
+/*
+ * The MT8189 chipset comes in two variants: MT8189G and MT8189H. The
+ * MT8189G variant uses a single PMIC IC (MT6319), whereas the MT8189H
+ * variant uses two PMIC ICs. To ensure driver compatibility, we utilize
+ * the CPU ID and segment ID to accurately determine the required number
+ * of SPMIF instances.
+ */
+ if (mmio_read_32((uintptr_t)CHIP_ID_REG) == MTK_CPU_ID_MT8189 &&
+ mmio_read_32((uintptr_t)CPU_SEG_ID_REG) == MTK_CPU_SEG_ID_MT8189G)
+ spmi_device_register(spmi_dev, 1);
+ else
+ spmi_device_register(spmi_dev, ARRAY_SIZE(spmi_dev));
+
+ return 0;
+}
+MTK_ARCH_INIT(platform_pmif_spmi_init);
diff --git a/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h
new file mode 100644
index 0000000..71a2d2b
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6319_LOWPOWER_REG_H
+#define MT6319_LOWPOWER_REG_H
+
+#define MT6319_RG_LDO_VDIG18_SW_OP_EN_ADDR 0x0196
+#define MT6319_RG_LDO_VDIG18_HW_OP_EN_ADDR 0x0196
+#define MT6319_RG_VDIG18_PWROFF_OP_EN_ADDR 0x0197
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_EN_ADDR 0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_EN_ADDR 0x1708
+#define MT6319_RG_BUCK_VBUCK1_SW_OP_EN_ADDR 0x1490
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_CFG_ADDR 0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_CFG_ADDR 0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_MODE_ADDR 0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_MODE_ADDR 0x170e
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_EN_ADDR 0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_EN_ADDR 0x1711
+#define MT6319_RG_BUCK_VBUCK2_SW_OP_EN_ADDR 0x1510
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_CFG_ADDR 0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_CFG_ADDR 0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_MODE_ADDR 0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_MODE_ADD 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_MODE_ADDR 0x1717
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_EN_ADDR 0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_EN_ADDR 0x171a
+#define MT6319_RG_BUCK_VBUCK3_SW_OP_EN_ADDR 0x1590
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_CFG_ADDR 0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_CFG_ADDR 0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_MODE_ADDR 0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_MODE_ADDR 0x1720
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_EN_ADDR 0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_EN_ADDR 0x1723
+#define MT6319_RG_BUCK_VBUCK4_SW_OP_EN_ADDR 0x1610
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_CFG_ADDR 0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_CFG_ADDR 0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_MODE_ADDR 0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_MODE_ADDR 0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_MODE_ADDR 0x1729
+
+#endif /* MT6319_LOWPOWER_REG_H */
diff --git a/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h
new file mode 100644
index 0000000..7e14f00
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h
@@ -0,0 +1,1593 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6359P_LOWPOWER_REG_H
+#define MT6359P_LOWPOWER_REG_H
+
+#define MT6359P_RG_BUCK_VPU_VOSEL_SLEEP_ADDR 0x148e
+#define MT6359P_RG_BUCK_VPU_HW0_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW1_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW2_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW3_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW4_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW5_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW6_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW7_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW8_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW9_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW10_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW11_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW12_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW13_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW14_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_SW_OP_EN_ADDR 0x1494
+#define MT6359P_RG_BUCK_VPU_HW0_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW1_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW2_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW3_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW4_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW5_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW6_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW7_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW8_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW9_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW10_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW11_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW12_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW13_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW14_OP_CFG_ADDR 0x149a
+#define MT6359P_RG_BUCK_VPU_HW0_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VPU_HW1_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VPU_HW2_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VPU_HW3_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VPU_HW4_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VPU_HW5_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VPU_HW6_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VPU_HW7_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VPU_HW8_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VPU_HW9_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VPU_HW10_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VPU_HW11_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VPU_HW12_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VPU_HW13_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VPU_HW14_OP_MODE_ADDR 0x14a0
+#define MT6359P_RG_BUCK_VPU_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VCORE_VOSEL_SLEEP_ADDR 0x150e
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_SW_OP_EN_ADDR 0x1514
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_CFG_ADDR 0x151a
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_MODE_ADDR 0x1520
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VGPU11_VOSEL_SLEEP_ADDR 0x158e
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_SW_OP_EN_ADDR 0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_CFG_ADDR 0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_MODE_ADDR 0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VGPU12_VOSEL_SLEEP_ADDR 0x160e
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_SW_OP_EN_ADDR 0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_CFG_ADDR 0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_MODE_ADDR 0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VMODEM_VOSEL_SLEEP_ADDR 0x168e
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_SW_OP_EN_ADDR 0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_CFG_ADDR 0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_MODE_ADDR 0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VPROC1_VOSEL_SLEEP_ADDR 0x170e
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_SW_OP_EN_ADDR 0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_CFG_ADDR 0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_MODE_ADDR 0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VPROC2_VOSEL_SLEEP_ADDR 0x178e
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_SW_OP_EN_ADDR 0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_CFG_ADDR 0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_MODE_ADDR 0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VS1_VOSEL_SLEEP_ADDR 0x180e
+#define MT6359P_RG_BUCK_VS1_HW0_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW1_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW2_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW3_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW4_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW5_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW6_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW7_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW8_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW9_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW10_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW11_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW12_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW13_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW14_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_SW_OP_EN_ADDR 0x1814
+#define MT6359P_RG_BUCK_VS1_HW0_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW1_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW2_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW3_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW4_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW5_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW6_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW7_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW8_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW9_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW10_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW11_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW12_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW13_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW14_OP_CFG_ADDR 0x181a
+#define MT6359P_RG_BUCK_VS1_HW0_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VS1_HW1_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VS1_HW2_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VS1_HW3_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VS1_HW4_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VS1_HW5_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VS1_HW6_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VS1_HW7_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VS1_HW8_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VS1_HW9_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VS1_HW10_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VS1_HW11_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VS1_HW12_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VS1_HW13_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VS1_HW14_OP_MODE_ADDR 0x1820
+#define MT6359P_RG_BUCK_VS1_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_BUCK_VS2_VOSEL_SLEEP_ADDR 0x188e
+#define MT6359P_RG_BUCK_VS2_HW0_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW1_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW2_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW3_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW4_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW5_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW6_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW7_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW8_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW9_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW10_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW11_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW12_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW13_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW14_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_SW_OP_EN_ADDR 0x1894
+#define MT6359P_RG_BUCK_VS2_HW0_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW1_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW2_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW3_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW4_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW5_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW6_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW7_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW8_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW9_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW10_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW11_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW12_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW13_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW14_OP_CFG_ADDR 0x189a
+#define MT6359P_RG_BUCK_VS2_HW0_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW0_OP_MODE_SHIFT 0
+#define MT6359P_RG_BUCK_VS2_HW1_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW1_OP_MODE_SHIFT 1
+#define MT6359P_RG_BUCK_VS2_HW2_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW2_OP_MODE_SHIFT 2
+#define MT6359P_RG_BUCK_VS2_HW3_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW3_OP_MODE_SHIFT 3
+#define MT6359P_RG_BUCK_VS2_HW4_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW4_OP_MODE_SHIFT 4
+#define MT6359P_RG_BUCK_VS2_HW5_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW5_OP_MODE_SHIFT 5
+#define MT6359P_RG_BUCK_VS2_HW6_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW6_OP_MODE_SHIFT 6
+#define MT6359P_RG_BUCK_VS2_HW7_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW7_OP_MODE_SHIFT 7
+#define MT6359P_RG_BUCK_VS2_HW8_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW8_OP_MODE_SHIFT 8
+#define MT6359P_RG_BUCK_VS2_HW9_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW9_OP_MODE_SHIFT 9
+#define MT6359P_RG_BUCK_VS2_HW10_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW10_OP_MODE_SHIFT 10
+#define MT6359P_RG_BUCK_VS2_HW11_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW11_OP_MODE_SHIFT 11
+#define MT6359P_RG_BUCK_VS2_HW12_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW12_OP_MODE_SHIFT 12
+#define MT6359P_RG_BUCK_VS2_HW13_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW13_OP_MODE_SHIFT 13
+#define MT6359P_RG_BUCK_VS2_HW14_OP_MODE_ADDR 0x18a0
+#define MT6359P_RG_BUCK_VS2_HW14_OP_MODE_SHIFT 14
+#define MT6359P_RG_LDO_VFE28_OP_MODE_ADDR 0x1b8a
+#define MT6359P_RG_LDO_VFE28_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VFE28_HW0_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW1_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW2_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW3_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW4_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW5_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW6_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW7_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW8_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW9_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW10_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW11_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW12_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW13_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW14_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_SW_OP_EN_ADDR 0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW0_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW1_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW2_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW3_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW4_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW5_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW6_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW7_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW8_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW9_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW10_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW11_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW12_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW13_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_HW14_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VFE28_SW_OP_CFG_ADDR 0x1b94
+#define MT6359P_RG_LDO_VXO22_OP_MODE_ADDR 0x1b9c
+#define MT6359P_RG_LDO_VXO22_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VXO22_HW0_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW1_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW2_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW3_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW4_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW5_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW6_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW7_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW8_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW9_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW10_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW11_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW12_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW13_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW14_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_SW_OP_EN_ADDR 0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW0_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW1_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW2_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW3_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW4_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW5_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW6_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW7_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW8_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW9_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW10_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW11_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW12_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW13_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW14_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VXO22_SW_OP_CFG_ADDR 0x1ba6
+#define MT6359P_RG_LDO_VRF18_OP_MODE_ADDR 0x1bae
+#define MT6359P_RG_LDO_VRF18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VRF18_HW0_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW1_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW2_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW3_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW4_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW5_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW6_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW7_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW8_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW9_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW10_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW11_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW12_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW13_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW14_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_SW_OP_EN_ADDR 0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW0_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW1_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW2_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW3_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW4_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW5_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW6_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW7_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW8_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW9_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW10_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW11_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW12_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW13_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW14_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF18_SW_OP_CFG_ADDR 0x1bb8
+#define MT6359P_RG_LDO_VRF12_OP_MODE_ADDR 0x1bc0
+#define MT6359P_RG_LDO_VRF12_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VRF12_HW0_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW1_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW2_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW3_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW4_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW5_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW6_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW7_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW8_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW9_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW10_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW11_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW12_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW13_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW14_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_SW_OP_EN_ADDR 0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW0_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW1_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW2_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW3_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW4_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW5_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW6_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW7_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW8_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW9_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW10_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW11_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW12_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW13_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_HW14_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VRF12_SW_OP_CFG_ADDR 0x1bca
+#define MT6359P_RG_LDO_VEFUSE_OP_MODE_ADDR 0x1bd2
+#define MT6359P_RG_LDO_VEFUSE_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VEFUSE_HW0_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW1_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW2_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW3_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW4_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW5_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW6_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW7_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW8_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW9_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW10_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW11_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW12_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW13_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW14_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_SW_OP_EN_ADDR 0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW0_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW1_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW2_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW3_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW4_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW5_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW6_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW7_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW8_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW9_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW10_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW11_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW12_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW13_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW14_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_SW_OP_CFG_ADDR 0x1bdc
+#define MT6359P_RG_LDO_VCN33_1_OP_MODE_ADDR 0x1be4
+#define MT6359P_RG_LDO_VCN33_1_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCN33_1_HW0_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW1_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW2_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW3_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW4_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW5_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW6_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW7_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW8_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW9_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW10_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW11_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW12_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW13_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW14_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_SW_OP_EN_ADDR 0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW0_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW1_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW2_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW3_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW4_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW5_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW6_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW7_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW8_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW9_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW10_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW11_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW12_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW13_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW14_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_1_SW_OP_CFG_ADDR 0x1bee
+#define MT6359P_RG_LDO_VCN33_2_OP_MODE_ADDR 0x1c0a
+#define MT6359P_RG_LDO_VCN33_2_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCN33_2_HW0_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW1_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW2_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW3_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW4_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW5_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW6_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW7_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW8_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW9_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW10_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW11_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW12_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW13_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW14_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_SW_OP_EN_ADDR 0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW0_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW1_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW2_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW3_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW4_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW5_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW6_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW7_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW8_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW9_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW10_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW11_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW12_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW13_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW14_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN33_2_SW_OP_CFG_ADDR 0x1c14
+#define MT6359P_RG_LDO_VCN13_OP_MODE_ADDR 0x1c1e
+#define MT6359P_RG_LDO_VCN13_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCN13_HW0_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW1_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW2_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW3_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW4_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW5_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW6_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW7_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW8_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW9_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW10_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW11_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW12_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW13_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW14_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_SW_OP_EN_ADDR 0x1c22
+#define MT6359P_RG_LDO_VCN13_HW0_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW1_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW2_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW3_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW4_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW5_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW6_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW7_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW8_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW9_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW10_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW11_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW12_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW13_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_HW14_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN13_SW_OP_CFG_ADDR 0x1c28
+#define MT6359P_RG_LDO_VCN18_OP_MODE_ADDR 0x1c30
+#define MT6359P_RG_LDO_VCN18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCN18_HW0_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW1_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW2_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW3_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW4_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW5_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW6_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW7_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW8_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW9_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW10_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW11_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW12_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW13_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW14_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_SW_OP_EN_ADDR 0x1c34
+#define MT6359P_RG_LDO_VCN18_HW0_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW1_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW2_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW3_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW4_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW5_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW6_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW7_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW8_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW9_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW10_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW11_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW12_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW13_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW14_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VCN18_SW_OP_CFG_ADDR 0x1c3a
+#define MT6359P_RG_LDO_VA09_OP_MODE_ADDR 0x1c42
+#define MT6359P_RG_LDO_VA09_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VA09_HW0_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW1_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW2_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW3_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW4_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW5_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW6_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW7_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW8_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW9_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW10_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW11_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW12_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW13_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW14_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_SW_OP_EN_ADDR 0x1c46
+#define MT6359P_RG_LDO_VA09_HW0_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW1_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW2_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW3_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW4_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW5_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW6_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW7_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW8_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW9_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW10_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW11_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW12_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW13_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_HW14_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VA09_SW_OP_CFG_ADDR 0x1c4c
+#define MT6359P_RG_LDO_VCAMIO_OP_MODE_ADDR 0x1c54
+#define MT6359P_RG_LDO_VCAMIO_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VCAMIO_HW0_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW1_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW2_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW3_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW4_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW5_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW6_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW7_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW8_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW9_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW10_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW11_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW12_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW13_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW14_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_SW_OP_EN_ADDR 0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW0_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW1_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW2_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW3_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW4_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW5_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW6_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW7_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW8_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW9_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW10_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW11_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW12_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW13_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW14_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_SW_OP_CFG_ADDR 0x1c5e
+#define MT6359P_RG_LDO_VA12_OP_MODE_ADDR 0x1c66
+#define MT6359P_RG_LDO_VA12_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VA12_HW0_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW1_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW2_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW3_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW4_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW5_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW6_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW7_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW8_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW9_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW10_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW11_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW12_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW13_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW14_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_SW_OP_EN_ADDR 0x1c6a
+#define MT6359P_RG_LDO_VA12_HW0_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW1_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW2_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW3_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW4_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW5_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW6_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW7_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW8_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW9_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW10_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW11_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW12_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW13_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_HW14_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VA12_SW_OP_CFG_ADDR 0x1c70
+#define MT6359P_RG_LDO_VAUX18_OP_MODE_ADDR 0x1c8a
+#define MT6359P_RG_LDO_VAUX18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VAUX18_HW0_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW1_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW2_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW3_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW4_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW5_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW6_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW7_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW8_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW9_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW10_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW11_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW12_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW13_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW14_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_SW_OP_EN_ADDR 0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW0_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW1_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW2_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW3_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW4_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW5_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW6_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW7_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW8_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW9_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW10_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW11_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW12_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW13_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW14_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUX18_SW_OP_CFG_ADDR 0x1c94
+#define MT6359P_RG_LDO_VAUD18_OP_MODE_ADDR 0x1c9c
+#define MT6359P_RG_LDO_VAUD18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VAUD18_HW0_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW1_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW2_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW3_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW4_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW5_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW6_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW7_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW8_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW9_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW10_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW11_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW12_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW13_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW14_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_SW_OP_EN_ADDR 0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW0_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW1_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW2_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW3_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW4_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW5_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW6_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW7_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW8_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW9_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW10_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW11_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW12_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW13_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW14_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VAUD18_SW_OP_CFG_ADDR 0x1ca6
+#define MT6359P_RG_LDO_VIO18_OP_MODE_ADDR 0x1cae
+#define MT6359P_RG_LDO_VIO18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VIO18_HW0_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW1_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW2_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW3_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW4_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW5_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW6_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW7_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW8_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW9_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW10_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW11_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW12_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW13_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW14_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_SW_OP_EN_ADDR 0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW0_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW1_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW2_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW3_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW4_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW5_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW6_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW7_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW8_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW9_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW10_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW11_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW12_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW13_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW14_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VIO18_SW_OP_CFG_ADDR 0x1cb8
+#define MT6359P_RG_LDO_VEMC_OP_MODE_ADDR 0x1cc0
+#define MT6359P_RG_LDO_VEMC_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VEMC_HW0_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW1_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW2_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW3_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW4_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW5_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW6_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW7_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW8_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW9_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW10_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW11_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW12_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW13_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW14_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_SW_OP_EN_ADDR 0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW0_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW1_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW2_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW3_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW4_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW5_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW6_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW7_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW8_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW9_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW10_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW11_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW12_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW13_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_HW14_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VEMC_SW_OP_CFG_ADDR 0x1cca
+#define MT6359P_RG_LDO_VSIM1_OP_MODE_ADDR 0x1cd2
+#define MT6359P_RG_LDO_VSIM1_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSIM1_HW0_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW1_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW2_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW3_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW4_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW5_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW6_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW7_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW8_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW9_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW10_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW11_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW12_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW13_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW14_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_SW_OP_EN_ADDR 0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW0_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW1_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW2_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW3_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW4_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW5_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW6_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW7_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW8_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW9_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW10_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW11_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW12_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW13_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW14_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM1_SW_OP_CFG_ADDR 0x1cdc
+#define MT6359P_RG_LDO_VSIM2_OP_MODE_ADDR 0x1ce4
+#define MT6359P_RG_LDO_VSIM2_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSIM2_HW0_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW1_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW2_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW3_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW4_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW5_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW6_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW7_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW8_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW9_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW10_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW11_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW12_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW13_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW14_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_SW_OP_EN_ADDR 0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW0_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW1_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW2_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW3_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW4_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW5_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW6_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW7_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW8_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW9_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW10_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW11_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW12_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW13_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW14_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VSIM2_SW_OP_CFG_ADDR 0x1cee
+#define MT6359P_RG_LDO_VUSB_OP_MODE_ADDR 0x1d0a
+#define MT6359P_RG_LDO_VUSB_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VUSB_HW0_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW1_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW2_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW3_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW4_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW5_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW6_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW7_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW8_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW9_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW10_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW11_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW12_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW13_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW14_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_SW_OP_EN_ADDR 0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW0_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW1_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW2_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW3_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW4_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW5_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW6_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW7_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW8_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW9_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW10_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW11_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW12_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW13_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_HW14_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VUSB_SW_OP_CFG_ADDR 0x1d14
+#define MT6359P_RG_LDO_VRFCK_OP_MODE_ADDR 0x1d1e
+#define MT6359P_RG_LDO_VRFCK_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VRFCK_HW0_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW1_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW2_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW3_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW4_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW5_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW6_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW7_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW8_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW9_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW10_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW11_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW12_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW13_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW14_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_SW_OP_EN_ADDR 0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW0_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW1_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW2_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW3_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW4_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW5_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW6_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW7_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW8_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW9_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW10_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW11_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW12_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW13_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW14_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VRFCK_SW_OP_CFG_ADDR 0x1d28
+#define MT6359P_RG_LDO_VBBCK_OP_MODE_ADDR 0x1d30
+#define MT6359P_RG_LDO_VBBCK_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VBBCK_HW0_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW1_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW2_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW3_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW4_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW5_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW6_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW7_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW8_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW9_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW10_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW11_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW12_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW13_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW14_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_SW_OP_EN_ADDR 0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW0_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW1_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW2_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW3_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW4_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW5_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW6_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW7_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW8_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW9_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW10_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW11_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW12_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW13_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW14_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBBCK_SW_OP_CFG_ADDR 0x1d3a
+#define MT6359P_RG_LDO_VBIF28_OP_MODE_ADDR 0x1d42
+#define MT6359P_RG_LDO_VBIF28_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VBIF28_HW0_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW1_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW2_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW3_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW4_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW5_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW6_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW7_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW8_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW9_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW10_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW11_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW12_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW13_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW14_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_SW_OP_EN_ADDR 0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW0_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW1_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW2_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW3_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW4_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW5_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW6_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW7_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW8_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW9_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW10_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW11_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW12_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW13_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW14_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VBIF28_SW_OP_CFG_ADDR 0x1d4c
+#define MT6359P_RG_LDO_VIBR_OP_MODE_ADDR 0x1d54
+#define MT6359P_RG_LDO_VIBR_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VIBR_HW0_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW1_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW2_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW3_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW4_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW5_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW6_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW7_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW8_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW9_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW10_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW11_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW12_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW13_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW14_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_SW_OP_EN_ADDR 0x1d58
+#define MT6359P_RG_LDO_VIBR_HW0_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW1_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW2_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW3_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW4_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW5_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW6_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW7_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW8_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW9_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW10_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW11_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW12_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW13_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW14_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIBR_SW_OP_CFG_ADDR 0x1d5e
+#define MT6359P_RG_LDO_VIO28_OP_MODE_ADDR 0x1d66
+#define MT6359P_RG_LDO_VIO28_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VIO28_HW0_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW1_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW2_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW3_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW4_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW5_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW6_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW7_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW8_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW9_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW10_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW11_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW12_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW13_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW14_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_SW_OP_EN_ADDR 0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW0_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW1_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW2_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW3_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW4_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW5_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW6_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW7_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW8_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW9_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW10_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW11_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW12_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW13_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_HW14_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VIO28_SW_OP_CFG_ADDR 0x1d70
+#define MT6359P_RG_LDO_VM18_OP_MODE_ADDR 0x1d8a
+#define MT6359P_RG_LDO_VM18_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VM18_HW0_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW1_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW2_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW3_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW4_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW5_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW6_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW7_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW8_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW9_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW10_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW11_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW12_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW13_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW14_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_SW_OP_EN_ADDR 0x1d8e
+#define MT6359P_RG_LDO_VM18_HW0_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW1_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW2_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW3_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW4_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW5_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW6_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW7_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW8_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW9_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW10_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW11_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW12_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW13_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_HW14_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VM18_SW_OP_CFG_ADDR 0x1d94
+#define MT6359P_RG_LDO_VUFS_OP_MODE_ADDR 0x1d9c
+#define MT6359P_RG_LDO_VUFS_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VUFS_HW0_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW1_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW2_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW3_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW4_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW5_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW6_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW7_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW8_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW9_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW10_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW11_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW12_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW13_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW14_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_SW_OP_EN_ADDR 0x1da0
+#define MT6359P_RG_LDO_VUFS_HW0_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW1_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW2_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW3_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW4_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW5_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW6_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW7_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW8_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW9_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW10_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW11_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW12_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW13_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_HW14_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VUFS_SW_OP_CFG_ADDR 0x1da6
+#define MT6359P_RG_LDO_VSRAM_PROC1_OP_MODE_ADDR 0x1e8a
+#define MT6359P_RG_LDO_VSRAM_PROC1_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP_ADDR 0x1e8e
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW0_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW1_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW2_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW3_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW4_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW5_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW6_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW7_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW8_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW9_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW10_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW11_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW12_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW13_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW14_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_SW_OP_EN_ADDR 0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW0_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW1_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW2_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW3_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW4_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW5_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW6_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW7_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW8_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW9_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW10_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW11_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW12_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW13_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW14_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_SW_OP_CFG_ADDR 0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC2_OP_MODE_ADDR 0x1eaa
+#define MT6359P_RG_LDO_VSRAM_PROC2_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP_ADDR 0x1eae
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW0_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW1_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW2_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW3_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW4_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW5_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW6_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW7_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW8_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW9_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW10_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW11_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW12_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW13_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW14_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_SW_OP_EN_ADDR 0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW0_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW1_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW2_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW3_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW4_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW5_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW6_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW7_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW8_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW9_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW10_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW11_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW12_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW13_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW14_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_SW_OP_CFG_ADDR 0x1ebc
+#define MT6359P_RG_LDO_VSRAM_OTHERS_OP_MODE_ADDR 0x1f0a
+#define MT6359P_RG_LDO_VSRAM_OTHERS_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_ADDR 0x1f0e
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW0_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW1_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW2_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW3_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW4_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW5_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW6_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW7_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW8_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW9_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW10_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW11_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW12_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW13_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW14_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SW_OP_EN_ADDR 0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW0_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW1_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW2_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW3_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW4_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW5_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW6_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW7_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW8_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW9_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW10_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW11_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW12_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW13_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW14_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SW_OP_CFG_ADDR 0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP_ADDR 0x1f28
+#define MT6359P_RG_LDO_VSRAM_MD_OP_MODE_ADDR 0x1f30
+#define MT6359P_RG_LDO_VSRAM_MD_OP_MODE_SHIFT 10
+#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_SLEEP_ADDR 0x1f34
+#define MT6359P_RG_LDO_VSRAM_MD_HW0_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW1_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW2_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW3_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW4_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW5_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW6_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW7_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW8_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW9_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW10_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW11_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW12_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW13_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW14_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_SW_OP_EN_ADDR 0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW0_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW1_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW2_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW3_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW4_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW5_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW6_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW7_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW8_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW9_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW10_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW11_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW12_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW13_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW14_OP_CFG_ADDR 0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_SW_OP_CFG_ADDR 0x1f42
+
+#endif /* MT6359P_LOWPOWER_REG_H */
diff --git a/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h b/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h
new file mode 100644
index 0000000..60b49bf
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6359P_SET_LOWPOWER_H
+#define MT6359P_SET_LOWPOWER_H
+
+#include <stdint.h>
+
+#include "mt6359p_lowpower_reg.h"
+#include <pmic_wrap_init_common.h>
+
+#define OP_MODE_MU (0)
+#define OP_MODE_LP (1)
+
+#define HW_OFF (0)
+#define HW_ON (0)
+#define HW_LP (1)
+
+enum {
+ HW0 = 0,
+ HW1,
+ HW2,
+ HW3,
+ HW4,
+ HW5,
+ HW6,
+ HW7,
+ HW8,
+ HW9,
+ HW10,
+ HW11,
+ HW12,
+ HW13,
+ HW14,
+};
+
+#define PMIC_BUCK_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \
+{ \
+ pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
+ 1 << _user, \
+ (_cfg & 0x1) ? 1 << _user : 0); \
+ pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
+ 1 << _user, \
+ _mode ? 1 << _user : 0); \
+ pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
+ 1 << _user, \
+ _en ? 1 << _user : 0); \
+}
+
+#define PMIC_LDO_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \
+{ \
+ if (_user <= HW2) { \
+ pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_OP_MODE_ADDR, \
+ 1 << (_user + _chip##_RG_LDO_##_name##_OP_MODE_SHIFT), \
+ _mode ? 1 << (_user + _chip##_RG_LDO_##_name##_OP_MODE_SHIFT) : 0); \
+ } \
+ pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_CFG_ADDR, \
+ 1 << _user, \
+ (_cfg & 0x1) ? 1 << _user : 0); \
+ pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_EN_ADDR, \
+ 1 << _user, \
+ _en ? 1 << _user : 0); \
+}
+
+static inline int pmic_wrap_update_bits(uint32_t reg, uint32_t mask, uint32_t val)
+{
+ uint32_t orig = 0;
+ int ret = 0;
+
+ ret = pwrap_read(reg, &orig);
+ if (ret < 0)
+ return ret;
+
+ orig &= ~mask;
+ orig |= val & mask;
+
+ ret = pwrap_write(reg, orig);
+ return ret;
+}
+
+#endif /* MT6359P_MT6359P_SET_LOWPOWER_H */
diff --git a/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h b/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
index f79612d..4f0517f 100644
--- a/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
+++ b/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
@@ -12,6 +12,7 @@
#include <drivers/spmi_api.h>
#include "mt6316_lowpower_reg.h"
+#include "mt6319_lowpower_reg.h"
#include "mt6363_lowpower_reg.h"
#include "mt6373_lowpower_reg.h"
diff --git a/plat/mediatek/mt8189/include/platform_def.h b/plat/mediatek/mt8189/include/platform_def.h
index 067ebcc..54bf5ba 100644
--- a/plat/mediatek/mt8189/include/platform_def.h
+++ b/plat/mediatek/mt8189/include/platform_def.h
@@ -143,4 +143,40 @@
******************************************************************************/
#define SYSTIMER_BASE (IO_PHYS + 0x0CC10000)
+/*******************************************************************************
+ * SPMI related definitions
+ ******************************************************************************/
+#define SPMI_MST_P_BASE (IO_PHYS + 0x0CC00000)
+#define PMIF_SPMI_P_BASE (IO_PHYS + 0x0CC06000)
+#define SPMI_MST_P_SIZE (0x1000)
+
+/*******************************************************************************
+ * PWRAP related definitions
+ ******************************************************************************/
+#define PMICSPI_MST_BASE (IO_PHYS + 0x0c013000)
+#define PMICSPI_MST_SIZE (0x1000)
+#define PMIC_WRAP_BASE (IO_PHYS + 0x0CC04000)
+#define PMIF_SPI_BASE (0x1CC04000)
+#define PWRAP_REG_BASE (0x1C013000)
+#define PWRAP_WRAP_EN (PWRAP_REG_BASE + 0x14)
+
+/*******************************************************************************
+ * PMIC regsister related definitions
+ ******************************************************************************/
+#define PMIC_REG_BASE (0x0000)
+#define PWRAP_SIZE (0x1000)
+#define DEW_READ_TEST (PMIC_REG_BASE + 0x040e)
+#define DEW_WRITE_TEST (PMIC_REG_BASE + 0x0410)
+
+/*******************************************************************************
+ * Differentiate between 3G and 2.6G-related definitions
+ ******************************************************************************/
+#define EFUSEC_BASE (IO_PHYS + 0x01F10000)
+#define CHIP_ID_REG (EFUSEC_BASE + 0x7A0)
+#define CPU_SEG_ID_REG (EFUSEC_BASE + 0x7E0)
+
+#define MTK_CPU_ID_MT8189 0x81890000
+#define MTK_CPU_SEG_ID_MT8189G 0x20
+#define MTK_CPU_SEG_ID_MT8189H 0x21
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/mt8189/plat_config.mk b/plat/mediatek/mt8189/plat_config.mk
index f06555b..6293052 100644
--- a/plat/mediatek/mt8189/plat_config.mk
+++ b/plat/mediatek/mt8189/plat_config.mk
@@ -23,6 +23,14 @@
PLAT_EXTRA_RODATA_INCLUDES := 1
CONFIG_MTK_DISABLE_CACHE_AS_RAM := $(COREBOOT)
+CONFIG_MTK_PMIC := y
+CONFIG_MTK_PMIC_LOWPOWER := y
+CONFIG_MTK_PMIC_SHUTDOWN_CFG := y
+CONFIG_MTK_PMIC_SHUTDOWN_V2 := y
+CONFIG_MTK_SPMI := y
+PMIC_CHIP := mt6359p
+USE_PMIC_WRAP_INIT_V3 := 1
+
# Configs for A78 and A55
CTX_INCLUDE_AARCH32_REGS := 0
ERRATA_A55_1530923 := 1
diff --git a/plat/mediatek/mt8189/platform.mk b/plat/mediatek/mt8189/platform.mk
index c0c0427..381071a 100644
--- a/plat/mediatek/mt8189/platform.mk
+++ b/plat/mediatek/mt8189/platform.mk
@@ -31,7 +31,10 @@
MODULES-y += $(MTK_PLAT)/drivers/gic600
MODULES-y += $(MTK_PLAT)/drivers/iommu
MODULES-y += $(MTK_PLAT)/drivers/mcusys
+MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap
MODULES-y += $(MTK_PLAT)/drivers/timer
+MODULES-$(CONFIG_MTK_PMIC) += $(MTK_PLAT)/drivers/pmic
+MODULES-$(CONFIG_MTK_SPMI) += $(MTK_PLAT)/drivers/spmi
PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \
drivers/ti/uart/aarch64/16550_console.S \
diff --git a/plat/mediatek/mt8196/plat_config.mk b/plat/mediatek/mt8196/plat_config.mk
index e0dd87e..a7f17e1 100644
--- a/plat/mediatek/mt8196/plat_config.mk
+++ b/plat/mediatek/mt8196/plat_config.mk
@@ -59,6 +59,7 @@
CONFIG_MTK_PMIC := y
CONFIG_MTK_PMIC_LOWPOWER := y
CONFIG_MTK_PMIC_SHUTDOWN_CFG := y
+CONFIG_MTK_PMIC_SHUTDOWN_V2 := y
CONFIG_MTK_PMIC_SPT_SUPPORT := n
CONFIG_MTK_SMMU_SID := y
CONFIG_MTK_SPMI := y
diff --git a/services/std_svc/drtm/drtm_dma_prot.h b/services/std_svc/drtm/drtm_dma_prot.h
index 79dc9cb..5ccff87 100644
--- a/services/std_svc/drtm/drtm_dma_prot.h
+++ b/services/std_svc/drtm/drtm_dma_prot.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -20,7 +20,7 @@
enum dma_prot_type {
PROTECT_NONE = -1,
PROTECT_MEM_ALL = 0,
- PROTECT_MEM_REGION = 2,
+ PROTECT_MEM_REGION = 1,
};
struct dma_prot {
diff --git a/services/std_svc/drtm/drtm_measurements.c b/services/std_svc/drtm/drtm_measurements.c
index 7214e23..4518d37 100644
--- a/services/std_svc/drtm/drtm_measurements.c
+++ b/services/std_svc/drtm/drtm_measurements.c
@@ -138,7 +138,8 @@
/* PCR-17: End of DCE measurements. */
rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data,
strlen(drtm_event_arm_sep_data),
- DRTM_EVENT_ARM_SEPARATOR, NULL,
+ DRTM_EVENT_ARM_SEPARATOR,
+ drtm_event_arm_sep_data,
PCR_17);
CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));
@@ -188,7 +189,7 @@
/* PCR-18: Measure the DLME image entry point. */
dlme_img_ep = DL_ARGS_GET_DLME_ENTRY_POINT(a);
- drtm_event_log_measure_and_record((uintptr_t)&dlme_img_ep,
+ drtm_event_log_measure_and_record((uintptr_t)&(a->dlme_img_ep_off),
sizeof(dlme_img_ep),
DRTM_EVENT_ARM_DLME_EP, NULL,
PCR_18);
@@ -197,7 +198,8 @@
/* PCR-18: End of DCE measurements. */
rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data,
strlen(drtm_event_arm_sep_data),
- DRTM_EVENT_ARM_SEPARATOR, NULL,
+ DRTM_EVENT_ARM_SEPARATOR,
+ drtm_event_arm_sep_data,
PCR_18);
CHECK_RC(rc,
drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));
diff --git a/services/std_svc/sdei/sdei_event.c b/services/std_svc/sdei/sdei_event.c
index cc8f557..9c7f74a 100644
--- a/services/std_svc/sdei/sdei_event.c
+++ b/services/std_svc/sdei/sdei_event.c
@@ -61,11 +61,13 @@
* Both shared and private maps are stored in single-dimensional array. Private
* event entries are kept for each PE forming a 2D array.
*/
-sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm, uint64_t target_pe)
+sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm,
+uint64_t target_pe)
{
sdei_entry_t *cpu_priv_base;
- unsigned int base_idx;
+ unsigned int base_idx = 0U;
long int idx;
+ int target_pos;
/*
* For a private map, find the index of the mapping in the
@@ -74,9 +76,17 @@
idx = mapsub;
/* Base of private mappings for this CPU */
- base_idx = (unsigned int) plat_core_pos_by_mpidr(target_pe);
+ target_pos = plat_core_pos_by_mpidr(target_pe);
+
+ if ((target_pos < 0) || ((unsigned int)target_pos >= PLATFORM_CORE_COUNT)) {
+ return NULL;
+ }
+
+ base_idx = (unsigned int) target_pos;
base_idx *= nm;
+
cpu_priv_base = &sdei_private_event_table[base_idx];
+
/*
* Return the address of the entry at the same index in the
* per-CPU event entry.
diff --git a/services/std_svc/sdei/sdei_intr_mgmt.c b/services/std_svc/sdei/sdei_intr_mgmt.c
index 4854b2e..40c3c24 100644
--- a/services/std_svc/sdei/sdei_intr_mgmt.c
+++ b/services/std_svc/sdei/sdei_intr_mgmt.c
@@ -61,9 +61,12 @@
bool sdei_is_target_pe_masked(uint64_t target_pe)
{
- const sdei_cpu_state_t *state = sdei_get_target_pe_state(target_pe);
-
- return state->pe_masked;
+ int errstat = plat_core_pos_by_mpidr(target_pe);
+ if (errstat >= 0) {
+ const sdei_cpu_state_t *state = &cpu_state[errstat];
+ return state->pe_masked;
+ }
+ return true;
}
int64_t sdei_pe_mask(void)
diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c
index bbc9f73..52c01e8 100644
--- a/services/std_svc/sdei/sdei_main.c
+++ b/services/std_svc/sdei/sdei_main.c
@@ -948,6 +948,9 @@
if (map_priv->ev_num == SDEI_EVENT_0) {
se = get_event_entry_target_pe((long int) i,
(unsigned int) SDEI_PRIVATE_MAPPING()->num_maps, target_pe);
+ if (se == NULL) {
+ return SDEI_EINVAL;
+ }
if (!(GET_EV_STATE((se), REGISTERED))) {
return SDEI_EINVAL;
}
