)]}' { "log": [ { "commit": "330b42e7758515443a5ce41269b2180e3e90a0f6", "tree": "36d7d8d5fbb949f7edf7caaefffafaed76bf03d1", "parents": [ "2f89ed5b90cc7ce545647284f001d07cc55b434c" ], "author": { "name": "Andrew Walbran", "email": "qwandor@google.com", "time": "Thu Nov 18 17:22:49 2021 +0000" }, "committer": { "name": "Andrew Walbran", "email": "qwandor@google.com", "time": "Fri Nov 19 14:24:24 2021 +0000" }, "message": "Use PRIx64 macro for printing uint64_t values.\n\nThis is necessary to fix the build after merging upstream changes.\n\nChange-Id: I8dffbcf8f2c46ff3dc50c1654b8b143ff023e34a\n" }, { "commit": "2f89ed5b90cc7ce545647284f001d07cc55b434c", "tree": "548542853ed949ad5951e803268f33ea1c145968", "parents": [ "a81d1ecbfc0f5a808347fc8f14c052ae1c109b95", "d5c70fa9f998af0815cdeb9e6a42682f210bbdd4" ], "author": { "name": "Andrew Walbran", "email": "qwandor@google.com", "time": "Thu Nov 18 17:17:13 2021 +0000" }, "committer": { "name": "Andrew Walbran", "email": "qwandor@google.com", "time": "Fri Nov 19 14:22:55 2021 +0000" }, "message": "Merge branch \u0027upstream/master\u0027 into main\n\nChange-Id: Id6f67665a9ee7f90cf5114727c525727a6c4cb19\n" }, { "commit": "d5c70fa9f998af0815cdeb9e6a42682f210bbdd4", "tree": "0dbfabf446643fa44a9d00e1989aa3c9553b912a", "parents": [ "55b2e6f0d3b6d822ce46e287dd4ba233be12d441", "4333f95bedb5f2b53dcb62e0e9c563794ec33c07" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Nov 16 23:30:55 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 16 23:30:55 2021 +0100" }, "message": "Merge \"fix(spm_mm): do not compile if SVE/SME is enabled\" into integration" }, { "commit": "4333f95bedb5f2b53dcb62e0e9c563794ec33c07", "tree": "17b00ea2387dd23b87597fb6dd928a34b73d2ef2", "parents": [ "3015267f600068a52884956328d89a95740f27b4" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Nov 15 15:29:08 2021 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Nov 16 16:06:33 2021 +0000" }, "message": "fix(spm_mm): do not compile if SVE/SME is enabled\n\nAs spm_mm cannot handle SVE/SME usage in NS world so its better to give\ncompilation error when ENABLE_SVE_FOR_NS\u003d1 or ENABLE_SME_FOR_NS\u003d1.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I69dbb272ca681bb020501342008eda20d4c0b096\n" }, { "commit": "55b2e6f0d3b6d822ce46e287dd4ba233be12d441", "tree": "2f93fa3fdf57d2777a8b767da1f330c14118898a", "parents": [ "3015267f600068a52884956328d89a95740f27b4", "7446c266c91bc28c87fca634df57bdcf15b32a5b" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Nov 16 11:53:24 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 16 11:53:24 2021 +0100" }, "message": "Merge changes I9e6feeee,If1cd7962 into integration\n\n* changes:\n docs(rme): add description of TF-A changes for RME\n docs(gpt): add documentation page for GPT library\n" }, { "commit": "7446c266c91bc28c87fca634df57bdcf15b32a5b", "tree": "2f93fa3fdf57d2777a8b767da1f330c14118898a", "parents": [ "6ee92598cf540ac5746f8af714aa3601ea03ad3d" ], "author": { "name": "Zelalem Aweke", "email": "zelalem.aweke@arm.com", "time": "Thu Oct 21 13:59:45 2021 -0500" }, "committer": { "name": "Zelalem Aweke", "email": "zelalem.aweke@arm.com", "time": "Mon Nov 15 22:20:07 2021 +0100" }, "message": "docs(rme): add description of TF-A changes for RME\n\nThis patch expands the RME documentation with description of TF-A\nchanges for RME. It also modifies some other parts of TF-A documentation\nto account for RME changes.\n\nSigned-off-by: Zelalem Aweke \u003czelalem.aweke@arm.com\u003e\nChange-Id: I9e6feeee235f0ba4b767d239f15840f1e0c540bb\n" }, { "commit": "6ee92598cf540ac5746f8af714aa3601ea03ad3d", "tree": "05488479f31c86319a1b54fd3af12619daa852c5", "parents": [ "3015267f600068a52884956328d89a95740f27b4" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Wed Aug 25 16:32:23 2021 -0500" }, "committer": { "name": "John", "email": "john.powell@arm.com", "time": "Mon Nov 15 23:17:04 2021 +0200" }, "message": "docs(gpt): add documentation page for GPT library\n\nThis patch adds some documentation for the GPT library as well as adds\ncode owners for it.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: If1cd79626eadb27e1024d731b26ee2e20af74a66\n" }, { "commit": "3015267f600068a52884956328d89a95740f27b4", "tree": "443e3060373aaccb2c65986f068b685673c3d496", "parents": [ "2242773ddbd959677af69d9df3aba3fd1b0bb4e1", "dc78e62d80e64bf4fe5d5bf4844a7bd1696b7c92" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Nov 12 19:51:42 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 12 19:51:42 2021 +0100" }, "message": "Merge \"feat(sme): enable SME functionality\" into integration" }, { "commit": "dc78e62d80e64bf4fe5d5bf4844a7bd1696b7c92", "tree": "443e3060373aaccb2c65986f068b685673c3d496", "parents": [ "2242773ddbd959677af69d9df3aba3fd1b0bb4e1" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Thu Jul 08 14:14:00 2021 -0500" }, "committer": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Fri Nov 12 10:38:00 2021 -0600" }, "message": "feat(sme): enable SME functionality\n\nThis patch adds two new compile time options to enable SME in TF-A:\nENABLE_SME_FOR_NS and ENABLE_SME_FOR_SWD for use in non-secure and\nsecure worlds respectively. Setting ENABLE_SME_FOR_NS\u003d1 will enable\nSME for non-secure worlds and trap SME, SVE, and FPU/SIMD instructions\nin secure context. Setting ENABLE_SME_FOR_SWD\u003d1 will disable these\ntraps, but support for SME context management does not yet exist in\nSPM so building with SPD\u003dspmd will fail.\n\nThe existing ENABLE_SVE_FOR_NS and ENABLE_SVE_FOR_SWD options cannot\nbe used with SME as it is a superset of SVE and will enable SVE and\nFPU/SIMD along with SME.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Iaaac9d22fe37b4a92315207891da848a8fd0ed73\n" }, { "commit": "2242773ddbd959677af69d9df3aba3fd1b0bb4e1", "tree": "374d6d750e0457890e256e04e448051cb382783d", "parents": [ "d15e4e085a0057025d05c199180ce47a96985b51", "4ef449c15a4055d92632cb7e72267f525a7e2fca" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Nov 12 15:01:00 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 12 15:01:00 2021 +0100" }, "message": "Merge \"fix: use correct printf format for uint64_t\" into integration" }, { "commit": "4ef449c15a4055d92632cb7e72267f525a7e2fca", "tree": "2176da7a5cbb4fab6d2e5aaf895860412a1b39f8", "parents": [ "66c3906e4c32d675eb06bd081de8a3359f76b84c" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Nov 12 12:59:09 2021 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Nov 12 13:02:02 2021 +0000" }, "message": "fix: use correct printf format for uint64_t\n\nsha 4ce3e99a3 introduced printf format specifiers for fixed width\ntypes, which uses PRI*64 instead of \"ll\" for 64 bit values.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Ic6811cc1788c698adde0807e5f8ab5290a900a26\n" }, { "commit": "d15e4e085a0057025d05c199180ce47a96985b51", "tree": "e1c216e077a823c1f24e9ad98ba8132fb5a3cb36", "parents": [ "66c3906e4c32d675eb06bd081de8a3359f76b84c", "964ee4e6be70ef638d6c875a761ab5ca359d84fe" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Nov 12 12:53:30 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 12 12:53:30 2021 +0100" }, "message": "Merge \"fix(mt8195): use correct print format for uint64_t\" into integration" }, { "commit": "964ee4e6be70ef638d6c875a761ab5ca359d84fe", "tree": "e1c216e077a823c1f24e9ad98ba8132fb5a3cb36", "parents": [ "66c3906e4c32d675eb06bd081de8a3359f76b84c" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Nov 11 11:32:53 2021 -0600" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Nov 11 12:23:36 2021 -0600" }, "message": "fix(mt8195): use correct print format for uint64_t\n\nsha 4ce3e99a3 introduced printf format specifiers for fixed width\ntypes, which uses PRI*64 instead of \"ll\" for 64 bit variables.\n\nChange-Id: I09a8d174694d4b170a6ef2e4a03df13adc829c00\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "66c3906e4c32d675eb06bd081de8a3359f76b84c", "tree": "0ff165f1190b5e2a480be25999dc41b6227f5cef", "parents": [ "b6b486f3839de9e2962d57ed735af7a393677831", "52558e080d56a619a1477b19e33f88b754bb93a6" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Nov 11 17:20:48 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Nov 11 17:20:48 2021 +0100" }, "message": "Merge \"docs(spm): secure interrupt management in SPMC\" into integration" }, { "commit": "52558e080d56a619a1477b19e33f88b754bb93a6", "tree": "0ff165f1190b5e2a480be25999dc41b6227f5cef", "parents": [ "b6b486f3839de9e2962d57ed735af7a393677831" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Sep 23 14:29:05 2021 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Nov 10 16:07:33 2021 -0600" }, "message": "docs(spm): secure interrupt management in SPMC\n\nChange-Id: I9bed67e4146ae92123ab925334e37fb0d3677ef1\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "b6b486f3839de9e2962d57ed735af7a393677831", "tree": "6d567ba69bffd82816a94dfd387dc5a2c9540fd6", "parents": [ "7ddeabab27c8c324468f6fc0d21ade259ef97760", "d39db2695ba626b9c0ee38652fe160b4e84b15d9" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Nov 10 14:20:48 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 10 14:20:48 2021 +0100" }, "message": "Merge \"fix(sdei): fix assert while kdump issue\" into integration" }, { "commit": "7ddeabab27c8c324468f6fc0d21ade259ef97760", "tree": "8a4d21b35063ca0d4473986493ba741089b78fe7", "parents": [ "a706524417fbb5844c0b057bdcad263679a693f4", "2461bd3a89f7f2cdf4a7302536746733970cfe53" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Nov 10 11:35:48 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 10 11:35:48 2021 +0100" }, "message": "Merge \"fix(gpt_rme): use correct print format for uint64_t\" into integration" }, { "commit": "2461bd3a89f7f2cdf4a7302536746733970cfe53", "tree": "8a4d21b35063ca0d4473986493ba741089b78fe7", "parents": [ "a706524417fbb5844c0b057bdcad263679a693f4" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Nov 09 20:49:56 2021 +0000" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Nov 09 20:58:03 2021 +0000" }, "message": "fix(gpt_rme): use correct print format for uint64_t\n\nsha 4ce3e99a3 introduced printf format specifiers for fixed width\ntypes, which uses PRI*64 instead of \"ll\" for 64 bit values.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I30472411467061d58cc6ee22407ed3bad2552751\n" }, { "commit": "a706524417fbb5844c0b057bdcad263679a693f4", "tree": "70dbfe93338278a6fb4e762b14a450e37cecd47e", "parents": [ "c8390565b26d163b22013ebb4d14aab99b7ff2f7", "51d8d1e326e39c83e49a0f4c4c269db74fcda226" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Tue Nov 09 21:13:39 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 09 21:13:39 2021 +0100" }, "message": "Merge \"Changing SMC code for transitioning Granule\" into integration" }, { "commit": "c8390565b26d163b22013ebb4d14aab99b7ff2f7", "tree": "3680d1d5ee0d856a1da400a190fc6006e33f8836", "parents": [ "f7a83544813bd6806f77424cac0d1441326d1c5b", "0c23e6f44d41593b6e7f97594c12b5791bd75189" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Nov 09 16:16:28 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 09 16:16:28 2021 +0100" }, "message": "Merge \"fix(spmd): error macro to use correct print format\" into integration" }, { "commit": "f7a83544813bd6806f77424cac0d1441326d1c5b", "tree": "41225f6ca25e0cc59a12f6eec70f9d42afbd92dd", "parents": [ "a127b99d5a063c798d1c6d2e1d4791a630f78355", "a125c556230501ee0f5ec9f8b0b721625d484a41" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Tue Nov 09 16:08:25 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 09 16:08:25 2021 +0100" }, "message": "Merge \"feat(measured boot): add documentation to build and run PoC\" into integration" }, { "commit": "0c23e6f44d41593b6e7f97594c12b5791bd75189", "tree": "88f19707680df2da4bc0700b0872ba63e8be2941", "parents": [ "a127b99d5a063c798d1c6d2e1d4791a630f78355" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Nov 09 12:37:20 2021 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Nov 09 15:44:24 2021 +0100" }, "message": "fix(spmd): error macro to use correct print format\n\nFollowing merge of [1] then [2] broke the build because of an incorrect\nformat specifier in an ERROR macro. Fix to use the correct print format.\n\n[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5437\n[2] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9211\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I14d4c31091f6a5f4c3252f6d810e9d2bb2f545c4\n" }, { "commit": "a127b99d5a063c798d1c6d2e1d4791a630f78355", "tree": "3e6f3af603c018c3183fd66456c0c072a71fbd5a", "parents": [ "2e43638e9541e35984b616015971dd517d7da853", "8cb99c3fc3539bb9926e73a1c33fd72f424fc453" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Nov 09 11:57:30 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 09 11:57:30 2021 +0100" }, "message": "Merge \"feat(SPMD): route secure interrupts to SPMC\" into integration" }, { "commit": "2e43638e9541e35984b616015971dd517d7da853", "tree": "cb2a24126cfa9e423effa8e1ac6e423a625071cd", "parents": [ "28623c102d6fec0ba0271be64951679bf20681ba", "216c1223c2c65bd1c119a28b9406f70a9ee7b063" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Nov 09 06:03:32 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 09 06:03:32 2021 +0100" }, "message": "Merge changes from topic \"st_usb\" into integration\n\n* changes:\n fix(drivers/usb): add a optional ops get_other_speed_config_desc\n fix(drivers/usb): remove unnecessary cast\n" }, { "commit": "28623c102d6fec0ba0271be64951679bf20681ba", "tree": "3d7f668993625ec3eb4c9e0d63a5c68af1d9f1ef", "parents": [ "ae2289b93f8631f328e44e603a17bfe3df90f459", "4ce3e99a336b74611349595ea7fd5ed0277c3eeb" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Nov 08 21:34:42 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 08 21:34:42 2021 +0100" }, "message": "Merge \"fix: libc: use long for 64-bit types on aarch64\" into integration" }, { "commit": "51d8d1e326e39c83e49a0f4c4c269db74fcda226", "tree": "954883bd08e3d2a4a1df3ecced14ce0fa725e4c0", "parents": [ "683bb4d7bdfd42e6e026902c43797f132b2a75d5" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Mon Nov 08 10:36:53 2021 -0600" }, "committer": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Mon Nov 08 10:43:40 2021 -0600" }, "message": "Changing SMC code for transitioning Granule\n\nChanging the SMC code value to conform with RMM for\ntransitioning a realm granule back to non-secure,\notherwise known as undelegate.\n\nSigned-off-by: Mark Dykes \u003cmark.dykes@arm.com\u003e\nChange-Id: Ia45ad6cab538de48c65b071b49e504be234afa2b\n" }, { "commit": "ae2289b93f8631f328e44e603a17bfe3df90f459", "tree": "793738bd0edce7b9d7b852cfc9e0caa6aff7ffc0", "parents": [ "0b5e33c7aa6cf5723f68a2b6170b155832c965d1", "195381a91313bc0bce2cfa087f3c55136a9e8496" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Nov 08 16:52:43 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 08 16:52:43 2021 +0100" }, "message": "Merge \"fix(arm_fpga): Change PL011 UART IRQ\" into integration" }, { "commit": "4ce3e99a336b74611349595ea7fd5ed0277c3eeb", "tree": "da86b310c5d589ce2a0a4cb93e0ab88af5818c2d", "parents": [ "663461b9144e21b3fb0de92c886b63254964429a" ], "author": { "name": "Scott Branden", "email": "scott.branden@broadcom.com", "time": "Tue Aug 25 13:49:32 2020 -0700" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Nov 08 14:41:17 2021 +0000" }, "message": "fix: libc: use long for 64-bit types on aarch64\n\nUse long instead of long long on aarch64 for 64_t stdint types.\nIntroduce inttypes.h to properly support printf format specifiers for\nfixed width types for such change.\n\nChange-Id: I0bca594687a996fde0a9702d7a383055b99f10a1\nSigned-off-by: Scott Branden \u003cscott.branden@broadcom.com\u003e\n" }, { "commit": "0b5e33c7aa6cf5723f68a2b6170b155832c965d1", "tree": "efcbed23ee8532247732888c15bb6bc7f1d7732b", "parents": [ "683bb4d7bdfd42e6e026902c43797f132b2a75d5", "4c8fe6b17fa994a630b2a30f8666df103f2e370d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Nov 08 15:28:19 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Nov 08 15:28:19 2021 +0100" }, "message": "Merge changes Ic2f90d79,Ieca02425,I615bcc1f,I6a9cb4a2,I5247f8f8, ... into integration\n\n* changes:\n fix(errata): workaround for Neoverse V1 erratum 2216392\n fix(errata): workaround for Cortex A78 erratum 2242635\n fix(errata): workaround for Neoverse-N2 erratum 2280757\n fix(errata): workaround for Neoverse-N2 erratum 2242400\n fix(errata): workaround for Neoverse-N2 erratum 2138958\n fix(errata): workaround for Neoverse-N2 erratum 2242415\n" }, { "commit": "a125c556230501ee0f5ec9f8b0b721625d484a41", "tree": "f40ef517f982636517ff1c38b5bffe6825c19f53", "parents": [ "663461b9144e21b3fb0de92c886b63254964429a" ], "author": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Mon Jul 05 12:04:22 2021 +0100" }, "committer": { "name": "Javier Almansa Sobrino", "email": "javier.almansasobrino@arm.com", "time": "Mon Nov 08 10:49:26 2021 +0000" }, "message": "feat(measured boot): add documentation to build and run PoC\n\nAdd documentation to build and run a PoC based on the OP-TEE toolkit\nto show how TF-A Measured Boot can interact with a third party (f)TPM\nservice.\n\nSigned-off-by: Javier Almansa Sobrino \u003cjavier.almansasobrino@arm.com\u003e\nChange-Id: I11ac99c4ff54ea52aba0731aa7f707d7cd0c4216\n" }, { "commit": "683bb4d7bdfd42e6e026902c43797f132b2a75d5", "tree": "6c42c87e6f69c19b53e3219db5e56f26d1df2415", "parents": [ "25d7dafb2c61b682dcb77a74baed2ae50f056910", "422b44fb56db7ca8b1a2f9f706733d7d4c2fdeb1" ], "author": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Sat Nov 06 02:32:00 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Nov 06 02:32:00 2021 +0100" }, "message": "Merge changes from topic \"arm_fpga_auto\" into integration\n\n* changes:\n feat(arm_fpga): write UART baud base clock frequency into DTB\n feat(arm_fpga): query PL011 to learn system frequency\n refactor(arm_fpga): move command line code into separate function\n fix(fdt): avoid output on missing DT property\n feat(arm_fpga): add ITS autodetection\n feat(arm_fpga): determine GICR base by probing\n feat(gicv3): introduce GIC component identification\n feat(libfdt): also allow changing base address\n fix(arm_fpga): avoid re-linking from executable ELF file\n" }, { "commit": "4c8fe6b17fa994a630b2a30f8666df103f2e370d", "tree": "307ac1b3140e21367b9f945925f93e2d96e34114", "parents": [ "1ea9190c6a4d2299c6dc19adc0bbe93d4f051eff" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Thu Sep 02 18:29:17 2021 -0500" }, "committer": { "name": "John", "email": "john.powell@arm.com", "time": "Fri Nov 05 23:10:58 2021 +0100" }, "message": "fix(errata): workaround for Neoverse V1 erratum 2216392\n\nNeoverse V1 erratum 2216392 is a Cat B erratum present in the V1 core.\nIt applies to revisions r1p0 and r1p1 and is still open. The issue is\nalso present in r0p0 but there is no workaround in that revision.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1401781\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Ic2f90d79c75e8ffef01aac81eddf1bfd8b7164ab\n" }, { "commit": "25d7dafb2c61b682dcb77a74baed2ae50f056910", "tree": "5a8e456d80bc7ee972aa080476a949160f1eb9ec", "parents": [ "164e1cdafec152510ac76efebc3c3aeee021c677", "a19bd32ed14c33571f3715198d47bac9d0f2808e" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri Nov 05 21:09:38 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 05 21:09:38 2021 +0100" }, "message": "Merge \"feat(tc0): add Ivy partition\" into integration" }, { "commit": "1ea9190c6a4d2299c6dc19adc0bbe93d4f051eff", "tree": "92a2cc63fa5311d153f5a1333d68afc68208b12c", "parents": [ "0d2d99924e1be548e75c46cfd536f7503cf863e0" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Thu Sep 02 17:53:30 2021 -0500" }, "committer": { "name": "John", "email": "john.powell@arm.com", "time": "Fri Nov 05 20:52:41 2021 +0200" }, "message": "fix(errata): workaround for Cortex A78 erratum 2242635\n\nCortex A78 erratum 2242635 is a Cat B erratum present in the A78 Core.\nIt applies to revisions r1p0, r1p1, r1p2, and is still open. The issue\nis also present in r0p0 but there is no workaround for this revision.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1401784\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Ieca024254cabbc683ff13a70f3aeb8f2f3c5ce07\n" }, { "commit": "164e1cdafec152510ac76efebc3c3aeee021c677", "tree": "a533d3cb406d436698680d91ac64d49f6da6546f", "parents": [ "1330adffc3c42a8e6efcdd075e698bdebf390500", "325376eb818b95ade63a58476cf2e75c00578aa0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Nov 05 18:33:39 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 05 18:33:39 2021 +0100" }, "message": "Merge \"refactor(stm32mp1): use fconf.mk\" into integration" }, { "commit": "1330adffc3c42a8e6efcdd075e698bdebf390500", "tree": "5eb4ed3b790d29420047b90554aaef4c0f9cea87", "parents": [ "80d00095b711136bc3376b90ea3cf36bfe52c574", "96b71eb9597efbf4857216cac1caeefc9e8bbf3e" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Nov 05 18:24:15 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 05 18:24:15 2021 +0100" }, "message": "Merge \"feat(ff-a): feature retrieval through FFA_FEATURES call\" into integration" }, { "commit": "96b71eb9597efbf4857216cac1caeefc9e8bbf3e", "tree": "d69654394d13972c9bdccee4ddc63926eb11a22f", "parents": [ "e33ca7b44a6c40ec4fb245baef4889cee30a73c9" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Nov 01 16:52:46 2021 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Nov 05 16:44:31 2021 +0000" }, "message": "feat(ff-a): feature retrieval through FFA_FEATURES call\n\nUpdated FFA_FEATURES according to FF-A v1.1 in SPMC can also be used\nto retrieve feature information, and should now accept other arguments\nthan just FF-A call IDs.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I02cc24a31ab3092ec1ce6fed1a9649ffe7136782\n" }, { "commit": "80d00095b711136bc3376b90ea3cf36bfe52c574", "tree": "d86b56e9a79fb2f1f6fda904bf68cfd17ac61f8c", "parents": [ "dcb40592b15b8d9145de79c1c0c0d053fbdccf21", "7ca49284be083b03ae11aa348b40358876ee5d4b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Nov 05 15:56:08 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 05 15:56:08 2021 +0100" }, "message": "Merge changes from topic \"st_usb\" into integration\n\n* changes:\n fix(drivers/usb): remove deadcode when USBD_EP_NB \u003d 1\n fix(drivers/usb): fix Null pointer dereferences in usb_core_set_config\n" }, { "commit": "dcb40592b15b8d9145de79c1c0c0d053fbdccf21", "tree": "f09cc2a6555f814952d58600dfe9567cc58656f3", "parents": [ "48382bbc2fb6e58033e74044e0a0fcb5560a7612", "8d26029168fe70a86de524ed68c56e8666823714" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Nov 05 14:36:52 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 05 14:36:52 2021 +0100" }, "message": "Merge \"fix(fdts stm32mp1): correct copyright dates\" into integration" }, { "commit": "325376eb818b95ade63a58476cf2e75c00578aa0", "tree": "5d3aba7ef48d1625931f6cc1deb18e24b3587d49", "parents": [ "48382bbc2fb6e58033e74044e0a0fcb5560a7612" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Oct 29 17:04:17 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Nov 05 13:32:32 2021 +0100" }, "message": "refactor(stm32mp1): use fconf.mk\n\nUpdate STM32MP1 platform.mk file to include fconf.mk.\n\nChange-Id: Idc623a832b4cdf9486835fc612803015f4f1a5f5\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "8d26029168fe70a86de524ed68c56e8666823714", "tree": "f09cc2a6555f814952d58600dfe9567cc58656f3", "parents": [ "48382bbc2fb6e58033e74044e0a0fcb5560a7612" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Nov 02 15:06:01 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Nov 05 13:28:55 2021 +0100" }, "message": "fix(fdts stm32mp1): correct copyright dates\n\nAdd 2021 year in the file header Copyright line.\n\nChange-Id: I09f7bef1f746c429ff308286169354e58648a1cd\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "d39db2695ba626b9c0ee38652fe160b4e84b15d9", "tree": "643e2e32fd91d8ffd7b7218fb5e210262b9c5102", "parents": [ "663461b9144e21b3fb0de92c886b63254964429a" ], "author": { "name": "Ming Huang", "email": "huangming@linux.alibaba.com", "time": "Thu Sep 09 17:42:27 2021 +0800" }, "committer": { "name": "Ming Huang", "email": "huangming@linux.alibaba.com", "time": "Fri Nov 05 18:53:44 2021 +0800" }, "message": "fix(sdei): fix assert while kdump issue\n\nAssert condition:\n1 Register secure timer(ppi\u003d29) for sdei nmi watchdog;\n2 kernel panic and then kdump;\nWhile kdump, kernel mask all cores sdei, secure timer trigger\nand go to handle_masked_trigger() and assert here:\nassert(se-\u003eaffinity \u003d\u003d my_mpidr);\n\nAs kernel register with flag\u003d0, mpidr\u003d0 and TF-A set flag to\nSDEI_REGF_RM_PE but leave mpidr\u003d0. So set mpidr to fix his\nassert issue.\n\nSigned-off-by: Ming Huang \u003chuangming@linux.alibaba.com\u003e\nChange-Id: Ia9182f40bde94fb004b46e2a72b186eb0ef05166\n" }, { "commit": "48382bbc2fb6e58033e74044e0a0fcb5560a7612", "tree": "8ad40cb1a8063b037d0f3f20e5c876e68940132b", "parents": [ "08da187682fdefbec6f9793a3f2eb3b8d71ac72f", "f6f1b9b8c2b280e0423d07efe3a2bca3f854c9f8" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Nov 05 10:44:07 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 05 10:44:07 2021 +0100" }, "message": "Merge \"chore(docs): update supported FVP models doc\" into integration" }, { "commit": "08da187682fdefbec6f9793a3f2eb3b8d71ac72f", "tree": "18bcb51f66453a521bd8dcc921baf9e28afddc7a", "parents": [ "89ff55fef4b74beda62d04b01428f3e587a4fb4d", "77612b90acaffc82cea712f4a431c727bbb968ec" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Nov 05 10:35:56 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Nov 05 10:35:56 2021 +0100" }, "message": "Merge \"fix(gpt_rme): add necessary barriers and remove cache clean\" into integration" }, { "commit": "77612b90acaffc82cea712f4a431c727bbb968ec", "tree": "05577b194b98d7154c2381dbeddc80ac0528832d", "parents": [ "55eeb7b08f8ab9f5d9614e16a0c772342fd4713e" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Oct 11 14:38:46 2021 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Fri Nov 05 09:33:03 2021 +0000" }, "message": "fix(gpt_rme): add necessary barriers and remove cache clean\n\nThis patch adds necessary barriers after GPT entries are modified\nso that the writes are observed correctly by the GPC hardware.\nThe shareability of GPC fetches are changed from OSH to ISH so\nthat they align with the shareability of MMU attributes for the\nregion. Thus by adding a dsbishst() between the GPT L1 entry\nwrite as part of granule migration at runtime, we can now remove\nthe clean cache maintenance operation (CMO) for that region.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nSigned-off-by: Robert Wakim \u003crobert.wakim@arm.com\u003e\nChange-Id: Ib9e405b106f0db95c7fbdb26773c0ed41663a5b4\n" }, { "commit": "216c1223c2c65bd1c119a28b9406f70a9ee7b063", "tree": "59d5ed256d00ade4b3f2cd0cf37e64c892bd1ad9", "parents": [ "025f5ef201a39ba7285f368139e690bbd7a44653" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Thu Nov 04 15:13:33 2021 +0100" }, "committer": { "name": "Patrick DELAUNAY", "email": "patrick.delaunay@foss.st.com", "time": "Fri Nov 05 11:28:59 2021 +0200" }, "message": "fix(drivers/usb): add a optional ops get_other_speed_config_desc\n\nCorrectly handle USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION request\nin USB driver and support a different result than\nUSB_DESC_TYPE_CONFIGURATION with the new optional ops\nget_other_speed_config_desc().\n\nThe support of this descriptor is optionnal and is only\nrequired when high-speed capable device which can operate at its\nother possible speed.\n\nThis patch allows to remove the pbuf update in usb_core_get_desc()\nand solves an issue on USB re-enumeration on STM32MP15 platform\nas the result of get_config_desc() is a const array.\nThis issue is not see on normal use-case, as the USB enumeration\nis only done in ROM code and TF-A reuse the same USB descritors.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: I8edcc1e45065ab4e45d48f4bc37b49120674fdb0\n" }, { "commit": "025f5ef201a39ba7285f368139e690bbd7a44653", "tree": "64e050e58eb376f59afb3c29ea930add3919de94", "parents": [ "89ff55fef4b74beda62d04b01428f3e587a4fb4d" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Thu Nov 04 14:39:28 2021 +0100" }, "committer": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Fri Nov 05 10:22:44 2021 +0100" }, "message": "fix(drivers/usb): remove unnecessary cast\n\nRemove the unnecessary cast on the result of function which\nalready return the correct type.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: Ie21f7e78a880d30d1f31e32b3d2c3fb09489d65b\n" }, { "commit": "0d2d99924e1be548e75c46cfd536f7503cf863e0", "tree": "0acbfaf974cd8dd869ee687a35896306409c4b81", "parents": [ "603806d1376c4b18211fb1d4cc338153de026c32" ], "author": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Wed Oct 20 17:30:46 2021 -0700" }, "committer": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Thu Nov 04 13:01:13 2021 -0700" }, "message": "fix(errata): workaround for Neoverse-N2 erratum 2280757\n\nNeoverse-N2 erratum 2280757 is a Cat B erratum that applies to\nrevision r0p0 of CPU. It is still open. The workaround\nis to set CPUACTLR_EL1[22] to 1\u0027b1. Setting CPUACTLR_EL1[22]\nwill cause CFP instruction to invalidate all branch predictor\nresources regardless of context.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1982442/latest\n\nSigned-off-by: nayanpatel-arm \u003cnayankumar.patel@arm.com\u003e\nChange-Id: I615bcc1f993c45659b8b6f1a34fca0eb490f8add\n" }, { "commit": "603806d1376c4b18211fb1d4cc338153de026c32", "tree": "296a38e38a12cf1a83d9d44b26c711c6a96306ec", "parents": [ "c948185c973c13df36c62c4bcb50e22b14d6e06a" ], "author": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Thu Oct 07 17:59:33 2021 -0700" }, "committer": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Thu Nov 04 12:51:26 2021 -0700" }, "message": "fix(errata): workaround for Neoverse-N2 erratum 2242400\n\nNeoverse-N2 erratum 2242400 is a Cat B erratum that applies to\nrevision r0p0 of CPU. It is still open. The workaround\nis to set CPUACTLR5_EL1[17] to 1\u0027b1 followed by setting few\nsystem control registers to specific values as per attached\nSDEN document.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1982442/latest\n\nSigned-off-by: nayanpatel-arm \u003cnayankumar.patel@arm.com\u003e\nChange-Id: I6a9cb4a23238b8b511802a1ee9fcc5b207137649\n" }, { "commit": "c948185c973c13df36c62c4bcb50e22b14d6e06a", "tree": "cf7854ffdf7ec1dcfb16d8efda3d3f467c1a8ed6", "parents": [ "5819e23bc47c860872141caf42bddddb1b8679a5" ], "author": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Wed Oct 20 18:28:58 2021 -0700" }, "committer": { "name": "nayankumar.patel", "email": "nayankumar.patel@arm.com", "time": "Thu Nov 04 20:30:19 2021 +0100" }, "message": "fix(errata): workaround for Neoverse-N2 erratum 2138958\n\nNeoverse-N2 erratum 2138958 is a Cat B erratum that applies to\nrevision r0p0 of CPU. It is still open. The workaround\nis to set CPUACTLR5_EL1[13] to 1\u0027b1.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1982442/latest\n\nSigned-off-by: nayanpatel-arm \u003cnayankumar.patel@arm.com\u003e\nChange-Id: I5247f8f8eef08d38c169aad6d2c5501ac387c720\n" }, { "commit": "5819e23bc47c860872141caf42bddddb1b8679a5", "tree": "31d3ab806fe8fd956cd95cfa37c34f4ec2e66811", "parents": [ "663461b9144e21b3fb0de92c886b63254964429a" ], "author": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Wed Oct 06 15:31:24 2021 -0700" }, "committer": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Thu Nov 04 12:13:22 2021 -0700" }, "message": "fix(errata): workaround for Neoverse-N2 erratum 2242415\n\nNeoverse-N2 erratum 2242415 is a Cat B erratum that applies to\nrevision r0p0 of CPU. It is still open. The workaround\nis to set CPUACTLR_EL1[22] to 1\u0027b1. Setting CPUACTLR_EL1[22]\nwill cause CFP instruction to invalidate all branch predictor\nresources regardless of context.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1982442/latest\n\nSigned-off-by: nayanpatel-arm \u003cnayankumar.patel@arm.com\u003e\nChange-Id: I442be81fbc32e21fed51a84f59584df17f845e96\n" }, { "commit": "195381a91313bc0bce2cfa087f3c55136a9e8496", "tree": "4374c214378c40e6952b2e8aa26889d5b1d2c94f", "parents": [ "663461b9144e21b3fb0de92c886b63254964429a" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Fri May 14 16:13:55 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Nov 04 17:06:36 2021 +0000" }, "message": "fix(arm_fpga): Change PL011 UART IRQ\n\nAbout a year ago there was a change in the underlying Arm platform design\nframework, which lead to a reorganisation of the interrupt map (to make\nroom for multi-chip designs).\n\nThis lead to the PL011 debug UART interrupt to move from SPI 115 to SPI\n415. Unfortunately there is not a good or easy way to auto-detect this\nchange: Flooding the TX FIFO and checking GICD_ISPENDR registers might\nbe possible, but sounds a bit over the top for BL31.\n\nSo we would need to break one group of images: newer ones, as we do right\nnow, or older ones.\nBy now every interesting FPGA image seems to use the newer IRQ, so in\nthe interest of having a smooth experience for most users, lets switch\nto this IRQ.\n\nWhen people are interested in older images, they can either change the\nnumber back in the .dts file, or provide a patched DTB on the FPGA\ncommand line.\n\nChange-Id: I3c7e7b711f5142813bd94eecde3095a4fc555bb3\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "422b44fb56db7ca8b1a2f9f706733d7d4c2fdeb1", "tree": "678ecd9034a3f3153a2866ca7a7e4e939c186ee9", "parents": [ "d850169c9c233c4bc413d8319196557b54683688" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Sep 01 11:59:57 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Nov 04 15:58:34 2021 +0000" }, "message": "feat(arm_fpga): write UART baud base clock frequency into DTB\n\nSince we now autodetect the actual system frequency, which is also used\nas the base for the UART baudrate generation, we should update the value\ncurrently hard-coded in the DT. Otherwise Linux will reprogram the\ndivider using a potentially wrong base rate, which breaks the UART\noutput.\n\nFind the DT node referenced by the UART node as the clock rate, and set\nthe \"clock-frequency\" property in that node to the detected system\nfrequency. This will let Linux reprogram the divider to the same value,\npreserving the actual baudrate.\n\nChange-Id: Ib5a936849f2198577b86509f032751d5386ed2f8\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "d850169c9c233c4bc413d8319196557b54683688", "tree": "48d48377c7bf4abc5055c3f30c4d8219a589f539", "parents": [ "52b8f4465e48165695440e730039b2a99517b4b7" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Sep 01 11:59:08 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Nov 04 15:58:34 2021 +0000" }, "message": "feat(arm_fpga): query PL011 to learn system frequency\n\nThe Arm FPGAs run in mostly one clock domain, which is used for the CPU\ncores, the generic timer, and also the UART baudrate base clock. This\nsingle clock can have different rates, to compensate for different IP\ncomplexity. So far most images used 10 MHz, but different rates start to\nappear.\n\nTo avoid patching both the arch timer frequency and UART baud base fixed\nclock in the DTB manually, we would like to set the clock rate\nautomatically. Fortunately the SCP firmware has the actual clock rate\nhard coded, and already programs the PL011 UART baud divider register\nwith the correct value to achieve a 38400 bps baudrate.\n\nSo read the two PL011 baudrate divider values and re-calculate the\noriginal base clock from there, to use as the arch timer frequency. If\nthe arch timer DT node contains a clock-frequency property, we use that\ninstead, to support overriding and disabling this autodetection.\n\nChange-Id: I9857fbb418deb4644aeb2816f1102796f9bfd3bb\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "52b8f4465e48165695440e730039b2a99517b4b7", "tree": "e74b7d3b85bd22a17ec6d8b673db1bf7ab69f514", "parents": [ "49e789e353efaf97f84eca016c6a1b8a2b3e3d98" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Sep 01 11:54:30 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Nov 04 15:58:34 2021 +0000" }, "message": "refactor(arm_fpga): move command line code into separate function\n\nThe code dealing with finding the command line and inserting that into\nthe DTB is somewhat large, and drowns the other DT handlers in our\nfpga_prepare_dtb() function.\n\nMove that code into a separate function, to improve readability.\n\nChange-Id: I828203c4bb248d38a2562fcb6afdefedf3179f8d\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "49e789e353efaf97f84eca016c6a1b8a2b3e3d98", "tree": "eaec198c224c67d1d72dce770fbfdb4029e2eb36", "parents": [ "d7e39c43f2f58aabb085ed7b8f461f9ece6002d0" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Sep 02 17:00:06 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Nov 04 15:58:34 2021 +0000" }, "message": "fix(fdt): avoid output on missing DT property\n\nWhen we use our fdt_read_uint32* helper functions, we output a warning\non not finding the requested property.\n\nHowever non-existing properties are not that uncommon, and *trying* to\nread such a property is actually a nice way of checking its existence.\n\nSince we already return a specific error value in this case, the caller\ncan easily check this and give a more specific error message, if needed.\nWhen the caller decides to properly handle the error (fallback, default\nvalue, etc), a message on the console is quite misleading.\n\nDemote the message to a VERBOSE, so normal builds will not spam the\nconsole with pointless messages.\n\nChange-Id: I7a279a4ee0147c5f4a0503d0a8745c6cfea58be5\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "d7e39c43f2f58aabb085ed7b8f461f9ece6002d0", "tree": "e66cd1918e11c8d12212ef15b6ccdceec39d90f5", "parents": [ "93b785f5ae66a6418581c304c83a346e8baa5aa3" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Jul 20 20:05:38 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Nov 04 15:58:34 2021 +0000" }, "message": "feat(arm_fpga): add ITS autodetection\n\nSome FPGAs come with a GIC that has an ITS block configured. Since the\nITS sits between the distributor and redistributors, we can autodetect\nthat, and already adjust the GICR base address.\n\nTo also make this ITS usable, add an ITS node to our base DTB, and\nremove that should we not find an ITS during the scan for the\nredistributor. This allows to use the same TF-A binary for FPGA images\nwith or without an ITS.\n\nChange-Id: I4c0417dec7bccdbad8cbca26fa2634950fc50a66\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "93b785f5ae66a6418581c304c83a346e8baa5aa3", "tree": "3b3c253dd7e470fd64ed22b2a5721e49795f015f", "parents": [ "73a643eed9d88910a09ca666bc7ab7f5e532324e" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed May 19 09:40:01 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Nov 04 15:58:34 2021 +0000" }, "message": "feat(arm_fpga): determine GICR base by probing\n\nWhen an Arm Ltd GIC (Arm GIC-[567]00) is instantiated with one or more\nITSes, the ITS MMIO frames appear between the distributor and\nredistributor addresses. This makes the beginning of the redistributor\nregion dependent on the existence and number of ITSes.\n\nTo support various FPGA images, with and without ITSes, probe the\naddresses in question, to learn whether they accommodate an ITS or a\nredistributor. This can be safely done by looking at the PIDR[01]\nregisters, which contain an ID code for each region, documented in the\nArm GIC TRMs.\n\nWe try to find all ITSes instantiated, and skip either two or four 64K\nframes, depending on GICv4.1 support. At some point we will find the\nfirst redistributor; this address we then update in the DTB.\n\nChange-Id: Iefb88c2afa989e044fe0b36b7020b56538c60b07\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "73a643eed9d88910a09ca666bc7ab7f5e532324e", "tree": "0349da21589d42c5ae60c3bc33d1596a180fd223", "parents": [ "4d585fe52feb231d5e73ec50a505122d5e9bf450" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Aug 24 10:03:57 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Nov 04 15:58:34 2021 +0000" }, "message": "feat(gicv3): introduce GIC component identification\n\nThe GIC specification describes ID registers in each GIC register frame\n(PIDRx), which can be used to identify a GIC component. The Arm Ltd. GIC\nimplementations use certain ID values to identify the distributor, the\nredistributors and other parts like ITSes.\n\nIntroduce a function that reads those part number IDs, which are spread\nover two registers. The actual numbers are only meaningful in connection\nwith a certain GIC model, which would need to be checked beforehand, by\nthe caller.\n\nChange-Id: Ia6ff326a1e8b12664e4637bc8e2683d2b5c7721c\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "4d585fe52feb231d5e73ec50a505122d5e9bf450", "tree": "8e4a83c5090d6c51487e6f9672c7e45a1d553ad2", "parents": [ "a67ac7648cd814ed8f8d4ece1b265c6d48c6dc81" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed May 19 09:37:21 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Nov 04 15:58:34 2021 +0000" }, "message": "feat(libfdt): also allow changing base address\n\nFor platforms where we don\u0027t know the number of cores at compile time,\nthe size of the GIC redistributor frame is then also undetermined, since\nit depends on this number of cores.\nOn top of this the GICR base address can also change, when an unknown\nnumber of ITS frames (including zero) take up space between the\ndistributor and redistributor.\n\nSo while those two adjustments are done for independent reasons, the\ncode for doing so is very similar, so we should utilise the existing\nfdt_adjust_gic_redist() function.\n\nAdd an (optional) gicr_base parameters to the prototype, so callers can\nchoose to also adjust this base address later, if needed.\n\nChange-Id: Id39c0ba83e7401fdff1944e86950bb7121f210e8\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "a67ac7648cd814ed8f8d4ece1b265c6d48c6dc81", "tree": "ac95fa6660508dc0128fc15c6332f9dada3fb371", "parents": [ "663461b9144e21b3fb0de92c886b63254964429a" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Nov 04 13:47:17 2021 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Nov 04 15:58:34 2021 +0000" }, "message": "fix(arm_fpga): avoid re-linking from executable ELF file\n\nWhen we build the convenience firmware package file for the Arm FPGA\nboards (bl31.axf), we combine trampolines, the DTB and the actual BL31\ncode into one ELF file, which is more a \"container with load addresses\"\nthan an actual executable. So far ld was fine with us using bl31.elf as\nan input file, but binutils 2.35 changed that and complains about\ntaking an *executable* ELF file as in *input* to the linker:\n-----------------\naarch64-none-elf-ld.bfd: cannot use executable file \u0027build/arm_fpga/debug/./bl31/bl31.elf\u0027 as input to a link\n-----------------\n\nFortunately we don\u0027t need the actual BL31 ELF file for *that* part of\nthe linking, so can use the just created bl31.bin binary version of it.\nActually that shrinks the file, as we needlessly included the .BSS\nsection in the final file before.\n\nUsing the binary works with both older and newer toolchains versions, so\nlet\u0027s do this unconditionally.\n\nChange-Id: Ib7e697f8363499123f7cb860f118f182d0830768\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "f6f1b9b8c2b280e0423d07efe3a2bca3f854c9f8", "tree": "16cc5bbeb0a714f00c2dba9ed7577c0a87ce29a3", "parents": [ "89ff55fef4b74beda62d04b01428f3e587a4fb4d" ], "author": { "name": "Maksims Svecovs", "email": "maksims.svecovs@arm.com", "time": "Mon Oct 25 16:13:42 2021 +0100" }, "committer": { "name": "Maksims Svecovs", "email": "maksims.svecovs@arm.com", "time": "Thu Nov 04 11:34:17 2021 +0100" }, "message": "chore(docs): update supported FVP models doc\n\nUpdate supported models list according to changes for v2.6 release in\nci/tf-a-ci-scripts repository:\n* general FVP model update: d10c1b9\n* gic600 update: aa2548a\n* CSS prebults model update: f1c3a4f\n\nSigned-off-by: Maksims Svecovs \u003cmaksims.svecovs@arm.com\u003e\nChange-Id: If2841f05238facb3cace7d5c8a78083d54f35e27\n" }, { "commit": "7ca49284be083b03ae11aa348b40358876ee5d4b", "tree": "97803ad7730b853d6a7dab19e3cf6c9d120e1f48", "parents": [ "0cb9870ddfa1b2fec50debe6d6333cbcb3df1e7e" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Tue Nov 02 13:14:45 2021 +0100" }, "committer": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Thu Nov 04 09:49:30 2021 +0100" }, "message": "fix(drivers/usb): remove deadcode when USBD_EP_NB \u003d 1\n\nCID 373791: Control flow issues (DEADCODE)\nCID 373789: Control flow issues (DEADCODE)\n\nSince USBD_EP_NB \u003d 1 for DFU stack on STMP32MP15 platform (only EP0 is\nrequired for DFU support) the value of num can\u0027t be different of 0\nand the code can\u0027t be reached in usb_core_receive / usb_core_transmit.\n\nAdd a simple sub-function with this part of code.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: I07a56909bb1e6de19ce52da7945b6d2916be8538\n" }, { "commit": "0cb9870ddfa1b2fec50debe6d6333cbcb3df1e7e", "tree": "63cc9b1468ace1e0fd420838dcf2159ac4fa74a5", "parents": [ "89ff55fef4b74beda62d04b01428f3e587a4fb4d" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Tue Nov 02 11:09:12 2021 +0100" }, "committer": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Thu Nov 04 09:48:44 2021 +0100" }, "message": "fix(drivers/usb): fix Null pointer dereferences in usb_core_set_config\n\nCorrect the invalid test on NULL pointer pdev-\u003eclass in\nusb_core_set_config function.\n\nThis patch fix the coverity errors:\n\n ** CID 373790: Null pointer dereferences (FORWARD_NULL)\n /drivers/usb/usb_device.c: 182 in usb_core_set_config()\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: I83e43261bafa2d47f800e56df0b047a6c58a1e29\n" }, { "commit": "8cb99c3fc3539bb9926e73a1c33fd72f424fc453", "tree": "8cee238231486fc6db58e8ed8e75e58f487eb780", "parents": [ "663461b9144e21b3fb0de92c886b63254964429a" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Aug 05 11:27:42 2020 +0200" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Nov 03 15:42:21 2021 -0500" }, "message": "feat(SPMD): route secure interrupts to SPMC\n\nDefine a handler in the SPMD to route secure interrupts occurring while\nthe normal world runs. On a Group1 Secure interrupt (with a GICv3 or a\nGroup0 interrupt on GICv2), the normal world is pre-empted to EL3 and\nredirected to the SPMD/SPMC for further handling.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: I1350d74048c5549a2af8da0ba004c08512cc006a\n" }, { "commit": "89ff55fef4b74beda62d04b01428f3e587a4fb4d", "tree": "8e5bd4b76c2555d190508db3d3b632eaacbb46c8", "parents": [ "663461b9144e21b3fb0de92c886b63254964429a", "306dcd6b0d1981b75e103c560a4034bdaa6862d5" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Nov 03 19:38:00 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 03 19:38:00 2021 +0100" }, "message": "Merge changes from topic \"fix_checkpatch_merges\" into integration\n\n* changes:\n fix(plat/st): remove double space\n fix(checkpatch): do not check merge commits\n" }, { "commit": "a19bd32ed14c33571f3715198d47bac9d0f2808e", "tree": "4418a4bd3573bbe5bf8d6d41c8eaa773c8b43836", "parents": [ "e33ca7b44a6c40ec4fb245baef4889cee30a73c9" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Sep 28 15:35:39 2021 +0200" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Nov 03 10:47:09 2021 -0500" }, "message": "feat(tc0): add Ivy partition\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\nChange-Id: Ie9d6a77722b2350c8479ecf7b0df701428e4da73\n" }, { "commit": "663461b9144e21b3fb0de92c886b63254964429a", "tree": "37ce29c13bb2110f46036159a74e1e23d33b2fae", "parents": [ "ed0722fe17aac96536b4525ea1a1ad9a6c7ce542", "403f4cb3e744b3893195e69af176cb3b4c113248" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Nov 03 12:52:24 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Nov 03 12:52:24 2021 +0100" }, "message": "Merge \"docs(gcc): update GCC to version 10.3-2021.07\" into integration" }, { "commit": "306dcd6b0d1981b75e103c560a4034bdaa6862d5", "tree": "5b0fd7a0d8c87de1f19e5cb573b3e17e52751941", "parents": [ "77a0a7f1d96b188849d1d8d8884b3c93857d3f69" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Nov 02 17:03:46 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Nov 03 08:50:37 2021 +0100" }, "message": "fix(plat/st): remove double space\n\nReplace double space with single space in stm32cubeprogrammer_usb.c.\n\nChange-Id: I717b136119e85fe8e25dd540758525f995200458\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "77a0a7f1d96b188849d1d8d8884b3c93857d3f69", "tree": "00b4e13223cedb212bdcdde0fb373ba7f0f0aee2", "parents": [ "ed0722fe17aac96536b4525ea1a1ad9a6c7ce542" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Nov 02 18:03:31 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Nov 02 18:15:59 2021 +0100" }, "message": "fix(checkpatch): do not check merge commits\n\nAdd the --no-merges option when listing patches to check with rev-list\ncommand, when running make checkpatch.\n\nChange-Id: I47f3f5dfe358ed2b960a754f70aec0dc3c2b4536\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "ed0722fe17aac96536b4525ea1a1ad9a6c7ce542", "tree": "f4c580ce4840ca6889d91195059a6eb98b88cc33", "parents": [ "4fcbbb33c31ddf4461e6b557f8aec1a72411ac10", "2062a3936f209c31ace73705754a3442305a577d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Nov 02 14:44:29 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Nov 02 14:44:29 2021 +0100" }, "message": "Merge \"fix(amu): remove `amu_fconf.c`\" into integration" }, { "commit": "2062a3936f209c31ace73705754a3442305a577d", "tree": "f4c580ce4840ca6889d91195059a6eb98b88cc33", "parents": [ "4fcbbb33c31ddf4461e6b557f8aec1a72411ac10" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Mon Nov 01 11:11:45 2021 +0000" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Mon Nov 01 11:13:24 2021 +0000" }, "message": "fix(amu): remove `amu_fconf.c`\n\nThis file is unused and was introduced accidentally by one of the\ncommits in the MPMM patch stack. This functionality was instead\nintroduced by `fconf_amu_getter.c`.\n\nChange-Id: Ib15b1114bacf9a2e7414c1fb35bd4fbdf0179210\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "4fcbbb33c31ddf4461e6b557f8aec1a72411ac10", "tree": "036e995ef44e9907646bac541c46e6cafe4ac91f", "parents": [ "6482255d5df64d7b128d8804ae4e9cb57d563215", "fa92fef0a024cdb537fe56c84a0156cc48c1ac2d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Oct 29 23:47:56 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 29 23:47:56 2021 +0200" }, "message": "Merge changes from topic \"st_usb\" into integration\n\n* changes:\n feat(plat/st/stm32mp1): add STM32MP_USB_PROGRAMMER target\n feat(plat/st/stm32mp1): add USB DFU support for STM32MP1\n feat(plat/st): add STM32CubeProgrammer support on USB\n feat(drivers/st/usb): add device driver for STM32MP1\n feat(plat/st): add a USB DFU stack\n feat(drivers/usb): add a USB device stack\n" }, { "commit": "6482255d5df64d7b128d8804ae4e9cb57d563215", "tree": "267e485ef851d6199d9a417ae78b218055dde208", "parents": [ "fea7f36938361ea33c02de0a78c4f1716c8a01d1", "88c227374c065e67bbd7d4a778a806a4c099aab5" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 29 18:48:52 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 29 18:48:52 2021 +0200" }, "message": "Merge \"refactor(fvp_r): remove unused files and clean up makefiles\" into integration" }, { "commit": "fea7f36938361ea33c02de0a78c4f1716c8a01d1", "tree": "a22ddaf5f80173b0eb9aa50cd6a7c1168ed487c8", "parents": [ "e33ca7b44a6c40ec4fb245baef4889cee30a73c9", "cdbbb9f7ecd4687fa52e1c655b631377c24862b9" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 29 18:11:23 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 29 18:11:23 2021 +0200" }, "message": "Merge changes from topic \"st_dt_update\" into integration\n\n* changes:\n fix(fdts stm32mp1): update PLL nodes for ED1/EV1 boards\n fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards\n feat(fdts stm32mp1): delete nodes for non-used boot devices\n fix(fdts stm32mp1): use \u0027kHz\u0027 as kilohertz abbreviation\n refactor(fdts stm32mp1): move STM32MP DDR node\n feat(fdts stm32mp1): align DT with latest kernel\n" }, { "commit": "fa92fef0a024cdb537fe56c84a0156cc48c1ac2d", "tree": "9445fa6d4828744e89b6b03ed9b281feff70c238", "parents": [ "942f6be211d4816ad2568d30d807b8fd53d7f981" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Tue Jul 06 14:07:56 2021 +0200" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 29 16:44:03 2021 +0200" }, "message": "feat(plat/st/stm32mp1): add STM32MP_USB_PROGRAMMER target\n\nAdd a support of USB as serial boot devices for STM32MP15x platform:\nthe FIP file is provide by STM32CubeProgrammer with the DFU protocol,\nloaded in DDR at DWL_BUFFER_BASE address and then the io memmap is used.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: I272c17c458ff1e9d0780f8fa22330c8a35533d19\n" }, { "commit": "942f6be211d4816ad2568d30d807b8fd53d7f981", "tree": "8cd4885bbb6ee19adddad9202b362c04262166b4", "parents": [ "afad5214a79259f56bc2003b00859abfe8a18d4d" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Wed Jun 30 17:06:19 2021 +0200" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 29 16:43:57 2021 +0200" }, "message": "feat(plat/st/stm32mp1): add USB DFU support for STM32MP1\n\nAdd the USB descriptor, the struct used for USB enumeration with\nthe function usb_dfu_plat_init().\n\nThe USB support is based on the usb lib and on the stm32mp1 usb driver.\n\nThe content of enumeration (the string descriptor) is identical to\nROM code to avoid the USB reset en re-enumeration needs.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: I18b40649e8df83813a5a340b0eee44c9a3470e43\n" }, { "commit": "afad5214a79259f56bc2003b00859abfe8a18d4d", "tree": "aeb040959b145b39cbab610b44b671ca0ea07a5d", "parents": [ "9a138eb5f29f6747e181a1b3b4199ad57721a3e0" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@st.com", "time": "Mon Sep 14 11:13:34 2020 +0200" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 29 16:43:49 2021 +0200" }, "message": "feat(plat/st): add STM32CubeProgrammer support on USB\n\nAdd a file to support over USB the STMicroelectronics tool\nSTM32CubeProgrammer in BL2 for STM32MP15x platform.\n\nThis tools is based on DFU stack.\n\nChange-Id: I48a8f772cb0e9b8be24c06847f724f0470c0f917\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\n" }, { "commit": "9a138eb5f29f6747e181a1b3b4199ad57721a3e0", "tree": "9a3213884d33b5d64a32d702561926e21673a8d8", "parents": [ "efbd65fa7b5cf70f20d6b18152741ccdf8a65bb6" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@st.com", "time": "Mon Sep 14 09:47:44 2020 +0200" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 29 16:43:43 2021 +0200" }, "message": "feat(drivers/st/usb): add device driver for STM32MP1\n\nAdd a device driver for Synopsis DWC2 USB IP of STM32MP15x,\nthis USB OTG device is only supported in device mode.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: I90b21f094f6637b85f3ace23a3a3a2f6fd4e0951\n" }, { "commit": "efbd65fa7b5cf70f20d6b18152741ccdf8a65bb6", "tree": "05de1e4a1ef2b0f5a1a7a0a49c011b3c0bbb2d67", "parents": [ "859bfd8d42341c6dea2b193db79dc4828e074ad7" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@st.com", "time": "Mon Sep 14 09:38:16 2020 +0200" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 29 16:43:36 2021 +0200" }, "message": "feat(plat/st): add a USB DFU stack\n\nAdd a stack to support the Universal Serial Bus Device Class\nSpecification for Device Firmware Upgrade (USB DFU v1.1).\n\nThis stack is based on the USB device stack (USBD).\n\nChange-Id: I8a56411d184882b6a9e3617c6dfb859086b8f353\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\n" }, { "commit": "859bfd8d42341c6dea2b193db79dc4828e074ad7", "tree": "32917dac036cb696631fe0fd412535d1112a018a", "parents": [ "e33ca7b44a6c40ec4fb245baef4889cee30a73c9" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@st.com", "time": "Fri Sep 04 18:20:51 2020 +0200" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 29 16:43:28 2021 +0200" }, "message": "feat(drivers/usb): add a USB device stack\n\nAdd a new USB framework to manage an USB device profile (USBD)\nbased on a peripheral controller driver (PCD).\n\nThis USB stack can be use to implement any Universal Serial Bus Device\nClass in TF-A on top of a USB driver defined in the platform.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: I7971ec6d952edec3511157a198e6e5359df4346b\n" }, { "commit": "88c227374c065e67bbd7d4a778a806a4c099aab5", "tree": "78ac19c0d64a70459b4bfe2731890171327d8c26", "parents": [ "3deb0600151b929fdd61e4fc764c99bdb9268f22" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Mon Oct 11 14:51:11 2021 -0500" }, "committer": { "name": "Gary Morrison", "email": "gary.morrison@arm.com", "time": "Fri Oct 29 09:43:19 2021 -0500" }, "message": "refactor(fvp_r): remove unused files and clean up makefiles\n\nThis patch removes files that are not used by TF-R as well as\nremoves unused generic files from the TF-R makefile.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Idb15ac295dc77fd38735bf2844efdb73e6f7c89b\n" }, { "commit": "e33ca7b44a6c40ec4fb245baef4889cee30a73c9", "tree": "eeff172f219c491cfcd2ee278f51c5b9315c7875", "parents": [ "7ab83390649a5b9eaf760b83c15ab9d4f501a422", "b15f7e2c509d45a68b08f5088736ed444a33791f" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Oct 29 14:45:28 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Oct 29 14:45:28 2021 +0200" }, "message": "Merge changes from topic \"ck/mpmm\" into integration\n\n* changes:\n docs(maintainers): add Chris Kay to AMU and MPMM\n feat(tc): enable MPMM\n feat(mpmm): add support for MPMM\n feat(amu): enable per-core AMU auxiliary counters\n docs(amu): add AMU documentation\n refactor(amu): refactor enablement and context switching\n refactor(amu): detect auxiliary counters at runtime\n refactor(amu): detect architected counters at runtime\n refactor(amu): conditionally compile auxiliary counter support\n refactor(amu): factor out register accesses\n refactor(amu)!: privatize unused AMU APIs\n refactor(amu)!: remove `PLAT_AMU_GROUP1_COUNTERS_MASK`\n build(amu): introduce `amu.mk`\n build(fconf)!: clean up source collection\n feat(fdt-wrappers): add CPU enumeration utility function\n build(fdt-wrappers): introduce FDT wrappers makefile\n build(bl2): deduplicate sources\n build(bl1): deduplicate sources\n" }, { "commit": "7ab83390649a5b9eaf760b83c15ab9d4f501a422", "tree": "6b3cf12317280a151ace559313ba2e331eb78c76", "parents": [ "5c548dc657aa3d5fb55ecdb3a522713f012088ad", "7186a29bbfe3044d5e8001ddfe1d9238578e0944" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Oct 28 14:28:14 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 28 14:28:14 2021 +0200" }, "message": "Merge \"feat(plat/arm/sgi): increase max BL2 size\" into integration" }, { "commit": "5c548dc657aa3d5fb55ecdb3a522713f012088ad", "tree": "e684ae010cad39755d2acd9d238a3cc0c70b5bfd", "parents": [ "292bb9a76862e37c7562a81ef25ea9a6d62d4cd6", "10bfc77e7b3afce17185114ac66361a0914f7784" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Oct 28 11:53:38 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Oct 28 11:53:38 2021 +0200" }, "message": "Merge \"fix(plat/imx/imx8m/imx8mm): fix FTBFS on SPD\u003dopteed\" into integration" }, { "commit": "cdbbb9f7ecd4687fa52e1c655b631377c24862b9", "tree": "d9b26e8892af3dcda9511d08ed7b4b3c47c135a0", "parents": [ "3e881a8834a955f1e552300bdbf1dafd02ea8f1c" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon May 17 11:25:37 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 28 11:53:16 2021 +0200" }, "message": "fix(fdts stm32mp1): update PLL nodes for ED1/EV1 boards\n\nAlign STM32MP157C-ED1/EV1 boards PLL nodes with what is done\nfor DK boards.\n\nChange-Id: I91be408ea1d9b0474caf4965175df33792b7e11e\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "3e881a8834a955f1e552300bdbf1dafd02ea8f1c", "tree": "41464431deefbfca14d53e4cabdb846b02162ede", "parents": [ "4357db5b17ce6ba7357dd99276f34ab497ce60ef" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon May 17 11:25:37 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 28 11:36:54 2021 +0200" }, "message": "fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards\n\nSet Ethernet source clock on PLL4P. This is required to enable PTP.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: Ia64fbb681d3f04f2b90f373c5eb044f5daa2836c\n" }, { "commit": "4357db5b17ce6ba7357dd99276f34ab497ce60ef", "tree": "f8d8991159106eeaa13d56d27e50e19716feb142", "parents": [ "4955d08de7aa664387d2e5f690e78b85ac23a402" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 16 18:17:32 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 28 11:36:54 2021 +0200" }, "message": "feat(fdts stm32mp1): delete nodes for non-used boot devices\n\nCleanup the BL2 device tree file by removing the nodes for the devices\nthat are not used to boot, depending on compilation flags.\nIn SDMMC boot, the gain for the dtb file is about 2.3kB.\n\nChange-Id: I3ba13e06dd22b52cff96f51db2dac94b532c81ae\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "4955d08de7aa664387d2e5f690e78b85ac23a402", "tree": "3b7cae45a612efe3a4800cece57842ff14cd0dbb", "parents": [ "8cafbda6d3da4dc4204c793fb9d0ca307cc566eb" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Tue Feb 09 10:40:37 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 28 11:36:54 2021 +0200" }, "message": "fix(fdts stm32mp1): use \u0027kHz\u0027 as kilohertz abbreviation\n\nThe kilohertz unit abbreviation should read \u0027kHz\u0027 in DDR\nsettings files of stm32mp15.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: Ifa363094f58dd943ef78c653c3e470a216739b41\n" }, { "commit": "8cafbda6d3da4dc4204c793fb9d0ca307cc566eb", "tree": "1ddc9a9cdeb10b2ea5dd551b647f88d7531dd4cd", "parents": [ "e8a953a9b85806f7324c8c7245435d5b9226c279" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@foss.st.com", "time": "Thu Feb 25 11:03:53 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 28 11:36:54 2021 +0200" }, "message": "refactor(fdts stm32mp1): move STM32MP DDR node\n\nMove the generic part of DDR node in SOC dtsi file.\nDDR dtsi files only include the part configured by CubeMX tool.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@foss.st.com\u003e\nChange-Id: I8c211e9782604da32aeaab98d0ef75fb1cd9c58d\n" }, { "commit": "e8a953a9b85806f7324c8c7245435d5b9226c279", "tree": "b39c7d3a1b1e1162240a4d696a7d089b0ecf2cc1", "parents": [ "292bb9a76862e37c7562a81ef25ea9a6d62d4cd6" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Oct 20 17:22:32 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Oct 28 11:36:54 2021 +0200" }, "message": "feat(fdts stm32mp1): align DT with latest kernel\n\nUpdate STM32MP1 device tree files with kernel 5.15.\n\nChange-Id: Id405a79e18c61e80cd2292a4f87b7b9641df9c82\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "292bb9a76862e37c7562a81ef25ea9a6d62d4cd6", "tree": "6226c4f1522ebe6d716fd48c79b4df316954d7d5", "parents": [ "04deada5d1d1ffa952db5d3831f6ff5ded0b59e5", "700e7685dd4682a929645a79de39f503c9140b2d" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Oct 27 13:30:00 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 27 13:30:00 2021 +0200" }, "message": "Merge \"fix: remove \"experimental\" tag for stable features\" into integration" }, { "commit": "04deada5d1d1ffa952db5d3831f6ff5ded0b59e5", "tree": "ba764e66958f984407383e9e5015ff3d54e2f78d", "parents": [ "387ff949e6a1ce4acf102e8b2252fd76d3a7d317", "3221fce842c0b5aea984bb8dbc1393082bd88a58" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Oct 27 12:59:19 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 27 12:59:19 2021 +0200" }, "message": "Merge \"fix(spmd): revert workaround hafnium as hypervisor\" into integration" }, { "commit": "3221fce842c0b5aea984bb8dbc1393082bd88a58", "tree": "8c96605cada356c9e6aa652adde64002ef95c86b", "parents": [ "0a712819f2fb70a67e23602c8b7aa13ec6e939cc" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Oct 20 15:17:07 2021 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Oct 26 18:19:47 2021 +0200" }, "message": "fix(spmd): revert workaround hafnium as hypervisor\n\nThis change essentially reverts [1] by removing the BL31 workaround\nforcing the dtb address when Hafnium is loaded as an Hypervisor.\n\n[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9569\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I302161d027261448113c66b7fafa9c11620b54ef\n" }, { "commit": "b15f7e2c509d45a68b08f5088736ed444a33791f", "tree": "bdd6a5291adb90db96f3420e1e9e9fb9649ddd44", "parents": [ "c19a82bef08df58350f1b6668e0604ff8a5bd46d" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Oct 14 12:32:52 2021 +0100" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Oct 26 12:15:43 2021 +0100" }, "message": "docs(maintainers): add Chris Kay to AMU and MPMM\n\nChange-Id: I8c775c8cac4fbbb2904952747a9572a71aff37b4\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "c19a82bef08df58350f1b6668e0604ff8a5bd46d", "tree": "be449f004db844d7567f5806b4ceaf7c96762841", "parents": [ "68120783d6d6f99c605e9f746ee0e91e2908feb1" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue May 18 18:49:51 2021 +0100" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Oct 26 12:15:43 2021 +0100" }, "message": "feat(tc): enable MPMM\n\nThis change enables MPMM and adds, to the TC firmware configuration\ndevice tree, the AMU counters representing the \"gears\" for the\nMaximum Power Mitigation Mechanism feature of the Cortex-X2,\nCortex-A710 and Cortex-A510:\n\n- Gear 0: throttle medium and high bandwidth vector and viruses.\n- Gear 1: throttle high bandwidth vector and viruses.\n- Gear 2: throttle power viruses only.\n\nThis ensures these counters are enabled and context-switched as\nexpected.\n\nChange-Id: I6df6e0fe3a5362861aa967a78ab7c34fc4bb8fc3\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "68120783d6d6f99c605e9f746ee0e91e2908feb1", "tree": "2b6298ff714fe1c0abda5f3a06dc9a12513e2c32", "parents": [ "742ca2307f4e9f82cb2c21518819425e5bcc0f90" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Wed May 05 13:38:30 2021 +0100" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Oct 26 12:15:42 2021 +0100" }, "message": "feat(mpmm): add support for MPMM\n\nMPMM - the Maximum Power Mitigation Mechanism - is an optional\nmicroarchitectural feature present on some Armv9-A cores, introduced\nwith the Cortex-X2, Cortex-A710 and Cortex-A510 cores.\n\nMPMM allows the SoC firmware to detect and limit high activity events\nto assist in SoC processor power domain dynamic power budgeting and\nlimit the triggering of whole-rail (i.e. clock chopping) responses to\novercurrent conditions.\n\nThis feature is enabled via the `ENABLE_MPMM` build option.\nConfiguration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or\nby via the plaform-implemented `plat_mpmm_topology` function.\n\nChange-Id: I77da82808ad4744ece8263f0bf215c5a091c3167\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "742ca2307f4e9f82cb2c21518819425e5bcc0f90", "tree": "535f69845871c33790f7aa032f609d24b59c74fc", "parents": [ "9cf75647235ad243acc7a585696ccb7b5ff54b36" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Aug 19 11:21:52 2021 +0100" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Oct 26 12:15:33 2021 +0100" }, "message": "feat(amu): enable per-core AMU auxiliary counters\n\nThis change makes AMU auxiliary counters configurable on a per-core\nbasis, controlled by `ENABLE_AMU_AUXILIARY_COUNTERS`.\n\nAuxiliary counters can be described via the `HW_CONFIG` device tree if\nthe `ENABLE_AMU_FCONF` build option is enabled, or the platform must\notherwise implement the `plat_amu_topology` function.\n\nA new phandle property for `cpu` nodes (`amu`) has been introduced to\nthe `HW_CONFIG` specification to allow CPUs to describe the view of\ntheir own AMU:\n\n```\ncpu0: cpu@0 {\n ...\n\n amu \u003d \u003c\u0026cpu0_amu\u003e;\n};\n```\n\nMultiple cores may share an `amu` handle if they implement the\nsame set of auxiliary counters.\n\nAMU counters are described for one or more AMUs through the use of a new\n`amus` node:\n\n```\namus {\n cpu0_amu: amu-0 {\n #address-cells \u003d \u003c1\u003e;\n #size-cells \u003d \u003c0\u003e;\n\n counter@0 {\n reg \u003d \u003c0\u003e;\n\n enable-at-el3;\n };\n\n counter@n {\n reg \u003d \u003cn\u003e;\n\n ...\n };\n };\n};\n```\n\nThis structure describes the **auxiliary** (group 1) AMU counters.\nArchitected counters have architecturally-defined behaviour, and as\nsuch do not require DTB entries.\n\nThese `counter` nodes support two properties:\n\n- The `reg` property represents the counter register index.\n- The presence of the `enable-at-el3` property determines whether\n the firmware should enable the counter prior to exiting EL3.\n\nChange-Id: Ie43aee010518c5725a3b338a4899b0857caf4c28\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "9cf75647235ad243acc7a585696ccb7b5ff54b36", "tree": "e4aca782e2c64e96ebd47557cbdc02b1e4a86c6a", "parents": [ "e747a59be4ab8e9fa6edc7f4fb04478cd0f823c2" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Aug 17 16:24:57 2021 +0100" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Oct 26 12:14:34 2021 +0100" }, "message": "docs(amu): add AMU documentation\n\nThis change adds some documentation on the AMU and its purpose. This is\nexpanded on in later patches.\n\nChange-Id: If2834676790938d8da5ea2ceba37b674f6cc0f01\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "e747a59be4ab8e9fa6edc7f4fb04478cd0f823c2", "tree": "74b840049d3433b72ae04967f275319fce65eb2f", "parents": [ "31d3cc2570dd61ac30efab030708ef32fcc987e5" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Mon May 24 20:35:26 2021 +0100" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Tue Oct 26 12:14:33 2021 +0100" }, "message": "refactor(amu): refactor enablement and context switching\n\nThis change represents a general refactoring to clean up old code that\nhas been adapted to account for changes required to enable dynamic\nauxiliary counters.\n\nChange-Id: Ia85e0518f3f65c765f07b34b67744fc869b9070d\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" } ], "next": "31d3cc2570dd61ac30efab030708ef32fcc987e5" }