| From: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> |
| Subject: [PATCH 4/4] arm: dts: owl-s500: Add RoseapplePi |
| To: Rob Herring <robh+dt@kernel.org>, |
| Andreas Fรคrber <afaerber@suse.de>, |
| Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
| Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, |
| linux-arm-kernel@lists.infradead.org |
| Date: Mon, 15 Jun 2020 03:19:11 +0300 (10 weeks, 3 days, 20 hours ago) |
| X-Mailer: git-send-email 2.27.0 |
| |
| Add a Device Tree for the RoseapplePi SBC. |
| |
| Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> |
| Signed-off-by: Peter Korsgaard <peter@korsgaard.com> |
| --- |
| arch/arm/boot/dts/Makefile | 1 + |
| arch/arm/boot/dts/owl-s500-roseapplepi.dts | 47 ++++++++++++++++++++++ |
| 2 files changed, 48 insertions(+) |
| create mode 100644 arch/arm/boot/dts/owl-s500-roseapplepi.dts |
| |
| diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile |
| index e8dd99201397..d0712e7275da 100644 |
| --- a/arch/arm/boot/dts/Makefile |
| +++ b/arch/arm/boot/dts/Makefile |
| @@ -856,6 +856,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ |
| dtb-$(CONFIG_ARCH_ACTIONS) += \ |
| owl-s500-cubieboard6.dtb \ |
| owl-s500-guitar-bb-rev-b.dtb \ |
| + owl-s500-roseapplepi.dtb \ |
| owl-s500-sparky.dtb |
| dtb-$(CONFIG_ARCH_PRIMA2) += \ |
| prima2-evb.dtb |
| diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts |
| new file mode 100644 |
| index 000000000000..c61fbaa3821e |
| --- /dev/null |
| +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts |
| @@ -0,0 +1,47 @@ |
| +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| +/* |
| + * Roseapple Pi |
| + * |
| + * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> |
| + */ |
| + |
| +/dts-v1/; |
| + |
| +#include "owl-s500.dtsi" |
| + |
| +/ { |
| + compatible = "roseapplepi,roseapplepi", "actions,s500"; |
| + model = "Roseapple Pi"; |
| + |
| + aliases { |
| + serial2 = &uart2; |
| + }; |
| + |
| + chosen { |
| + stdout-path = "serial2:115200n8"; |
| + }; |
| + |
| + memory@0 { |
| + device_type = "memory"; |
| + reg = <0x0 0x80000000>; /* 2GB */ |
| + }; |
| + |
| + uart2_clk: uart2-clk { |
| + compatible = "fixed-clock"; |
| + clock-frequency = <921600>; |
| + #clock-cells = <0>; |
| + }; |
| +}; |
| + |
| +&twd_timer { |
| + status = "okay"; |
| +}; |
| + |
| +&timer { |
| + clocks = <&hosc>; |
| +}; |
| + |
| +&uart2 { |
| + status = "okay"; |
| + clocks = <&uart2_clk>; |
| +}; |
| -- |
| 2.27.0 |
| |
| |